<p>Elyes HAOUAS has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/27908">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">src/soc: Fix typo<br><br>Change-Id: I8053d0f0863aa4d93692487f1ca802195c2d475f<br>Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr><br>---<br>M src/soc/intel/broadwell/me_status.c<br>M src/soc/intel/cannonlake/chip.h<br>M src/soc/intel/skylake/chip.h<br>M src/soc/nvidia/tegra124/chip.h<br>M src/soc/nvidia/tegra124/sdram_lp0.c<br>M src/soc/nvidia/tegra210/chip.h<br>M src/soc/qualcomm/ipq806x/uart.c<br>M src/soc/rockchip/rk3288/clock.c<br>M src/soc/rockchip/rk3399/clock.c<br>9 files changed, 9 insertions(+), 9 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/08/27908/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/soc/intel/broadwell/me_status.c b/src/soc/intel/broadwell/me_status.c</span><br><span>index 819e94c..2055dd8 100644</span><br><span>--- a/src/soc/intel/broadwell/me_status.c</span><br><span>+++ b/src/soc/intel/broadwell/me_status.c</span><br><span>@@ -315,7 +315,7 @@</span><br><span> pci_write_config32(PCH_DEV_ME, PCI_ME_H_GS,</span><br><span> ME_HSIO_MESSAGE | ME_HSIO_CMD_GETHSIOVER);</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- /* Must wait for ME acknowledgement */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Must wait for ME acknowledgment */</span><br><span> for (count = ME_RETRY; count > 0; --count) {</span><br><span> me_read_dword_ptr(&hfs, PCI_ME_HFS);</span><br><span> if (hfs.bios_msg_ack)</span><br><span>diff --git a/src/soc/intel/cannonlake/chip.h b/src/soc/intel/cannonlake/chip.h</span><br><span>index 4704d1c..2dc8c2c 100644</span><br><span>--- a/src/soc/intel/cannonlake/chip.h</span><br><span>+++ b/src/soc/intel/cannonlake/chip.h</span><br><span>@@ -156,7 +156,7 @@</span><br><span> </span><br><span> /* PCIe Root Ports */</span><br><span> uint8_t PcieRpEnable[CONFIG_MAX_ROOT_PORTS];</span><br><span style="color: hsl(0, 100%, 40%);">- /* PCIe ouput clocks type to Pcie devices.</span><br><span style="color: hsl(120, 100%, 40%);">+ /* PCIe output clocks type to Pcie devices.</span><br><span> * 0-23: PCH rootport, 0x70: LAN, 0x80: unspecified but in use,</span><br><span> * 0xFF: not used */</span><br><span> uint8_t PcieClkSrcUsage[CONFIG_MAX_ROOT_PORTS];</span><br><span>diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h</span><br><span>index a6e03ca..a147d92 100644</span><br><span>--- a/src/soc/intel/skylake/chip.h</span><br><span>+++ b/src/soc/intel/skylake/chip.h</span><br><span>@@ -116,7 +116,7 @@</span><br><span> /* Estimated maximum platform power in Watts */</span><br><span> u16 psys_pmax;</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- /* Wether to ignore VT-d support of the SKU */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Whether to ignore VT-d support of the SKU */</span><br><span> int ignore_vtd;</span><br><span> </span><br><span> /*</span><br><span>diff --git a/src/soc/nvidia/tegra124/chip.h b/src/soc/nvidia/tegra124/chip.h</span><br><span>index 6994ca2..d9ab67b 100644</span><br><span>--- a/src/soc/nvidia/tegra124/chip.h</span><br><span>+++ b/src/soc/nvidia/tegra124/chip.h</span><br><span>@@ -88,7 +88,7 @@</span><br><span> </span><br><span> int pixel_clock;</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- /* The minimum link configuraton settings */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* The minimum link configuration settings */</span><br><span> u32 lane_count;</span><br><span> u32 enhanced_framing;</span><br><span> u32 link_bw;</span><br><span>diff --git a/src/soc/nvidia/tegra124/sdram_lp0.c b/src/soc/nvidia/tegra124/sdram_lp0.c</span><br><span>index d5019d9..536ad31 100644</span><br><span>--- a/src/soc/nvidia/tegra124/sdram_lp0.c</span><br><span>+++ b/src/soc/nvidia/tegra124/sdram_lp0.c</span><br><span>@@ -23,7 +23,7 @@</span><br><span> #include <stdlib.h></span><br><span> </span><br><span> /*</span><br><span style="color: hsl(0, 100%, 40%);">- * This function reads SDRAM parameters (and a few CLK_RST regsiter values) from</span><br><span style="color: hsl(120, 100%, 40%);">+ * This function reads SDRAM parameters (and a few CLK_RST register values) from</span><br><span> * the common BCT format and writes them into PMC scratch registers (where the</span><br><span> * BootROM expects them on LP0 resume). Since those store the same values in a</span><br><span> * different format, we follow a "translation table" taken from Nvidia's U-Boot</span><br><span>diff --git a/src/soc/nvidia/tegra210/chip.h b/src/soc/nvidia/tegra210/chip.h</span><br><span>index 6a2aa84..75d2497 100644</span><br><span>--- a/src/soc/nvidia/tegra210/chip.h</span><br><span>+++ b/src/soc/nvidia/tegra210/chip.h</span><br><span>@@ -76,7 +76,7 @@</span><br><span> int hpd_plug_min_us;</span><br><span> int hpd_irq_min_us;</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- /* The minimum link configuraton settings */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* The minimum link configuration settings */</span><br><span> u32 lane_count;</span><br><span> u32 enhanced_framing;</span><br><span> u32 link_bw;</span><br><span>diff --git a/src/soc/qualcomm/ipq806x/uart.c b/src/soc/qualcomm/ipq806x/uart.c</span><br><span>index 8d4a225..3af7958 100644</span><br><span>--- a/src/soc/qualcomm/ipq806x/uart.c</span><br><span>+++ b/src/soc/qualcomm/ipq806x/uart.c</span><br><span>@@ -329,7 +329,7 @@</span><br><span> GSBI_PROTOCOL_CODE_I2C_UART << GSBI_CTRL_REG_PROTOCOL_CODE_S);</span><br><span> write32(MSM_BOOT_UART_DM_CSR(dm_base), UART_DM_CLK_RX_TX_BIT_RATE);</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- /* Intialize UART_DM */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Initialize UART_DM */</span><br><span> msm_boot_uart_dm_init(dm_base);</span><br><span> }</span><br><span> </span><br><span>diff --git a/src/soc/rockchip/rk3288/clock.c b/src/soc/rockchip/rk3288/clock.c</span><br><span>index 74151e8..1b1c135 100644</span><br><span>--- a/src/soc/rockchip/rk3288/clock.c</span><br><span>+++ b/src/soc/rockchip/rk3288/clock.c</span><br><span>@@ -469,7 +469,7 @@</span><br><span> </span><br><span> /* i2s source clock: gpll</span><br><span> i2s0_outclk_sel: clk_i2s</span><br><span style="color: hsl(0, 100%, 40%);">- i2s0_clk_sel: divider ouput from fraction</span><br><span style="color: hsl(120, 100%, 40%);">+ i2s0_clk_sel: divider output from fraction</span><br><span> i2s0_pll_div_con: 0*/</span><br><span> write32(&cru_ptr->cru_clksel_con[4],</span><br><span> RK_CLRSETBITS(1 << 15 | 1 << 12 | 3 << 8 | 0x7f << 0,</span><br><span>diff --git a/src/soc/rockchip/rk3399/clock.c b/src/soc/rockchip/rk3399/clock.c</span><br><span>index 5422deb..0b8c83f 100644</span><br><span>--- a/src/soc/rockchip/rk3399/clock.c</span><br><span>+++ b/src/soc/rockchip/rk3399/clock.c</span><br><span>@@ -804,7 +804,7 @@</span><br><span> int v;</span><br><span> </span><br><span> /**</span><br><span style="color: hsl(0, 100%, 40%);">- * clk_i2s0_sel: divider ouput from fraction</span><br><span style="color: hsl(120, 100%, 40%);">+ * clk_i2s0_sel: divider output from fraction</span><br><span> * clk_i2s0_pll_sel source clock: cpll</span><br><span> * clk_i2s0_div_con: 1 (div+1)</span><br><span> */</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/27908">change 27908</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/27908"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I8053d0f0863aa4d93692487f1ca802195c2d475f </div>
<div style="display:none"> Gerrit-Change-Number: 27908 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Elyes HAOUAS <ehaouas@noos.fr> </div>