<p>Maulik V Vaghela has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/27905">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">mb/intel/coffeelake: Enable 32MB rom compilation for Coffeelake U<br><br>Coffeelake U has 32MB flash chip support. Adding fmd file and enabling<br>CFL U board's Kconfig to output 32MB rom file.<br><br>Change-Id: I21431b7ac813781b12b95f80c6f8960a78caf4bc<br>Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com><br>---<br>M src/mainboard/intel/coffeelake_rvp/Kconfig<br>A src/mainboard/intel/coffeelake_rvp/chromeos_32MB.fmd<br>2 files changed, 45 insertions(+), 1 deletion(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/27905/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/mainboard/intel/coffeelake_rvp/Kconfig b/src/mainboard/intel/coffeelake_rvp/Kconfig</span><br><span>index 9dcb02c..bd6eef9 100644</span><br><span>--- a/src/mainboard/intel/coffeelake_rvp/Kconfig</span><br><span>+++ b/src/mainboard/intel/coffeelake_rvp/Kconfig</span><br><span>@@ -2,7 +2,8 @@</span><br><span> </span><br><span> config BOARD_SPECIFIC_OPTIONS</span><br><span> def_bool y</span><br><span style="color: hsl(0, 100%, 40%);">- select BOARD_ROMSIZE_KB_16384</span><br><span style="color: hsl(120, 100%, 40%);">+ select BOARD_ROMSIZE_KB_16384 if !BOARD_INTEL_COFFEELAKE_RVPU</span><br><span style="color: hsl(120, 100%, 40%);">+ select BOARD_ROMSIZE_KB_32768 if BOARD_INTEL_COFFEELAKE_RVPU</span><br><span> select GENERIC_SPD_BIN</span><br><span> select HAVE_ACPI_RESUME</span><br><span> select HAVE_ACPI_TABLES</span><br><span>diff --git a/src/mainboard/intel/coffeelake_rvp/chromeos_32MB.fmd b/src/mainboard/intel/coffeelake_rvp/chromeos_32MB.fmd</span><br><span>new file mode 100644</span><br><span>index 0000000..be6bfc0</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/intel/coffeelake_rvp/chromeos_32MB.fmd</span><br><span>@@ -0,0 +1,43 @@</span><br><span style="color: hsl(120, 100%, 40%);">+FLASH@0xfe000000 0x2000000 {</span><br><span style="color: hsl(120, 100%, 40%);">+ SI_ALL@0x0 0x1081000 {</span><br><span style="color: hsl(120, 100%, 40%);">+ SI_DESC@0x0 0x1000</span><br><span style="color: hsl(120, 100%, 40%);">+ SI_EC@0x1000 0x80000</span><br><span style="color: hsl(120, 100%, 40%);">+ SI_ME@0x81000 0x1000000</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ SI_BIOS@0x1400000 0xC00000 {</span><br><span style="color: hsl(120, 100%, 40%);">+ RW_SECTION_A@0x0 0x2d0000 {</span><br><span style="color: hsl(120, 100%, 40%);">+ VBLOCK_A@0x0 0x10000</span><br><span style="color: hsl(120, 100%, 40%);">+ FW_MAIN_A(CBFS)@0x10000 0x2bffc0</span><br><span style="color: hsl(120, 100%, 40%);">+ RW_FWID_A@0x2cffc0 0x40</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ RW_SECTION_B@0x2d0000 0x2d0000 {</span><br><span style="color: hsl(120, 100%, 40%);">+ VBLOCK_B@0x0 0x10000</span><br><span style="color: hsl(120, 100%, 40%);">+ FW_MAIN_B(CBFS)@0x10000 0x2bffc0</span><br><span style="color: hsl(120, 100%, 40%);">+ RW_FWID_B@0x2cffc0 0x40</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ RW_MISC@0x5a0000 0x30000 {</span><br><span style="color: hsl(120, 100%, 40%);">+ UNIFIED_MRC_CACHE@0x0 0x20000 {</span><br><span style="color: hsl(120, 100%, 40%);">+ RECOVERY_MRC_CACHE@0x0 0x10000</span><br><span style="color: hsl(120, 100%, 40%);">+ RW_MRC_CACHE@0x10000 0x10000</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ RW_ELOG@0x20000 0x4000</span><br><span style="color: hsl(120, 100%, 40%);">+ RW_SHARED@0x24000 0x4000 {</span><br><span style="color: hsl(120, 100%, 40%);">+ SHARED_DATA@0x0 0x2000</span><br><span style="color: hsl(120, 100%, 40%);">+ VBLOCK_DEV@0x2000 0x2000</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ RW_VPD@0x28000 0x2000</span><br><span style="color: hsl(120, 100%, 40%);">+ RW_NVRAM@0x2a000 0x6000</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ RW_LEGACY(CBFS)@0x5d0000 0x200000</span><br><span style="color: hsl(120, 100%, 40%);">+ WP_RO@0x7d0000 0x430000 {</span><br><span style="color: hsl(120, 100%, 40%);">+ RO_VPD@0x0 0x4000</span><br><span style="color: hsl(120, 100%, 40%);">+ RO_SECTION@0x4000 0x42c000 {</span><br><span style="color: hsl(120, 100%, 40%);">+ FMAP@0x0 0x800</span><br><span style="color: hsl(120, 100%, 40%);">+ RO_FRID@0x800 0x40</span><br><span style="color: hsl(120, 100%, 40%);">+ RO_FRID_PAD@0x840 0x7c0</span><br><span style="color: hsl(120, 100%, 40%);">+ GBB@0x1000 0xef000</span><br><span style="color: hsl(120, 100%, 40%);">+ COREBOOT(CBFS)@0xf0000 0x33c000</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/27905">change 27905</a>. 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<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I21431b7ac813781b12b95f80c6f8960a78caf4bc </div>
<div style="display:none"> Gerrit-Change-Number: 27905 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Maulik V Vaghela <maulik.v.vaghela@intel.com> </div>