<p>Arthur Heymans has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/27873">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">nb/intel/*: Use 2M TSEG instead of 8M on pre-arrandale hardware<br><br>8M was set in the assumption that at least 4M was needed for IED<br>(Intel Enhanced Debug) , but this is not true.<br><br>The SMRR MTRR's need to have TSEG aligned to its size which is easier when TSEG<br>is only 2M. Also at most 6M of RAM more becomes available for use.<br><br>Change-Id: I4b114c8dc13699b3c034f0a7060181d9d590737b<br>Signed-off-by: Arthur Heymans <arthur@aheymans.xyz><br>---<br>M src/northbridge/intel/gm45/raminit.c<br>M src/northbridge/intel/i945/early_init.c<br>M src/northbridge/intel/pineview/raminit.c<br>M src/northbridge/intel/x4x/raminit_ddr23.c<br>4 files changed, 9 insertions(+), 9 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/27873/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/northbridge/intel/gm45/raminit.c b/src/northbridge/intel/gm45/raminit.c</span><br><span>index 08f954d..61a2b4e 100644</span><br><span>--- a/src/northbridge/intel/gm45/raminit.c</span><br><span>+++ b/src/northbridge/intel/gm45/raminit.c</span><br><span>@@ -1242,12 +1242,12 @@</span><br><span> </span><br><span> uma_sizem = (gms_sizek + gsm_sizek) >> 10;</span><br><span> }</span><br><span style="color: hsl(0, 100%, 40%);">- /* TSEG 8M */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* TSEG 2M */</span><br><span> u8 reg8 = pci_read_config8(PCI_DEV(0, 0, 0), D0F0_ESMRAMC);</span><br><span> reg8 &= ~0x7;</span><br><span style="color: hsl(0, 100%, 40%);">- reg8 |= (2 << 1) | (1 << 0); /* 8M and TSEG_Enable */</span><br><span style="color: hsl(120, 100%, 40%);">+ reg8 |= (1 << 1) | (1 << 0); /* 2M and TSEG_Enable */</span><br><span> pci_write_config8(PCI_DEV(0, 0, 0), D0F0_ESMRAMC, reg8);</span><br><span style="color: hsl(0, 100%, 40%);">- uma_sizem += 8;</span><br><span style="color: hsl(120, 100%, 40%);">+ uma_sizem += 2;</span><br><span> }</span><br><span> </span><br><span> const unsigned int mmio_size = get_mmio_size();</span><br><span>diff --git a/src/northbridge/intel/i945/early_init.c b/src/northbridge/intel/i945/early_init.c</span><br><span>index 7de2c73..8e68af5 100644</span><br><span>--- a/src/northbridge/intel/i945/early_init.c</span><br><span>+++ b/src/northbridge/intel/i945/early_init.c</span><br><span>@@ -194,7 +194,7 @@</span><br><span> </span><br><span> reg8 = pci_read_config8(PCI_DEV(0, 0, 0), ESMRAMC);</span><br><span> reg8 &= ~0x7;</span><br><span style="color: hsl(0, 100%, 40%);">- reg8 |= (2 << 1) | (1 << 0); /* 8M and TSEG_Enable */</span><br><span style="color: hsl(120, 100%, 40%);">+ reg8 |= (1 << 1) | (1 << 0); /* 2M and TSEG_Enable */</span><br><span> pci_write_config8(PCI_DEV(0, 0, 0), ESMRAMC, reg8);</span><br><span> </span><br><span> /* Set C0000-FFFFF to access RAM on both reads and writes */</span><br><span>diff --git a/src/northbridge/intel/pineview/raminit.c b/src/northbridge/intel/pineview/raminit.c</span><br><span>index 66f0a10..59eadc3 100644</span><br><span>--- a/src/northbridge/intel/pineview/raminit.c</span><br><span>+++ b/src/northbridge/intel/pineview/raminit.c</span><br><span>@@ -2039,7 +2039,7 @@</span><br><span> gttsize = ggc_to_gtt[(ggc & 0x300) >> 8];</span><br><span> tom = s->channel_capacity[0];</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- tsegsize = 0x8; // 8MB</span><br><span style="color: hsl(120, 100%, 40%);">+ tsegsize = 0x2; // 2MB</span><br><span> mmiosize = 0x400; // 1GB</span><br><span> </span><br><span> reclaim = false;</span><br><span>@@ -2076,7 +2076,7 @@</span><br><span> </span><br><span> u8 reg8 = pci_read_config8(PCI_DEV(0, 0, 0), ESMRAMC);</span><br><span> reg8 &= ~0x7;</span><br><span style="color: hsl(0, 100%, 40%);">- reg8 |= (2 << 1) | (1 << 0); /* 8M and TSEG_Enable */</span><br><span style="color: hsl(120, 100%, 40%);">+ reg8 |= (1 << 1) | (1 << 0); /* 2M and TSEG_Enable */</span><br><span> pci_write_config8(PCI_DEV(0, 0, 0), ESMRAMC, reg8);</span><br><span> </span><br><span> printk(BIOS_DEBUG, "GBSM (igd) = verified %08x (written %08x)\n",</span><br><span>diff --git a/src/northbridge/intel/x4x/raminit_ddr23.c b/src/northbridge/intel/x4x/raminit_ddr23.c</span><br><span>index c445cad..a788dd9 100644</span><br><span>--- a/src/northbridge/intel/x4x/raminit_ddr23.c</span><br><span>+++ b/src/northbridge/intel/x4x/raminit_ddr23.c</span><br><span>@@ -1722,7 +1722,7 @@</span><br><span> ggc = pci_read_config16(PCI_DEV(0, 0, 0), 0x52);</span><br><span> gfxsize = ggc2uma[(ggc & 0xf0) >> 4];</span><br><span> gttsize = ggc2gtt[(ggc & 0xf00) >> 8];</span><br><span style="color: hsl(0, 100%, 40%);">- tsegsize = 8; // 8MB TSEG</span><br><span style="color: hsl(120, 100%, 40%);">+ tsegsize = 2; // 2MB TSEG</span><br><span> mmiosize = 0x800; // 2GB MMIO</span><br><span> umasizem = gfxsize + gttsize + tsegsize;</span><br><span> mmiostart = 0x1000 - mmiosize + umasizem;</span><br><span>@@ -1759,10 +1759,10 @@</span><br><span> pci_write_config16(PCI_DEV(0, 0, 0), 0xa2, touud);</span><br><span> pci_write_config32(PCI_DEV(0, 0, 0), 0xa4, gfxbase << 20);</span><br><span> pci_write_config32(PCI_DEV(0, 0, 0), 0xa8, gttbase << 20);</span><br><span style="color: hsl(0, 100%, 40%);">- /* Enable and set tseg size to 8M */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Enable and set tseg size to 2M */</span><br><span> reg8 = pci_read_config8(PCI_DEV(0, 0, 0), D0F0_ESMRAMC);</span><br><span> reg8 &= ~0x7;</span><br><span style="color: hsl(0, 100%, 40%);">- reg8 |= (2 << 1) | (1 << 0); /* 8M and TSEG_Enable */</span><br><span style="color: hsl(120, 100%, 40%);">+ reg8 |= (1 << 1) | (1 << 0); /* 2M and TSEG_Enable */</span><br><span> pci_write_config8(PCI_DEV(0, 0, 0), D0F0_ESMRAMC, reg8);</span><br><span> pci_write_config32(PCI_DEV(0, 0, 0), 0xac, tsegbase << 20);</span><br><span> }</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/27873">change 27873</a>. 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<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I4b114c8dc13699b3c034f0a7060181d9d590737b </div>
<div style="display:none"> Gerrit-Change-Number: 27873 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Arthur Heymans <arthur@aheymans.xyz> </div>