<p>Elyes HAOUAS has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/27875">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">src: Fix typo<br><br>Change-Id: Iadc28d1632aa9b7d0b028c229049a348d5c07882<br>Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr><br>---<br>M src/ec/google/chromeec/ec_commands.h<br>M src/northbridge/intel/gm45/ram_calc.c<br>M src/northbridge/intel/i945/ram_calc.c<br>M src/northbridge/intel/pineview/ram_calc.c<br>M src/northbridge/intel/x4x/ram_calc.c<br>5 files changed, 5 insertions(+), 5 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/27875/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/ec/google/chromeec/ec_commands.h b/src/ec/google/chromeec/ec_commands.h</span><br><span>index 730be09..bafaa89 100644</span><br><span>--- a/src/ec/google/chromeec/ec_commands.h</span><br><span>+++ b/src/ec/google/chromeec/ec_commands.h</span><br><span>@@ -426,7 +426,7 @@</span><br><span>  * parent structure that the alignment will still be true given the packing of</span><br><span>  * the parent structure.  This is particularly important if the sub-structure</span><br><span>  * will be passed as a pointer to another function, since that function will</span><br><span style="color: hsl(0, 100%, 40%);">- * not know about the misaligment caused by the parent structure's packing.</span><br><span style="color: hsl(120, 100%, 40%);">+ * not know about the misalignment caused by the parent structure's packing.</span><br><span>  *</span><br><span>  * Also be very careful using __packed - particularly when nesting non-packed</span><br><span>  * structures inside packed ones.  In fact, DO NOT use __packed directly;</span><br><span>diff --git a/src/northbridge/intel/gm45/ram_calc.c b/src/northbridge/intel/gm45/ram_calc.c</span><br><span>index 0e95341..5af3e16 100644</span><br><span>--- a/src/northbridge/intel/gm45/ram_calc.c</span><br><span>+++ b/src/northbridge/intel/gm45/ram_calc.c</span><br><span>@@ -107,7 +107,7 @@</span><br><span> }</span><br><span> </span><br><span> /* Depending of UMA and TSEG configuration, TSEG might start at any</span><br><span style="color: hsl(0, 100%, 40%);">- * 1 MiB aligment. As this may cause very greedy MTRR setup, push</span><br><span style="color: hsl(120, 100%, 40%);">+ * 1 MiB alignment. As this may cause very greedy MTRR setup, push</span><br><span>  * CBMEM top downwards to 4 MiB boundary.</span><br><span>  */</span><br><span> void *cbmem_top(void)</span><br><span>diff --git a/src/northbridge/intel/i945/ram_calc.c b/src/northbridge/intel/i945/ram_calc.c</span><br><span>index 15ba7f4..7ee7198 100644</span><br><span>--- a/src/northbridge/intel/i945/ram_calc.c</span><br><span>+++ b/src/northbridge/intel/i945/ram_calc.c</span><br><span>@@ -59,7 +59,7 @@</span><br><span> }</span><br><span> </span><br><span> /* Depending of UMA and TSEG configuration, TSEG might start at any</span><br><span style="color: hsl(0, 100%, 40%);">- * 1 MiB aligment. As this may cause very greedy MTRR setup, push</span><br><span style="color: hsl(120, 100%, 40%);">+ * 1 MiB alignment. As this may cause very greedy MTRR setup, push</span><br><span>  * CBMEM top downwards to 4 MiB boundary.</span><br><span>  */</span><br><span> void *cbmem_top(void)</span><br><span>diff --git a/src/northbridge/intel/pineview/ram_calc.c b/src/northbridge/intel/pineview/ram_calc.c</span><br><span>index d116709..62855c2 100644</span><br><span>--- a/src/northbridge/intel/pineview/ram_calc.c</span><br><span>+++ b/src/northbridge/intel/pineview/ram_calc.c</span><br><span>@@ -95,7 +95,7 @@</span><br><span> }</span><br><span> </span><br><span> /* Depending of UMA and TSEG configuration, TSEG might start at any</span><br><span style="color: hsl(0, 100%, 40%);">- * 1 MiB aligment. As this may cause very greedy MTRR setup, push</span><br><span style="color: hsl(120, 100%, 40%);">+ * 1 MiB alignment. As this may cause very greedy MTRR setup, push</span><br><span>  * CBMEM top downwards to 4 MiB boundary.</span><br><span>  */</span><br><span> void *cbmem_top(void)</span><br><span>diff --git a/src/northbridge/intel/x4x/ram_calc.c b/src/northbridge/intel/x4x/ram_calc.c</span><br><span>index 49afdc3..1f1c13f 100644</span><br><span>--- a/src/northbridge/intel/x4x/ram_calc.c</span><br><span>+++ b/src/northbridge/intel/x4x/ram_calc.c</span><br><span>@@ -93,7 +93,7 @@</span><br><span> }</span><br><span> </span><br><span> /* Depending of UMA and TSEG configuration, TSEG might start at any</span><br><span style="color: hsl(0, 100%, 40%);">- * 1 MiB aligment. As this may cause very greedy MTRR setup, push</span><br><span style="color: hsl(120, 100%, 40%);">+ * 1 MiB alignment. As this may cause very greedy MTRR setup, push</span><br><span>  * CBMEM top downwards to 4 MiB boundary.</span><br><span>  */</span><br><span> void *cbmem_top(void)</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/27875">change 27875</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/27875"/><meta itemprop="name" content="View Change"/></div></div>

<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: Iadc28d1632aa9b7d0b028c229049a348d5c07882 </div>
<div style="display:none"> Gerrit-Change-Number: 27875 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Elyes HAOUAS <ehaouas@noos.fr> </div>