<p>Raul Rangel has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/27876">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">soc/amd/stoneyridge: Set undocumented misc register<br><br>By setting this register in bootblock AmdInitEnv will no longer trigger<br>a reset in romstage. This fixes a few vboot test failures and also<br>speeds up boot time.<br><br>BUG=b:111610455<br>TEST=Built grunt and made sure bootblock only happens once on cold boot,<br>and S3 resume.<br><br>Change-Id: Ie19f7a14deaef45ac63156bec6946273c1b9447e<br>Signed-off-by: Raul E Rangel <rrangel@chromium.org><br>---<br>M src/soc/amd/stoneyridge/southbridge.c<br>1 file changed, 21 insertions(+), 3 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/76/27876/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/soc/amd/stoneyridge/southbridge.c b/src/soc/amd/stoneyridge/southbridge.c</span><br><span>index 348d5f1..c75aefd 100644</span><br><span>--- a/src/soc/amd/stoneyridge/southbridge.c</span><br><span>+++ b/src/soc/amd/stoneyridge/southbridge.c</span><br><span>@@ -556,7 +556,7 @@</span><br><span>  }</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void setup_spread_spectrum(void)</span><br><span style="color: hsl(120, 100%, 40%);">+static void setup_spread_spectrum(int *reboot)</span><br><span> {</span><br><span>       uint16_t rstcfg = pm_read16(PWR_RESET_CFG);</span><br><span> </span><br><span>@@ -606,11 +606,24 @@</span><br><span>      cntl1 |= CG1PLL_FBDIV_TEST;</span><br><span>  misc_write32(MISC_CLK_CNTL1, cntl1);</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-        soft_reset();</span><br><span style="color: hsl(120, 100%, 40%);">+ *reboot |= 1;</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static void setup_misc(int *reboot)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+    uint32_t reg = misc_read32(0x50);</span><br><span style="color: hsl(120, 100%, 40%);">+     if (!(reg & (1 << 16))) {</span><br><span style="color: hsl(120, 100%, 40%);">+           reg |= 1 << 16;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+               misc_write32(0x50, reg);</span><br><span style="color: hsl(120, 100%, 40%);">+              *reboot |= 1;</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span> }</span><br><span> </span><br><span> void bootblock_fch_early_init(void)</span><br><span> {</span><br><span style="color: hsl(120, 100%, 40%);">+        int reboot = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span>    sb_enable_rom();</span><br><span>     sb_lpc_port80();</span><br><span>     sb_lpc_decode();</span><br><span>@@ -619,7 +632,12 @@</span><br><span>      sb_disable_4dw_burst(); /* Must be disabled on CZ(ST) */</span><br><span>     sb_acpi_mmio_decode();</span><br><span>       sb_enable_cf9_io();</span><br><span style="color: hsl(0, 100%, 40%);">-     setup_spread_spectrum();</span><br><span style="color: hsl(120, 100%, 40%);">+      setup_spread_spectrum(&reboot);</span><br><span style="color: hsl(120, 100%, 40%);">+   setup_misc(&reboot);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+    if (reboot)</span><br><span style="color: hsl(120, 100%, 40%);">+           soft_reset();</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span>      sb_enable_legacy_io();</span><br><span>       enable_aoac_devices();</span><br><span> }</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/27876">change 27876</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/27876"/><meta itemprop="name" content="View Change"/></div></div>

<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: Ie19f7a14deaef45ac63156bec6946273c1b9447e </div>
<div style="display:none"> Gerrit-Change-Number: 27876 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Raul Rangel <rrangel@chromium.org> </div>