<p><a href="https://review.coreboot.org/27875">View Change</a></p><p>40 comments:</p><ul style="list-style: none; padding: 0;"><li style="margin: 0; padding: 0;"><p><a href="https://review.coreboot.org/#/c/27875/2/src/commonlib/include/commonlib/timestamp_serialized.h">File src/commonlib/include/commonlib/timestamp_serialized.h:</a></p><ul style="list-style: none; padding: 0;"><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/27875/2/src/commonlib/include/commonlib/timestamp_serialized.h@243">Patch Set #2, Line 243:</a> <code style="font-family:monospace,monospace"> { TS_ME_INFORM_DRAM_WAIT, "waiting for ME acknowledgment of raminit"},</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li></ul></li><li style="margin: 0; padding: 0;"><p><a href="https://review.coreboot.org/#/c/27875/2/src/mainboard/advansus/a785e-i/resourcemap.c">File src/mainboard/advansus/a785e-i/resourcemap.c:</a></p><ul style="list-style: none; padding: 0;"><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/27875/2/src/mainboard/advansus/a785e-i/resourcemap.c@122">Patch Set #2, Line 122:</a> <code style="font-family:monospace,monospace"> * This field defines the upp address bits of a 40-bit address that</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li></ul></li><li style="margin: 0; padding: 0;"><p><a href="https://review.coreboot.org/#/c/27875/2/src/mainboard/amd/bimini_fam10/resourcemap.c">File src/mainboard/amd/bimini_fam10/resourcemap.c:</a></p><ul style="list-style: none; padding: 0;"><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/27875/2/src/mainboard/amd/bimini_fam10/resourcemap.c@123">Patch Set #2, Line 123:</a> <code style="font-family:monospace,monospace"> * This field defines the upp address bits of a 40-bit address that</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li></ul></li><li style="margin: 0; padding: 0;"><p><a href="https://review.coreboot.org/#/c/27875/2/src/mainboard/amd/mahogany_fam10/resourcemap.c">File src/mainboard/amd/mahogany_fam10/resourcemap.c:</a></p><ul style="list-style: none; padding: 0;"><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/27875/2/src/mainboard/amd/mahogany_fam10/resourcemap.c@124">Patch Set #2, Line 124:</a> <code style="font-family:monospace,monospace"> * This field defines the upp address bits of a 40-bit address that</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li></ul></li><li style="margin: 0; padding: 0;"><p><a href="https://review.coreboot.org/#/c/27875/2/src/mainboard/amd/serengeti_cheetah_fam10/resourcemap.c">File src/mainboard/amd/serengeti_cheetah_fam10/resourcemap.c:</a></p><ul style="list-style: none; padding: 0;"><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/27875/2/src/mainboard/amd/serengeti_cheetah_fam10/resourcemap.c@122">Patch Set #2, Line 122:</a> <code style="font-family:monospace,monospace"> * This field defines the upp address bits of a 40-bit address that</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li></ul></li><li style="margin: 0; padding: 0;"><p><a href="https://review.coreboot.org/#/c/27875/2/src/mainboard/amd/south_station/mainboard.c">File src/mainboard/amd/south_station/mainboard.c:</a></p><ul style="list-style: none; padding: 0;"><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/27875/2/src/mainboard/amd/south_station/mainboard.c@21">Patch Set #2, Line 21:</a> <code style="font-family:monospace,monospace">#include "SBPLATFORM.h" /* Platform Specific Definitions */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">please, no space before tabs</p></li></ul></li><li style="margin: 0; padding: 0;"><p><a href="https://review.coreboot.org/#/c/27875/2/src/mainboard/amd/tilapia_fam10/resourcemap.c">File src/mainboard/amd/tilapia_fam10/resourcemap.c:</a></p><ul style="list-style: none; padding: 0;"><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/27875/2/src/mainboard/amd/tilapia_fam10/resourcemap.c@122">Patch Set #2, Line 122:</a> <code style="font-family:monospace,monospace"> * This field defines the upp address bits of a 40-bit address that</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li></ul></li><li style="margin: 0; padding: 0;"><p><a href="https://review.coreboot.org/#/c/27875/2/src/mainboard/amd/torpedo/gpio.h">File src/mainboard/amd/torpedo/gpio.h:</a></p><ul style="list-style: none; padding: 0;"><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/27875/2/src/mainboard/amd/torpedo/gpio.h@301">Patch Set #2, Line 301:</a> <code style="font-family:monospace,monospace">#define GPIO_189_SELECT FUNCTION1 // USED AS AC_OK RECEIVER, INPUT, low active</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/27875/2/src/mainboard/amd/torpedo/gpio.h@302">Patch Set #2, Line 302:</a> <code style="font-family:monospace,monospace">#define GPIO_190_SELECT FUNCTION1 // USED TO MONITER INTERRUPT FROM BATT CHARGER, INPUT</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li></ul></li><li style="margin: 0; padding: 0;"><p><a href="https://review.coreboot.org/#/c/27875/2/src/mainboard/amd/union_station/mainboard.c">File src/mainboard/amd/union_station/mainboard.c:</a></p><ul style="list-style: none; padding: 0;"><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/27875/2/src/mainboard/amd/union_station/mainboard.c@20">Patch Set #2, Line 20:</a> <code style="font-family:monospace,monospace">#include "SBPLATFORM.h" /* Platform Specific Definitions */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">please, no space before tabs</p></li></ul></li><li style="margin: 0; padding: 0;"><p><a href="https://review.coreboot.org/#/c/27875/2/src/mainboard/asus/kcma-d8/resourcemap.c">File src/mainboard/asus/kcma-d8/resourcemap.c:</a></p><ul style="list-style: none; padding: 0;"><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/27875/2/src/mainboard/asus/kcma-d8/resourcemap.c@127">Patch Set #2, Line 127:</a> <code style="font-family:monospace,monospace"> * This field defines the upp address bits of a 40-bit address that</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/27875/2/src/mainboard/asus/kcma-d8/resourcemap.c@382">Patch Set #2, Line 382:</a> <code style="font-family:monospace,monospace"> * This field defines the upp address bits of a 40-bit address that</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li></ul></li><li style="margin: 0; padding: 0;"><p><a href="https://review.coreboot.org/#/c/27875/2/src/mainboard/asus/kfsn4-dre/resourcemap.c">File src/mainboard/asus/kfsn4-dre/resourcemap.c:</a></p><ul style="list-style: none; padding: 0;"><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/27875/2/src/mainboard/asus/kfsn4-dre/resourcemap.c@127">Patch Set #2, Line 127:</a> <code style="font-family:monospace,monospace"> * This field defines the upp address bits of a 40-bit address that</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li></ul></li><li style="margin: 0; padding: 0;"><p><a href="https://review.coreboot.org/#/c/27875/2/src/mainboard/asus/kgpe-d16/resourcemap.c">File src/mainboard/asus/kgpe-d16/resourcemap.c:</a></p><ul style="list-style: none; padding: 0;"><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/27875/2/src/mainboard/asus/kgpe-d16/resourcemap.c@127">Patch Set #2, Line 127:</a> <code style="font-family:monospace,monospace"> * This field defines the upp address bits of a 40-bit address that</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/27875/2/src/mainboard/asus/kgpe-d16/resourcemap.c@382">Patch Set #2, Line 382:</a> <code style="font-family:monospace,monospace"> * This field defines the upp address bits of a 40-bit address that</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li></ul></li><li style="margin: 0; padding: 0;"><p><a href="https://review.coreboot.org/#/c/27875/2/src/mainboard/asus/m4a78-em/resourcemap.c">File src/mainboard/asus/m4a78-em/resourcemap.c:</a></p><ul style="list-style: none; padding: 0;"><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/27875/2/src/mainboard/asus/m4a78-em/resourcemap.c@124">Patch Set #2, Line 124:</a> <code style="font-family:monospace,monospace"> * This field defines the upp address bits of a 40-bit address that</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li></ul></li><li style="margin: 0; padding: 0;"><p><a href="https://review.coreboot.org/#/c/27875/2/src/mainboard/asus/m4a785-m/resourcemap.c">File src/mainboard/asus/m4a785-m/resourcemap.c:</a></p><ul style="list-style: none; padding: 0;"><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/27875/2/src/mainboard/asus/m4a785-m/resourcemap.c@124">Patch Set #2, Line 124:</a> <code style="font-family:monospace,monospace"> * This field defines the upp address bits of a 40-bit address that</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li></ul></li><li style="margin: 0; padding: 0;"><p><a href="https://review.coreboot.org/#/c/27875/2/src/mainboard/asus/m5a88-v/resourcemap.c">File src/mainboard/asus/m5a88-v/resourcemap.c:</a></p><ul style="list-style: none; padding: 0;"><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/27875/2/src/mainboard/asus/m5a88-v/resourcemap.c@122">Patch Set #2, Line 122:</a> <code style="font-family:monospace,monospace"> * This field defines the upp address bits of a 40-bit address that</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li></ul></li><li style="margin: 0; padding: 0;"><p><a href="https://review.coreboot.org/#/c/27875/2/src/mainboard/avalue/eax-785e/resourcemap.c">File src/mainboard/avalue/eax-785e/resourcemap.c:</a></p><ul style="list-style: none; padding: 0;"><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/27875/2/src/mainboard/avalue/eax-785e/resourcemap.c@122">Patch Set #2, Line 122:</a> <code style="font-family:monospace,monospace"> * This field defines the upp address bits of a 40-bit address that</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li></ul></li><li style="margin: 0; padding: 0;"><p><a href="https://review.coreboot.org/#/c/27875/2/src/mainboard/gigabyte/ma785gm/resourcemap.c">File src/mainboard/gigabyte/ma785gm/resourcemap.c:</a></p><ul style="list-style: none; padding: 0;"><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/27875/2/src/mainboard/gigabyte/ma785gm/resourcemap.c@124">Patch Set #2, Line 124:</a> <code style="font-family:monospace,monospace"> * This field defines the upp address bits of a 40-bit address that</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li></ul></li><li style="margin: 0; padding: 0;"><p><a href="https://review.coreboot.org/#/c/27875/2/src/mainboard/gigabyte/ma785gmt/resourcemap.c">File src/mainboard/gigabyte/ma785gmt/resourcemap.c:</a></p><ul style="list-style: none; padding: 0;"><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/27875/2/src/mainboard/gigabyte/ma785gmt/resourcemap.c@124">Patch Set #2, Line 124:</a> <code style="font-family:monospace,monospace"> * This field defines the upp address bits of a 40-bit address that</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li></ul></li><li style="margin: 0; padding: 0;"><p><a href="https://review.coreboot.org/#/c/27875/2/src/mainboard/gigabyte/ma78gm/resourcemap.c">File src/mainboard/gigabyte/ma78gm/resourcemap.c:</a></p><ul style="list-style: none; padding: 0;"><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/27875/2/src/mainboard/gigabyte/ma78gm/resourcemap.c@124">Patch Set #2, Line 124:</a> <code style="font-family:monospace,monospace"> * This field defines the upp address bits of a 40-bit address that</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li></ul></li><li style="margin: 0; padding: 0;"><p><a href="https://review.coreboot.org/#/c/27875/2/src/mainboard/iei/kino-780am2-fam10/resourcemap.c">File src/mainboard/iei/kino-780am2-fam10/resourcemap.c:</a></p><ul style="list-style: none; padding: 0;"><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/27875/2/src/mainboard/iei/kino-780am2-fam10/resourcemap.c@124">Patch Set #2, Line 124:</a> <code style="font-family:monospace,monospace"> * This field defines the upp address bits of a 40-bit address that</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li></ul></li><li style="margin: 0; padding: 0;"><p><a href="https://review.coreboot.org/#/c/27875/2/src/mainboard/jetway/pa78vm5/resourcemap.c">File src/mainboard/jetway/pa78vm5/resourcemap.c:</a></p><ul style="list-style: none; padding: 0;"><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/27875/2/src/mainboard/jetway/pa78vm5/resourcemap.c@125">Patch Set #2, Line 125:</a> <code style="font-family:monospace,monospace"> * This field defines the upp address bits of a 40-bit address that</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li></ul></li><li style="margin: 0; padding: 0;"><p><a href="https://review.coreboot.org/#/c/27875/2/src/mainboard/msi/ms9652_fam10/resourcemap.c">File src/mainboard/msi/ms9652_fam10/resourcemap.c:</a></p><ul style="list-style: none; padding: 0;"><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/27875/2/src/mainboard/msi/ms9652_fam10/resourcemap.c@125">Patch Set #2, Line 125:</a> <code style="font-family:monospace,monospace"> * This field defines the upp address bits of a 40-bit address that</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li></ul></li><li style="margin: 0; padding: 0;"><p><a href="https://review.coreboot.org/#/c/27875/2/src/mainboard/siemens/mc_tcu3/ptn3460.c">File src/mainboard/siemens/mc_tcu3/ptn3460.c:</a></p><ul style="list-style: none; padding: 0;"><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/27875/2/src/mainboard/siemens/mc_tcu3/ptn3460.c@117">Patch Set #2, Line 117:</a> <code style="font-family:monospace,monospace"> status = i2c_write(PTN_I2C_CONTROLLER, PTN_SLAVE_ADR, PTN_CONFIG_OFF + 5,</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/27875/2/src/mainboard/siemens/mc_tcu3/ptn3460.c@143">Patch Set #2, Line 143:</a> <code style="font-family:monospace,monospace"> status = i2c_write(PTN_I2C_CONTROLLER, PTN_SLAVE_ADR, PTN_CONFIG_OFF + 5,</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/27875/2/src/mainboard/siemens/mc_tcu3/ptn3460.c@171">Patch Set #2, Line 171:</a> <code style="font-family:monospace,monospace"> status = i2c_write(PTN_I2C_CONTROLLER, PTN_SLAVE_ADR, PTN_CONFIG_OFF + 4,</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li></ul></li><li style="margin: 0; padding: 0;"><p><a href="https://review.coreboot.org/#/c/27875/2/src/mainboard/supermicro/h8dmr_fam10/resourcemap.c">File src/mainboard/supermicro/h8dmr_fam10/resourcemap.c:</a></p><ul style="list-style: none; padding: 0;"><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/27875/2/src/mainboard/supermicro/h8dmr_fam10/resourcemap.c@125">Patch Set #2, Line 125:</a> <code style="font-family:monospace,monospace"> * This field defines the upp address bits of a 40-bit address that</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li></ul></li><li style="margin: 0; padding: 0;"><p><a href="https://review.coreboot.org/#/c/27875/2/src/mainboard/supermicro/h8qme_fam10/resourcemap.c">File src/mainboard/supermicro/h8qme_fam10/resourcemap.c:</a></p><ul style="list-style: none; padding: 0;"><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/27875/2/src/mainboard/supermicro/h8qme_fam10/resourcemap.c@125">Patch Set #2, Line 125:</a> <code style="font-family:monospace,monospace"> * This field defines the upp address bits of a 40-bit address that</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li></ul></li><li style="margin: 0; padding: 0;"><p><a href="https://review.coreboot.org/#/c/27875/2/src/mainboard/supermicro/h8scm_fam10/resourcemap.c">File src/mainboard/supermicro/h8scm_fam10/resourcemap.c:</a></p><ul style="list-style: none; padding: 0;"><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/27875/2/src/mainboard/supermicro/h8scm_fam10/resourcemap.c@124">Patch Set #2, Line 124:</a> <code style="font-family:monospace,monospace"> * This field defines the upp address bits of a 40-bit address that</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li></ul></li><li style="margin: 0; padding: 0;"><p><a href="https://review.coreboot.org/#/c/27875/2/src/mainboard/tyan/s2912_fam10/resourcemap.c">File src/mainboard/tyan/s2912_fam10/resourcemap.c:</a></p><ul style="list-style: none; padding: 0;"><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/27875/2/src/mainboard/tyan/s2912_fam10/resourcemap.c@125">Patch Set #2, Line 125:</a> <code style="font-family:monospace,monospace"> * This field defines the upp address bits of a 40-bit address that</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li></ul></li><li style="margin: 0; padding: 0;"><p><a href="https://review.coreboot.org/#/c/27875/2/src/northbridge/amd/amdfam10/amdfam10.h">File src/northbridge/amd/amdfam10/amdfam10.h:</a></p><ul style="list-style: none; padding: 0;"><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/27875/2/src/northbridge/amd/amdfam10/amdfam10.h@371">Patch Set #2, Line 371:</a> <code style="font-family:monospace,monospace"> for DDR2 400, 533, 667, F2x[1,0]9C_x[02:01], [03], [06:05], [07] control timing of all DIMMs</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/27875/2/src/northbridge/amd/amdfam10/amdfam10.h@372">Patch Set #2, Line 372:</a> <code style="font-family:monospace,monospace"> for DDR2 800, DDR3 800, 1067, 1333, 1600, F2x[1,0]9C_x[02:01], [03], [06:05], [07] control timing of DIMM0</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/27875/2/src/northbridge/amd/amdfam10/amdfam10.h@373">Patch Set #2, Line 373:</a> <code style="font-family:monospace,monospace"> F2x[1,0]9C_x[102:101], [103], [106:105], [107] control timing of DIMM1</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li></ul></li><li style="margin: 0; padding: 0;"><p><a href="https://review.coreboot.org/#/c/27875/2/src/northbridge/amd/amdht/h3ffeat.h">File src/northbridge/amd/amdht/h3ffeat.h:</a></p><ul style="list-style: none; padding: 0;"><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/27875/2/src/northbridge/amd/amdht/h3ffeat.h@160">Patch Set #2, Line 160:</a> <code style="font-family:monospace,monospace"> /* The number of coherent links coming off of each node (i.e. the 'Degree' of the node) */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li></ul></li><li style="margin: 0; padding: 0;"><p><a href="https://review.coreboot.org/#/c/27875/2/src/northbridge/amd/amdht/h3ncmn.c">File src/northbridge/amd/amdht/h3ncmn.c:</a></p><ul style="list-style: none; padding: 0;"><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/27875/2/src/northbridge/amd/amdht/h3ncmn.c@1119">Patch Set #2, Line 1119:</a> <code style="font-family:monospace,monospace"> * InitComplete = 1,Link initialization is complete</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li></ul></li><li style="margin: 0; padding: 0;"><p><a href="https://review.coreboot.org/#/c/27875/2/src/northbridge/amd/amdmct/mct_ddr3/s3utils.c">File src/northbridge/amd/amdmct/mct_ddr3/s3utils.c:</a></p><ul style="list-style: none; padding: 0;"><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/27875/2/src/northbridge/amd/amdmct/mct_ddr3/s3utils.c@849">Patch Set #2, Line 849:</a> <code style="font-family:monospace,monospace"> /* Restore DRAM Address/Timing Control Register */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li></ul></li><li style="margin: 0; padding: 0;"><p><a href="https://review.coreboot.org/#/c/27875/2/src/northbridge/amd/amdmct/wrappers/mcti_d.c">File src/northbridge/amd/amdmct/wrappers/mcti_d.c:</a></p><ul style="list-style: none; padding: 0;"><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/27875/2/src/northbridge/amd/amdmct/wrappers/mcti_d.c@172">Patch Set #2, Line 172:</a> <code style="font-family:monospace,monospace"> //val = 1; /* Ignore faulty SPD checksum (DIMM will still be disabled), continue current node initialization */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li></ul></li><li style="margin: 0; padding: 0;"><p><a href="https://review.coreboot.org/#/c/27875/2/src/superio/smsc/sio1036/sio1036_early_init.c">File src/superio/smsc/sio1036/sio1036_early_init.c:</a></p><ul style="list-style: none; padding: 0;"><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/27875/2/src/superio/smsc/sio1036/sio1036_early_init.c@76">Patch Set #2, Line 76:</a> <code style="font-family:monospace,monospace"> pnp_write_config (dev, 0x0A, 0x00 | IR_OUTPUT_MUX);</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">space prohibited between function name and open parenthesis '('</p></li></ul></li></ul><p>To view, visit <a href="https://review.coreboot.org/27875">change 27875</a>. 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<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: comment </div>
<div style="display:none"> Gerrit-Change-Id: Iadc28d1632aa9b7d0b028c229049a348d5c07882 </div>
<div style="display:none"> Gerrit-Change-Number: 27875 </div>
<div style="display:none"> Gerrit-PatchSet: 2 </div>
<div style="display:none"> Gerrit-Owner: Elyes HAOUAS <ehaouas@noos.fr> </div>
<div style="display:none"> Gerrit-Reviewer: Martin Roth <martinroth@google.com> </div>
<div style="display:none"> Gerrit-Reviewer: build bot (Jenkins) <no-reply@coreboot.org> </div>
<div style="display:none"> Gerrit-Comment-Date: Mon, 06 Aug 2018 17:34:27 +0000 </div>
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