<p>Arthur Heymans has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/27871">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">nb/intel/*: Account for cbmem_top alignment<br><br>Having cbmem floating between two ram regions is a bad idea and some<br>payloads (e.g. tianocore) even bail out on this. To overcome this issue mark the<br>region between tom and cbmem as uma.<br><br>Change-Id: Ifab37b0003f09a680024d5b155ab0bb157920952<br>Signed-off-by: Arthur Heymans <arthur@aheymans.xyz><br>---<br>M src/northbridge/intel/gm45/northbridge.c<br>M src/northbridge/intel/i945/northbridge.c<br>M src/northbridge/intel/pineview/northbridge.c<br>M src/northbridge/intel/x4x/northbridge.c<br>4 files changed, 49 insertions(+), 4 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/27871/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/northbridge/intel/gm45/northbridge.c b/src/northbridge/intel/gm45/northbridge.c</span><br><span>index e14f843..d946553 100644</span><br><span>--- a/src/northbridge/intel/gm45/northbridge.c</span><br><span>+++ b/src/northbridge/intel/gm45/northbridge.c</span><br><span>@@ -13,6 +13,7 @@</span><br><span>  * GNU General Public License for more details.</span><br><span>  */</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+#include <cbmem.h></span><br><span> #include <console/console.h></span><br><span> #include <arch/io.h></span><br><span> #include <stdint.h></span><br><span>@@ -72,7 +73,7 @@</span><br><span> static void mch_domain_read_resources(struct device *dev)</span><br><span> {</span><br><span>     u64 tom, touud;</span><br><span style="color: hsl(0, 100%, 40%);">- u32 tomk, tolud, uma_sizek = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+       u32 tomk, tolud, uma_sizek = 0, delta_cbmem;</span><br><span>         u32 pcie_config_base, pcie_config_size;</span><br><span> </span><br><span>  /* Total Memory 2GB example:</span><br><span>@@ -138,6 +139,15 @@</span><br><span>  tomk -= tseg_sizek;</span><br><span>  uma_sizek += tseg_sizek;</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+  /* cbmem_top can be shifted downwards due to aligment.</span><br><span style="color: hsl(120, 100%, 40%);">+           Mark the region between cbmem_top and tomk as unusable */</span><br><span style="color: hsl(120, 100%, 40%);">+  delta_cbmem = tomk - ((uint32_t)cbmem_top() >> 10);</span><br><span style="color: hsl(120, 100%, 40%);">+     tomk -= delta_cbmem;</span><br><span style="color: hsl(120, 100%, 40%);">+  uma_sizek += delta_cbmem;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+   printk(BIOS_DEBUG, "Unused RAM between cbmem_top and TOM: 0x%xK\n",</span><br><span style="color: hsl(120, 100%, 40%);">+        delta_cbmem);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span>       printk(BIOS_INFO, "Available memory below 4GB: %uM\n", tomk >> 10);</span><br><span> </span><br><span>      /* Report the memory regions */</span><br><span>diff --git a/src/northbridge/intel/i945/northbridge.c b/src/northbridge/intel/i945/northbridge.c</span><br><span>index d3539b8..b6e1515 100644</span><br><span>--- a/src/northbridge/intel/i945/northbridge.c</span><br><span>+++ b/src/northbridge/intel/i945/northbridge.c</span><br><span>@@ -13,6 +13,7 @@</span><br><span>  * GNU General Public License for more details.</span><br><span>  */</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+#include <cbmem.h></span><br><span> #include <console/console.h></span><br><span> #include <arch/io.h></span><br><span> #include <stdint.h></span><br><span>@@ -62,7 +63,7 @@</span><br><span>        uint32_t pci_tolm, tseg_sizek;</span><br><span>       uint8_t tolud;</span><br><span>       uint16_t reg16;</span><br><span style="color: hsl(0, 100%, 40%);">- unsigned long long tomk, tomk_stolen;</span><br><span style="color: hsl(120, 100%, 40%);">+ unsigned long long tomk, tomk_stolen, cbmem_topk, delta_cbmem;</span><br><span>       uint64_t uma_memory_base = 0, uma_memory_size = 0;</span><br><span>   uint64_t tseg_memory_base = 0, tseg_memory_size = 0;</span><br><span> </span><br><span>@@ -102,6 +103,17 @@</span><br><span>      tseg_memory_base = tomk_stolen * 1024ULL;</span><br><span>    tseg_memory_size = tseg_sizek * 1024ULL;</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+  /* cbmem_top can be shifted downwards due to aligment.</span><br><span style="color: hsl(120, 100%, 40%);">+           Mark the region between cbmem_top and tomk as unusable */</span><br><span style="color: hsl(120, 100%, 40%);">+  cbmem_topk = ((uint32_t)cbmem_top() >> 10);</span><br><span style="color: hsl(120, 100%, 40%);">+     delta_cbmem = tomk_stolen - cbmem_topk;</span><br><span style="color: hsl(120, 100%, 40%);">+       tomk_stolen -= delta_cbmem;</span><br><span style="color: hsl(120, 100%, 40%);">+   uma_sizek += delta_cbmem;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+   printk(BIOS_DEBUG, "Unused RAM between cbmem_top and TOM: 0x%xK\n",</span><br><span style="color: hsl(120, 100%, 40%);">+        delta_cbmem);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span>     /* The following needs to be 2 lines, otherwise the second</span><br><span>    * number is always 0</span><br><span>         */</span><br><span>@@ -113,6 +125,7 @@</span><br><span>    ram_resource(dev, 4, 768, (tomk - 768));</span><br><span>     uma_resource(dev, 5, uma_memory_base >> 10, uma_memory_size >> 10);</span><br><span>      mmio_resource(dev, 6, tseg_memory_base >> 10, tseg_memory_size >> 10);</span><br><span style="color: hsl(120, 100%, 40%);">+    uma_resource(dev, 7, cbmem_topk, delta_cbmem);</span><br><span> </span><br><span>   assign_resources(dev->link_list);</span><br><span> }</span><br><span>diff --git a/src/northbridge/intel/pineview/northbridge.c b/src/northbridge/intel/pineview/northbridge.c</span><br><span>index 4775b15..0c04b35 100644</span><br><span>--- a/src/northbridge/intel/pineview/northbridge.c</span><br><span>+++ b/src/northbridge/intel/pineview/northbridge.c</span><br><span>@@ -14,6 +14,7 @@</span><br><span>  * GNU General Public License for more details.</span><br><span>  */</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+#include <cbmem.h></span><br><span> #include <console/console.h></span><br><span> #include <arch/io.h></span><br><span> #include <stdint.h></span><br><span>@@ -55,7 +56,7 @@</span><br><span> {</span><br><span>         u64 tom, touud;</span><br><span>      u32 tomk, tolud, tseg_sizek;</span><br><span style="color: hsl(0, 100%, 40%);">-    u32 pcie_config_base, pcie_config_size;</span><br><span style="color: hsl(120, 100%, 40%);">+       u32 pcie_config_base, pcie_config_size, delta_cbmem;</span><br><span>         u16 index;</span><br><span>   const u32 top32memk = 4 * (GiB / KiB);</span><br><span> </span><br><span>@@ -100,6 +101,17 @@</span><br><span>    /* Subtract TSEG size */</span><br><span>     tseg_sizek = gtt_basek - tseg_basek;</span><br><span>         tomk -= tseg_sizek;</span><br><span style="color: hsl(120, 100%, 40%);">+   printk(BIOS_DEBUG, "TSEG decoded, subtracting %dM\n", tseg_sizek >> 10);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+    /* cbmem_top can be shifted downwards due to aligment.</span><br><span style="color: hsl(120, 100%, 40%);">+           Mark the region between cbmem_top and tomk as unusable */</span><br><span style="color: hsl(120, 100%, 40%);">+  delta_cbmem = tomk - ((uint32_t)cbmem_top() >> 10);</span><br><span style="color: hsl(120, 100%, 40%);">+     tomk -= delta_cbmem;</span><br><span style="color: hsl(120, 100%, 40%);">+  uma_sizek += delta_cbmem;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+   printk(BIOS_DEBUG, "Unused RAM between cbmem_top and TOMK: 0x%xK\n",</span><br><span style="color: hsl(120, 100%, 40%);">+               delta_cbmem);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> </span><br><span>   /* Report the memory regions */</span><br><span>      ram_resource(dev, index++, 0, 640);</span><br><span>diff --git a/src/northbridge/intel/x4x/northbridge.c b/src/northbridge/intel/x4x/northbridge.c</span><br><span>index d1926b2..aba5c54 100644</span><br><span>--- a/src/northbridge/intel/x4x/northbridge.c</span><br><span>+++ b/src/northbridge/intel/x4x/northbridge.c</span><br><span>@@ -14,6 +14,7 @@</span><br><span>  * GNU General Public License for more details.</span><br><span>  */</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+#include <cbmem.h></span><br><span> #include <console/console.h></span><br><span> #include <arch/io.h></span><br><span> #include <stdint.h></span><br><span>@@ -35,7 +36,7 @@</span><br><span> {</span><br><span>   u8 index, reg8;</span><br><span>      u64 tom, touud;</span><br><span style="color: hsl(0, 100%, 40%);">- u32 tomk, tseg_sizek = 0, tolud;</span><br><span style="color: hsl(120, 100%, 40%);">+      u32 tomk, tseg_sizek = 0, tolud, delta_cbmem;</span><br><span>        u32 pcie_config_base, pcie_config_size;</span><br><span>      u32 uma_sizek = 0;</span><br><span> </span><br><span>@@ -100,6 +101,15 @@</span><br><span> </span><br><span>    printk(BIOS_DEBUG, "%dM\n", tseg_sizek >> 10);</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+    /* cbmem_top can be shifted downwards due to aligment.</span><br><span style="color: hsl(120, 100%, 40%);">+           Mark the region between cbmem_top and tomk as unusable */</span><br><span style="color: hsl(120, 100%, 40%);">+  delta_cbmem = tomk - ((uint32_t)cbmem_top() >> 10);</span><br><span style="color: hsl(120, 100%, 40%);">+     tomk -= delta_cbmem;</span><br><span style="color: hsl(120, 100%, 40%);">+  uma_sizek += delta_cbmem;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+   printk(BIOS_DEBUG, "Unused RAM between cbmem_top and TOM: 0x%xK\n",</span><br><span style="color: hsl(120, 100%, 40%);">+        delta_cbmem);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span>       printk(BIOS_INFO, "Available memory below 4GB: %uM\n", tomk >> 10);</span><br><span> </span><br><span>      /* Report the memory regions */</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/27871">change 27871</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/27871"/><meta itemprop="name" content="View Change"/></div></div>

<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: Ifab37b0003f09a680024d5b155ab0bb157920952 </div>
<div style="display:none"> Gerrit-Change-Number: 27871 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Arthur Heymans <arthur@aheymans.xyz> </div>