<p>Elyes HAOUAS has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/27865">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">mb/kontron/986lcd-m: Use common pnp_{enter,exit} functions<br><br>Some unneeded includes are also removed.<br><br>Change-Id: Icd518c46d8503d11d24466c30840d7e514e9a05d<br>Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr><br>---<br>M src/mainboard/kontron/986lcd-m/romstage.c<br>1 file changed, 13 insertions(+), 31 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/27865/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/mainboard/kontron/986lcd-m/romstage.c b/src/mainboard/kontron/986lcd-m/romstage.c</span><br><span>index f7e8131..5996045 100644</span><br><span>--- a/src/mainboard/kontron/986lcd-m/romstage.c</span><br><span>+++ b/src/mainboard/kontron/986lcd-m/romstage.c</span><br><span>@@ -16,25 +16,21 @@</span><br><span> /* __PRE_RAM__ means: use "unsigned" for device, not a struct. */</span><br><span> </span><br><span> #include <stdint.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <string.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <lib.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <arch/acpi.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <cbmem.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <halt.h></span><br><span> #include <timestamp.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <arch/io.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <console/console.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <cpu/intel/romstage.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <cpu/x86/bist.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <cpu/x86/lapic.h></span><br><span> #include <device/pci_def.h></span><br><span> #include <device/pnp_def.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <cpu/x86/lapic.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <pc80/mc146818rtc.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include "option_table.h"</span><br><span style="color: hsl(0, 100%, 40%);">-#include <console/console.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <cpu/x86/bist.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <cpu/intel/romstage.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <halt.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <superio/winbond/w83627thg/w83627thg.h></span><br><span> #include <northbridge/intel/i945/i945.h></span><br><span> #include <northbridge/intel/i945/raminit.h></span><br><span> #include <southbridge/intel/i82801gx/i82801gx.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <superio/winbond/common/winbond.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <superio/winbond/w83627thg/w83627thg.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include "option_table.h"</span><br><span> </span><br><span> #define SERIAL_DEV PNP_DEV(0x2e, W83627THG_SP1)</span><br><span> </span><br><span>@@ -62,20 +58,6 @@</span><br><span> pci_write_config32(PCI_DEV(0, 0x1f, 0), GEN4_DEC, 0x00000301);</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-/* TODO: superio code should really not be in mainboard */</span><br><span style="color: hsl(0, 100%, 40%);">-static void pnp_enter_func_mode(pnp_devfn_t dev)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- u16 port = dev >> 8;</span><br><span style="color: hsl(0, 100%, 40%);">- outb(0x87, port);</span><br><span style="color: hsl(0, 100%, 40%);">- outb(0x87, port);</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-static void pnp_exit_func_mode(pnp_devfn_t dev)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- u16 port = dev >> 8;</span><br><span style="color: hsl(0, 100%, 40%);">- outb(0xaa, port);</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span> /* This box has two superios, so enabling serial becomes slightly excessive.</span><br><span> * We disable a lot of stuff to make sure that there are no conflicts between</span><br><span> * the two. Also set up the GPIOs from the beginning. This is the "no schematic</span><br><span>@@ -86,7 +68,7 @@</span><br><span> pnp_devfn_t dev;</span><br><span> </span><br><span> dev = PNP_DEV(0x2e, W83627THG_SP1);</span><br><span style="color: hsl(0, 100%, 40%);">- pnp_enter_func_mode(dev);</span><br><span style="color: hsl(120, 100%, 40%);">+ pnp_enter_conf_state(dev);</span><br><span> </span><br><span> pnp_write_config(dev, 0x24, 0xc6); /* PNPCSV */</span><br><span> </span><br><span>@@ -146,10 +128,10 @@</span><br><span> pnp_set_iobase(dev, PNP_IDX_IO0, 0xa00);</span><br><span> pnp_set_enable(dev, 1);</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- pnp_exit_func_mode(dev);</span><br><span style="color: hsl(120, 100%, 40%);">+ pnp_exit_conf_state(dev);</span><br><span> </span><br><span> dev = PNP_DEV(0x4e, W83627THG_SP1);</span><br><span style="color: hsl(0, 100%, 40%);">- pnp_enter_func_mode(dev);</span><br><span style="color: hsl(120, 100%, 40%);">+ pnp_enter_conf_state(dev);</span><br><span> </span><br><span> pnp_set_logical_device(dev); /* Set COM3 to sane non-conflicting values */</span><br><span> pnp_set_enable(dev, 0);</span><br><span>@@ -178,7 +160,7 @@</span><br><span> pnp_set_iobase(dev, PNP_IDX_IO0, 0x00);</span><br><span> pnp_set_iobase(dev, PNP_IDX_IO1, 0x00);</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- pnp_exit_func_mode(dev);</span><br><span style="color: hsl(120, 100%, 40%);">+ pnp_exit_conf_state(dev);</span><br><span> }</span><br><span> </span><br><span> static void rcba_config(void)</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/27865">change 27865</a>. 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<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: Icd518c46d8503d11d24466c30840d7e514e9a05d </div>
<div style="display:none"> Gerrit-Change-Number: 27865 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Elyes HAOUAS <ehaouas@noos.fr> </div>