<p>Patrick Georgi <strong>merged</strong> this change.</p><p><a href="https://review.coreboot.org/27807">View Change</a></p><div style="white-space:pre-wrap">Approvals:
build bot (Jenkins): Verified
Furquan Shaikh: Looks good to me, approved
</div><pre style="font-family: monospace,monospace; white-space: pre-wrap;">mb/google/poppy/variants/rammus: add gpio setting<br><br>The gpio setting is based on the proto board schematics<br><br>BUG=b:111579386<br>BRANCH=Master<br>TEST=Build pass<br><br>Change-Id: I20fc081d372b8686f6128a7e85276f9c6798b199<br>Signed-off-by: Zhuohao Lee <zhuohao@chromium.org><br>Reviewed-on: https://review.coreboot.org/27807<br>Tested-by: build bot (Jenkins) <no-reply@coreboot.org><br>Reviewed-by: Furquan Shaikh <furquan@google.com><br>---<br>M src/mainboard/google/poppy/variants/rammus/Makefile.inc<br>A src/mainboard/google/poppy/variants/rammus/gpio.c<br>2 files changed, 391 insertions(+), 0 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/mainboard/google/poppy/variants/rammus/Makefile.inc b/src/mainboard/google/poppy/variants/rammus/Makefile.inc</span><br><span>index edfacea..eed7c44 100644</span><br><span>--- a/src/mainboard/google/poppy/variants/rammus/Makefile.inc</span><br><span>+++ b/src/mainboard/google/poppy/variants/rammus/Makefile.inc</span><br><span>@@ -1,5 +1,8 @@</span><br><span> SPD_SOURCES = empty # 0b0000</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+bootblock-y += gpio.c</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> romstage-y += memory.c</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+ramstage-y += gpio.c</span><br><span> ramstage-y += nhlt.c</span><br><span>diff --git a/src/mainboard/google/poppy/variants/rammus/gpio.c b/src/mainboard/google/poppy/variants/rammus/gpio.c</span><br><span>new file mode 100644</span><br><span>index 0000000..771a3f4</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/google/poppy/variants/rammus/gpio.c</span><br><span>@@ -0,0 +1,388 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright 2018 Google Inc.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <baseboard/gpio.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <baseboard/variants.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <commonlib/helpers.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* Pad configuration in ramstage */</span><br><span style="color: hsl(120, 100%, 40%);">+/* Leave eSPI pins untouched from default settings */</span><br><span style="color: hsl(120, 100%, 40%);">+static const struct pad_config gpio_table[] = {</span><br><span style="color: hsl(120, 100%, 40%);">+ /* A0 : RCIN# ==> NC(T0804) */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NC(GPP_A0),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* A1 : ESPI_IO0 */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* A2 : ESPI_IO1 */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* A3 : ESPI_IO2 */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* A4 : ESPI_IO3 */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* A5 : ESPI_CS# */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* A6 : SERIRQ ==> NC(T0805) */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NC(GPP_A6),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* A7 : PIRQA# ==> NC(T0501) */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NC(GPP_A7),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* A8 : CLKRUN# ==> NC(T0806) */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NC(GPP_A8),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* A9 : ESPI_CLK */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* A10 : CLKOUT_LPC1 ==> NC */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NC(GPP_A10),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* A11 : PME# ==> NC(T0913) */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NC(GPP_A11),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* A12 : BM_BUSY# ==> NC */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NC(GPP_A12),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* A13 : SUSWARN# ==> SUSWARN_L */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* A14 : ESPI_RESET# */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* A15 : SUSACK# ==> SUSACK_L */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF(GPP_A15, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* A16 : SD_1P8_SEL ==> SD_PWR_1800_SEL */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* A17 : SD_PWR_EN# ==> EN_SD_SOCKET_PWR_L */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF(GPP_A17, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* A18 : ISH_GP0 ==> NC */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NC(GPP_A18),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* A19 : ISH_GP1 ==> NC */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NC(GPP_A19),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* A20 : ISH_GP2 ==> NC */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NC(GPP_A20),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* A21 : ISH_GP3 ==> NC */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NC(GPP_A21),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* A22 : ISH_GP4 ==> NC */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NC(GPP_A22),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* A23 : ISH_GP5 ==> NC */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NC(GPP_A23),</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* B0 : CORE_VID0 ==> WLAN_PCIE_WAKE_L */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPI_ACPI_SCI(GPP_B0, NONE, DEEP, INVERT),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* B1 : CORE_VID1 ==> NC */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NC(GPP_B1),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* B2 : VRALERT# ==> NC */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NC(GPP_B2),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* B3 : CPU_GP2 ==> TRACKPAD_INT_L */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPI_APIC(GPP_B3, NONE, PLTRST),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* B4 : CPU_GP3 ==> NC */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NC(GPP_B4),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* B5 : SRCCLKREQ0# ==> TRACKPAD_INT_L for wakeup event */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPI_ACPI_SCI(GPP_B5, NONE, DEEP, INVERT),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* B6 : SRCCLKREQ1# ==> WLAN_PCIE_CLKREQ_L */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* B7 : SRCCLKREQ2# ==> NC */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NC(GPP_B7),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* B8 : SRCCLKREQ3# ==> WLAN_PE_RST */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPO(GPP_B8, 0, DEEP),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* B9 : SRCCLKREQ4# ==> NC */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NC(GPP_B9),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* B10 : SRCCLKREQ5# ==> NC */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NC(GPP_B10),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* B11 : EXT_PWR_GATE# ==> NC */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NC(GPP_B11),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* B12 : SLP_S0# ==> SLP_S0_L_G */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* B13 : PLTRST# ==> PLT_RST_L_PCH */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* B14 : SPKR ==> NC */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NC(GPP_B14),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* B15 : GSPI0_CS# ==> PCH_SPI_H1_3V3_CS_L */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* B16 : GSPI0_CLK ==> PCH_SPI_H1_3V3_CLK */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF(GPP_B16, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* B17 : GSPI0_MISO ==> PCH_SPI_H1_3V3_MISO */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* B18 : GSPI0_MOSI ==> PCH_SPI_H1_3V3_MOSI */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* B19 : GSPI1_CS# ==> NC(T0807) */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NC(GPP_B19),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* B20 : GSPI1_CLK ==> NC(T0808) */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NC(GPP_B20),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* B21 : GSPI1_MISO ==> NC(T0809) */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NC(GPP_B21),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* B22 : GSPI1_MOSI ==> NC(T0810) */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NC(GPP_B22),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* B23 : SM1ALERT# ==> NC */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NC(GPP_B23),</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* C0 : SMBCLK ==> SMBCLK */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* C1 : SMBDATA ==> SMBDATA */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* C2 : SMBALERT# ==> NC */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NC(GPP_C2),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* C3 : SML0CLK ==> NC */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NC(GPP_C3),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* C4 : SML0DATA ==> NC */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NC(GPP_C4),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* C5 : SML0ALERT# ==> NC */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NC(GPP_C5),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* C6 : SM1CLK ==> EC_IN_RW_OD */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPI_GPIO_DRIVER(GPP_C6, 20K_PU, DEEP),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* C7 : SM1DATA ==> NC */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NC(GPP_C7),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* C8 : UART0_RXD ==> NC(BT_OFF#) */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NC(GPP_C8),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* C9 : UART0_TXD ==> NC(WLAN_OFF#) */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NC(GPP_C9),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* C10 : UART0_RTS# ==> NC(T0817) */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NC(GPP_C10),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* C11 : UART0_CTS# ==> EN_PP3300_DX_CAM */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPO(GPP_C11, 1, DEEP),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* C12 : UART1_RXD ==> PCH_MEM_CONFIG[0] */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPI_GPIO_DRIVER(GPP_C12, NONE, DEEP),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* C13 : UART1_TXD ==> PCH_MEM_CONFIG[1] */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPI_GPIO_DRIVER(GPP_C13, NONE, DEEP),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* C14 : UART1_RTS# ==> PCH_MEM_CONFIG[2] */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPI_GPIO_DRIVER(GPP_C14, NONE, DEEP),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* C15 : UART1_CTS# ==> PCH_MEM_CONFIG[3] */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPI_GPIO_DRIVER(GPP_C15, NONE, DEEP),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* C16 : I2C0_SDA ==> PCH_I2C0_TOUCHSCREEN_3V3_SDA */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* C17 : I2C0_SCL ==> PCH_I2C0_TOUCHSCREEN_3V3_SCL */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* C18 : I2C1_SDA ==> PCH_I2C1_TRACKPAD_3V3_SDA */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* C19 : I2C1_SCL ==> PCH_I2C1_TRACKPAD_3V3_SCL */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* C20 : UART2_RXD ==> PCHRX_SERVOTX_UART */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* C21 : UART2_TXD ==> PCHTX_SERVORX_UART */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* C22 : UART2_RTS# ==> EN_PP3300_DX_TOUCHSCREEN */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPO(GPP_C22, 0, DEEP),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* C23 : UART2_CTS# ==> PCH_WP */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, 20K_PU, DEEP),</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* D0 : SPI1_CS# ==> NC */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NC(GPP_D0),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* D1 : SPI1_CLK ==> NC(T0818) */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NC(GPP_D1),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* D2 : SPI1_MISO ==> NC(T0819) */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NC(GPP_D2),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* D3 : SPI1_MOSI ==> NC(T0820) */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NC(GPP_D3),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* D4 : FASHTRIG ==> NC */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NC(GPP_D4),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* D5 : ISH_I2C0_SDA ==> NC */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NC(GPP_D5),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* D6 : ISH_I2C0_SCL ==> NC */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NC(GPP_D6),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* D7 : ISH_I2C1_SDA ==> NC */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NC(GPP_D7),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* D8 : ISH_I2C1_SCL ==> NC(T0815) */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NC(GPP_D8),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* D9 : ISH_SPI_CS# ==> HP_IRQ_GPIO */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPI_APIC(GPP_D9, 20K_PU, DEEP),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* D10 : ISH_SPI_CLK ==> SPKR_RST_L */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPO(GPP_D10, 1, DEEP),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* D11 : ISH_SPI_MISO ==> SPKR_IRQ_L */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPI_APIC(GPP_D11, NONE, PLTRST),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* D12 : ISH_SPI_MOSI ==> NC(T0816) */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NC(GPP_D12),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* D13 : ISH_UART0_RXD ==> NC */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NC(GPP_D13),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* D14 : ISH_UART0_TXD ==> NC */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NC(GPP_D14),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* D15 : ISH_UART0_RTS# ==> NC */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NC(GPP_D15),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* D16 : ISH_UART0_CTS# ==> NC */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NC(GPP_D16),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* D17 : ISH_UART0_CTS# ==> DMIC_CLK1_PCH */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF(GPP_D17, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* D18 : DMIC_DATA1 ==> NC(T0703) */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NC(GPP_D18),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* D19 : DMIC_CLK0 ==> DMIC_CLK0_PCH */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* D20 : DMIC_DATA0 ==> DMIC_DATA0_PCH */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF(GPP_D20, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* D21 : SPI1_IO2 ==> NC */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NC(GPP_D21),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* D22 : SPI1_IO3 ==> BOOT_BEEP_OVERRIDE */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPO(GPP_D22, 1, DEEP),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* D23 : I2S_MCLK ==> I2S_MCLK */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF(GPP_D23, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* E0 : SATAXPCI0 ==> H1_PCH_INT_ODL */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPI_APIC_INVERT(GPP_E0, NONE, PLTRST),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* E1 : SATAXPCIE1 ==> NC */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NC(GPP_E1),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* E2 : SATAXPCIE2 ==> NC */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NC(GPP_E2),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* E3 : CPU_GP0 ==> NC */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NC(GPP_E3),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* E4 : SATA_DEVSLP0 ==> NC */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NC(GPP_E4),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* E5 : SATA_DEVSLP1 ==> NC */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NC(GPP_E5),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* E6 : SATA_DEVSLP2 ==> NC */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NC(GPP_E6),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* E7 : CPU_GP1 ==> TOUCHSCREEN_INT_L */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPI_APIC(GPP_E7, NONE, PLTRST),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* E8 : SATALED# ==> NC */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NC(GPP_E8),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* E9 : USB2_OCO# ==> USB_C0_OC_ODL */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* E10 : USB2_OC1# ==> USB_C1_OC_ODL */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF(GPP_E10, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* E11 : USB2_OC2# ==> NC(T0504) */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NC(GPP_E11),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* E12 : USB2_OC3# ==> USB_A0_OC# */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF(GPP_E12, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* E13 : DDPB_HPD0 ==> USB_C0_DP_HPD */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF(GPP_E13, 20K_PD, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* E14 : DDPC_HPD1 ==> USB_C1_DP_HPD */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF(GPP_E14, 20K_PD, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* E15 : DDPD_HPD2 ==> SD_CD_ODL */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPI_GPIO_DRIVER(GPP_E15, 20K_PU, DEEP),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* E16 : DDPE_HPD3 ==> NC(T0602) */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NC(GPP_E16),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* E17 : EDP_HPD ==> EDP_HPD */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* E18 : DDPB_CTRLCLK ==> NC */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NC(GPP_E18),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* E19 : DDPB_CTRLDATA ==> NC */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NC(GPP_E19),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* E20 : DDPC_CTRLCLK ==> NC */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NC(GPP_E20),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* E21 : DDPC_CTRLDATA ==> NC */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NC(GPP_E21),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* E22 : DDPD_CTRLCLK ==> NC */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NC(GPP_E22),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* E23 : DDPD_CTRLDATA ==> NC*/</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NC(GPP_E23),</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* The next 4 pads are for bit banging the amplifiers, default to I2S */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* F0 : I2S2_SCLK ==> I2S2_SCLK_SPKR_R */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPI_GPIO_DRIVER(GPP_F0, NONE, DEEP),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* F1 : I2S2_SFRM ==> I2S2_SFRM_SPKR_R */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPI_GPIO_DRIVER(GPP_F1, NONE, DEEP),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* F2 : I2S2_TXD ==> I2S2_PCH_TX_SPKR_RX_R */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPI_GPIO_DRIVER(GPP_F2, NONE, DEEP),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* F3 : I2S2_RXD ==> NC */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NC(GPP_F3),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* F4 : I2C2_SDA ==> I2C_2_SDA */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF_1V8(GPP_F4, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* F5 : I2C2_SCL ==> I2C_2_SCL */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF_1V8(GPP_F5, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* F6 : I2C3_SDA ==> PCH_I2C3_PEN_1V8_SDA */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF_1V8(GPP_F6, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* F7 : I2C3_SCL ==> PCH_I2C3_PEN_1V8_SCL */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF_1V8(GPP_F7, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* F8 : I2C4_SDA ==> PCH_I2C4_H1_1V8_SDA */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF_1V8(GPP_F8, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* F9 : I2C4_SCL ==> PCH_I2C4_H1_1V8_SCL */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF_1V8(GPP_F9, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* F10 : I2C5_SDA ==> PCH_I2C5_AUDIO_1V8_SDA */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF_1V8(GPP_F10, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* F11 : I2C5_SCL ==> PCH_I2C5_AUDIO_1V8_SCL */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF_1V8(GPP_F11, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* F12 : EMMC_CMD ==> EMMC_CMD */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF(GPP_F12, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* F13 : EMMC_DATA0 ==> EMMC_DAT0 */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF(GPP_F13, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* F14 : EMMC_DATA1 ==> EMMC_DAT1 */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF(GPP_F14, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* F15 : EMMC_DATA2 ==> EMMC_DAT2 */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF(GPP_F15, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* F16 : EMMC_DATA3 ==> EMMC_DAT3 */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF(GPP_F16, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* F17 : EMMC_DATA4 ==> EMMC_DAT4 */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF(GPP_F17, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* F18 : EMMC_DATA5 ==> EMMC_DAT5 */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF(GPP_F18, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* F19 : EMMC_DATA6 ==> EMMC_DAT6 */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* F20 : EMMC_DATA7 ==> EMMC_DAT7 */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* F21 : EMMC_RCLK ==> EMMC_RCLK */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* F22 : EMMC_CLK ==> EMMC_CLK */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF(GPP_F22, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* F23 : RSVD ==> NC */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NC(GPP_F23),</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* G0 : SD_CMD ==> SD_CMD */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF(GPP_G0, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* G1 : SD_DATA0 ==> SD_DATA0 */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF(GPP_G1, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* G2 : SD_DATA1 ==> SD_DATA1 */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF(GPP_G2, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* G3 : SD_DATA2 ==> SD_DATA2 */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF(GPP_G3, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* G4 : SD_DATA3 ==> SD_DATA3 */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF(GPP_G4, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* G5 : SD_CD# ==> SD_CD_ODL */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF(GPP_G5, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* G6 : SD_CLK ==> SD_CLK */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF(GPP_G6, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* G7 : SD_WP ==> NC(T0701) */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF(GPP_G7, 20K_PD, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* GPD0: BATLOW# ==> PCH_BATLOW_L */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF(GPD0, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* GPD1: ACPRESENT ==> EC_PCH_ACPRESENT */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF(GPD1, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* GPD2: LAN_WAKE# ==> EC_PCH_WAKE_R_L */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF(GPD2, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* GPD3: PWRBTN# ==> PCH_PWR_BTN_L */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF(GPD3, 20K_PU, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* GPD4: SLP_S3# ==> SLP_S3_L */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF(GPD4, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* GPD5: SLP_S4# ==> SLP_S4_L */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF(GPD5, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* GPD6: SLP_A# ==> NC(T0912) */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NC(GPD6),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* GPD7: RSVD ==> NC */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NC(GPD7),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* GPD8: SUSCLK ==> PCH_SUSCLK */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF(GPD8, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* GPD9: SLP_WLAN# ==> NC(T0911) */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NC(GPD9),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* GPD10: SLP_S5# ==> NC(T0905) */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NC(GPD10),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* GPD11: LANPHYC ==> NC */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NC(GPD11),</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* Early pad configuration in bootblock */</span><br><span style="color: hsl(120, 100%, 40%);">+static const struct pad_config early_gpio_table[] = {</span><br><span style="color: hsl(120, 100%, 40%);">+ /* B15 : GSPI0_CS# ==> PCH_SPI_H1_3V3_CS_L */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* B16 : GSPI0_CLK ==> PCH_SPI_H1_3V3_CLK */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF(GPP_B16, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* B17 : GSPI0_MISO ==> PCH_SPI_H1_3V3_MISO */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* B18 : GSPI0_MOSI ==> PCH_SPI_H1_3V3_MOSI */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Ensure UART pins are in native mode for H1. */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* C20 : UART2_RXD ==> PCHRX_SERVOTX_UART */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* C21 : UART2_TXD ==> PCHTX_SERVORX_UART */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* C23 : UART2_CTS# ==> PCH_WP */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, 20K_PU, DEEP),</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* E0 : SATAXPCI0 ==> H1_PCH_INT_ODL */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPI_APIC_INVERT(GPP_E0, NONE, PLTRST),</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+const struct pad_config *variant_gpio_table(size_t *num)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ *num = ARRAY_SIZE(gpio_table);</span><br><span style="color: hsl(120, 100%, 40%);">+ return gpio_table;</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+const struct pad_config *variant_early_gpio_table(size_t *num)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ *num = ARRAY_SIZE(early_gpio_table);</span><br><span style="color: hsl(120, 100%, 40%);">+ return early_gpio_table;</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/27807">change 27807</a>. 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<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: merged </div>
<div style="display:none"> Gerrit-Change-Id: I20fc081d372b8686f6128a7e85276f9c6798b199 </div>
<div style="display:none"> Gerrit-Change-Number: 27807 </div>
<div style="display:none"> Gerrit-PatchSet: 2 </div>
<div style="display:none"> Gerrit-Owner: Zhuohao Lee <zhuohao@chromium.org> </div>
<div style="display:none"> Gerrit-Reviewer: Furquan Shaikh <furquan@google.com> </div>
<div style="display:none"> Gerrit-Reviewer: Patrick Georgi <pgeorgi@google.com> </div>
<div style="display:none"> Gerrit-Reviewer: build bot (Jenkins) <no-reply@coreboot.org> </div>