<p>Patrick Georgi <strong>merged</strong> this change.</p><p><a href="https://review.coreboot.org/27813">View Change</a></p><div style="white-space:pre-wrap">Approvals:
build bot (Jenkins): Verified
Martin Roth: Looks good to me, approved
</div><pre style="font-family: monospace,monospace; white-space: pre-wrap;">soc/amd/stoneyridge: Enable spread spectrum in bootblock<br><br>setup_spread_spectrum is called in early_init, meaning the console is<br>not initialized yet. So you won't see boot block booting twice.<br><br>BUG=b:111610455<br>TEST=booted grunt and verified that AmdInitReset does not reboot. I had<br>AGESA patched to skip the JTAG check.<br><br>Change-Id: Ia036ea513ac67d4b8bcf5a78029d969a4ae012a6<br>Signed-off-by: Raul E Rangel <rrangel@chromium.org><br>Reviewed-on: https://review.coreboot.org/27813<br>Tested-by: build bot (Jenkins) <no-reply@coreboot.org><br>Reviewed-by: Martin Roth <martinroth@google.com><br>---<br>M src/soc/amd/stoneyridge/include/soc/southbridge.h<br>M src/soc/amd/stoneyridge/sb_util.c<br>M src/soc/amd/stoneyridge/southbridge.c<br>3 files changed, 89 insertions(+), 0 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/soc/amd/stoneyridge/include/soc/southbridge.h b/src/soc/amd/stoneyridge/include/soc/southbridge.h</span><br><span>index 15c9581..64b4b46 100644</span><br><span>--- a/src/soc/amd/stoneyridge/include/soc/southbridge.h</span><br><span>+++ b/src/soc/amd/stoneyridge/include/soc/southbridge.h</span><br><span>@@ -367,6 +367,28 @@</span><br><span> #define GPP_CLK0_CLOCK_REQ_MAP_MASK (0xf << GPP_CLK0_CLOCK_REQ_MAP_SHIFT)</span><br><span> #define GPP_CLK0_CLOCK_REQ_MAP_CLK_REQ0 1</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+/* Bit definitions for MISC_MMIO_BASE register MiscClkCntl1 */</span><br><span style="color: hsl(120, 100%, 40%);">+#define MISC_CGPLL_CONFIG1 0x08</span><br><span style="color: hsl(120, 100%, 40%);">+#define CG1PLL_SPREAD_SPECTRUM_ENABLE BIT(0)</span><br><span style="color: hsl(120, 100%, 40%);">+#define MISC_CGPLL_CONFIG3 0x10</span><br><span style="color: hsl(120, 100%, 40%);">+#define CG1PLL_REFDIV_SHIFT 0</span><br><span style="color: hsl(120, 100%, 40%);">+#define CG1PLL_REFDIV_MASK (0x3FF << CG1PLL_REFDIV_SHIFT)</span><br><span style="color: hsl(120, 100%, 40%);">+#define CG1PLL_FBDIV_SHIFT 10</span><br><span style="color: hsl(120, 100%, 40%);">+#define CG1PLL_FBDIV_MASK (0xFFF << CG1PLL_FBDIV_SHIFT)</span><br><span style="color: hsl(120, 100%, 40%);">+#define MISC_CGPLL_CONFIG4 0x14</span><br><span style="color: hsl(120, 100%, 40%);">+#define CG1PLL_SS_STEP_SIZE_DSFRAC_SHIFT 0</span><br><span style="color: hsl(120, 100%, 40%);">+#define CG1PLL_SS_STEP_SIZE_DSFRAC_MASK (0xFFFF << CG1PLL_SS_STEP_SIZE_DSFRAC_SHIFT)</span><br><span style="color: hsl(120, 100%, 40%);">+#define CG1PLL_SS_AMOUNT_DSFRAC_SHIFT 16</span><br><span style="color: hsl(120, 100%, 40%);">+#define CG1PLL_SS_AMOUNT_DSFRAC_MASK (0xFFFF << CG1PLL_SS_AMOUNT_DSFRAC_SHIFT)</span><br><span style="color: hsl(120, 100%, 40%);">+#define MISC_CGPLL_CONFIG5 0x18</span><br><span style="color: hsl(120, 100%, 40%);">+#define CG1PLL_SS_AMOUNT_NFRAC_SLIP_SHIFT 8</span><br><span style="color: hsl(120, 100%, 40%);">+#define CG1PLL_SS_AMOUNT_NFRAC_SLIP_MASK (0xF << CG1PLL_SS_AMOUNT_NFRAC_SLIP_SHIFT)</span><br><span style="color: hsl(120, 100%, 40%);">+#define MISC_CGPLL_CONFIG6 0x1C</span><br><span style="color: hsl(120, 100%, 40%);">+#define CG1PLL_LF_MODE_SHIFT 9</span><br><span style="color: hsl(120, 100%, 40%);">+#define CG1PLL_LF_MODE_MASK (0x1FF << CG1PLL_LF_MODE_SHIFT)</span><br><span style="color: hsl(120, 100%, 40%);">+#define MISC_CLK_CNTL1 0x40</span><br><span style="color: hsl(120, 100%, 40%);">+#define CG1PLL_FBDIV_TEST BIT(26)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> struct stoneyridge_aoac {</span><br><span> int enable;</span><br><span> int status;</span><br><span>@@ -404,6 +426,8 @@</span><br><span> void pm_write8(u8 reg, u8 value);</span><br><span> void pm_write16(u8 reg, u16 value);</span><br><span> void pm_write32(u8 reg, u32 value);</span><br><span style="color: hsl(120, 100%, 40%);">+u32 misc_read32(u8 reg);</span><br><span style="color: hsl(120, 100%, 40%);">+void misc_write32(u8 reg, u32 value);</span><br><span> uint8_t smi_read8(uint8_t offset);</span><br><span> uint16_t smi_read16(uint8_t offset);</span><br><span> uint32_t smi_read32(uint8_t offset);</span><br><span>diff --git a/src/soc/amd/stoneyridge/sb_util.c b/src/soc/amd/stoneyridge/sb_util.c</span><br><span>index 26c86e8..9daf0bb 100644</span><br><span>--- a/src/soc/amd/stoneyridge/sb_util.c</span><br><span>+++ b/src/soc/amd/stoneyridge/sb_util.c</span><br><span>@@ -36,6 +36,16 @@</span><br><span> return read16((void *)(PM_MMIO_BASE + reg));</span><br><span> }</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+void misc_write32(u8 reg, u32 value)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ write32((void *)(MISC_MMIO_BASE + reg), value);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+u32 misc_read32(u8 reg)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ return read32((void *)(MISC_MMIO_BASE + reg));</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> void pm_write32(u8 reg, u32 value)</span><br><span> {</span><br><span> write32((void *)(PM_MMIO_BASE + reg), value);</span><br><span>diff --git a/src/soc/amd/stoneyridge/southbridge.c b/src/soc/amd/stoneyridge/southbridge.c</span><br><span>index f098c1c..348d5f1 100644</span><br><span>--- a/src/soc/amd/stoneyridge/southbridge.c</span><br><span>+++ b/src/soc/amd/stoneyridge/southbridge.c</span><br><span>@@ -33,6 +33,7 @@</span><br><span> #include <soc/pci_devs.h></span><br><span> #include <agesa_headers.h></span><br><span> #include <soc/nvs.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <reset.h></span><br><span> </span><br><span> /*</span><br><span> * Table of devices that need their AOAC registers enabled and waited</span><br><span>@@ -555,6 +556,59 @@</span><br><span> }</span><br><span> }</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+static void setup_spread_spectrum(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ uint16_t rstcfg = pm_read16(PWR_RESET_CFG);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ rstcfg &= ~TOGGLE_ALL_PWR_GOOD;</span><br><span style="color: hsl(120, 100%, 40%);">+ pm_write16(PWR_RESET_CFG, rstcfg);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t cntl1 = misc_read32(MISC_CLK_CNTL1);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ if (cntl1 & CG1PLL_FBDIV_TEST) {</span><br><span style="color: hsl(120, 100%, 40%);">+ printk(BIOS_DEBUG, "Spread spectrum is ready\n");</span><br><span style="color: hsl(120, 100%, 40%);">+ misc_write32(MISC_CGPLL_CONFIG1,</span><br><span style="color: hsl(120, 100%, 40%);">+ misc_read32(MISC_CGPLL_CONFIG1) |</span><br><span style="color: hsl(120, 100%, 40%);">+ CG1PLL_SPREAD_SPECTRUM_ENABLE);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ return;</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ printk(BIOS_DEBUG, "Setting up spread spectrum\n");</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t cfg6 = misc_read32(MISC_CGPLL_CONFIG6);</span><br><span style="color: hsl(120, 100%, 40%);">+ cfg6 &= ~CG1PLL_LF_MODE_MASK;</span><br><span style="color: hsl(120, 100%, 40%);">+ cfg6 |= (0x0F8 << CG1PLL_LF_MODE_SHIFT) & CG1PLL_LF_MODE_MASK;</span><br><span style="color: hsl(120, 100%, 40%);">+ misc_write32(MISC_CGPLL_CONFIG6, cfg6);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t cfg3 = misc_read32(MISC_CGPLL_CONFIG3);</span><br><span style="color: hsl(120, 100%, 40%);">+ cfg3 &= ~CG1PLL_REFDIV_MASK;</span><br><span style="color: hsl(120, 100%, 40%);">+ cfg3 |= (0x003 << CG1PLL_REFDIV_SHIFT) & CG1PLL_REFDIV_MASK;</span><br><span style="color: hsl(120, 100%, 40%);">+ cfg3 &= ~CG1PLL_FBDIV_MASK;</span><br><span style="color: hsl(120, 100%, 40%);">+ cfg3 |= (0x04B << CG1PLL_FBDIV_SHIFT) & CG1PLL_FBDIV_MASK;</span><br><span style="color: hsl(120, 100%, 40%);">+ misc_write32(MISC_CGPLL_CONFIG3, cfg3);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t cfg5 = misc_read32(MISC_CGPLL_CONFIG5);</span><br><span style="color: hsl(120, 100%, 40%);">+ cfg5 &= ~CG1PLL_SS_AMOUNT_NFRAC_SLIP_MASK;</span><br><span style="color: hsl(120, 100%, 40%);">+ cfg5 |= (0x2 << CG1PLL_SS_AMOUNT_NFRAC_SLIP_SHIFT) & CG1PLL_SS_AMOUNT_NFRAC_SLIP_MASK;</span><br><span style="color: hsl(120, 100%, 40%);">+ misc_write32(MISC_CGPLL_CONFIG5, cfg5);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t cfg4 = misc_read32(MISC_CGPLL_CONFIG4);</span><br><span style="color: hsl(120, 100%, 40%);">+ cfg4 &= ~CG1PLL_SS_AMOUNT_DSFRAC_MASK;</span><br><span style="color: hsl(120, 100%, 40%);">+ cfg4 |= (0xD000 << CG1PLL_SS_AMOUNT_DSFRAC_SHIFT) & CG1PLL_SS_AMOUNT_DSFRAC_MASK;</span><br><span style="color: hsl(120, 100%, 40%);">+ cfg4 &= ~CG1PLL_SS_STEP_SIZE_DSFRAC_MASK;</span><br><span style="color: hsl(120, 100%, 40%);">+ cfg4 |= (0x02D5 << CG1PLL_SS_STEP_SIZE_DSFRAC_SHIFT) & CG1PLL_SS_STEP_SIZE_DSFRAC_MASK;</span><br><span style="color: hsl(120, 100%, 40%);">+ misc_write32(MISC_CGPLL_CONFIG4, cfg4);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ rstcfg |= TOGGLE_ALL_PWR_GOOD;</span><br><span style="color: hsl(120, 100%, 40%);">+ pm_write16(PWR_RESET_CFG, rstcfg);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ cntl1 |= CG1PLL_FBDIV_TEST;</span><br><span style="color: hsl(120, 100%, 40%);">+ misc_write32(MISC_CLK_CNTL1, cntl1);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ soft_reset();</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> void bootblock_fch_early_init(void)</span><br><span> {</span><br><span> sb_enable_rom();</span><br><span>@@ -565,6 +619,7 @@</span><br><span> sb_disable_4dw_burst(); /* Must be disabled on CZ(ST) */</span><br><span> sb_acpi_mmio_decode();</span><br><span> sb_enable_cf9_io();</span><br><span style="color: hsl(120, 100%, 40%);">+ setup_spread_spectrum();</span><br><span> sb_enable_legacy_io();</span><br><span> enable_aoac_devices();</span><br><span> }</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/27813">change 27813</a>. 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<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: merged </div>
<div style="display:none"> Gerrit-Change-Id: Ia036ea513ac67d4b8bcf5a78029d969a4ae012a6 </div>
<div style="display:none"> Gerrit-Change-Number: 27813 </div>
<div style="display:none"> Gerrit-PatchSet: 3 </div>
<div style="display:none"> Gerrit-Owner: Raul Rangel <rrangel@chromium.org> </div>
<div style="display:none"> Gerrit-Reviewer: Garrett Kirkendall <garrett.kirkendall@amd.corp-partner.google.com> </div>
<div style="display:none"> Gerrit-Reviewer: Martin Roth <martinroth@google.com> </div>
<div style="display:none"> Gerrit-Reviewer: Patrick Georgi <pgeorgi@google.com> </div>
<div style="display:none"> Gerrit-Reviewer: Raul Rangel <rrangel@chromium.org> </div>
<div style="display:none"> Gerrit-Reviewer: build bot (Jenkins) <no-reply@coreboot.org> </div>