<p>Ravishankar Sarawadi has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/27851">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">mb/google/octopus: Fix LPDDR4 nWR setting<br><br>Update nWR setting for LPDDR4 from default to 24 cycles as per spec.<br><br>BUG=b:112062440<br>TEST=Run memory stability test using Memtester.<br><br>Change-Id: I949d30ca9d5bb8fd876fe3c6cac7a719e771e839<br>Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com><br>---<br>M src/mainboard/google/octopus/variants/baseboard/memory.c<br>1 file changed, 8 insertions(+), 0 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/51/27851/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/mainboard/google/octopus/variants/baseboard/memory.c b/src/mainboard/google/octopus/variants/baseboard/memory.c</span><br><span>index 452d3a9..6e0fe47 100644</span><br><span>--- a/src/mainboard/google/octopus/variants/baseboard/memory.c</span><br><span>+++ b/src/mainboard/google/octopus/variants/baseboard/memory.c</span><br><span>@@ -76,6 +76,7 @@</span><br><span>           .ch0_dual_rank = 1,</span><br><span>          .ch1_dual_rank = 1,</span><br><span>          .part_num = "K4F6E304HB-MGCJ",</span><br><span style="color: hsl(120, 100%, 40%);">+              .enable_nWR_24 = 1,</span><br><span>  },</span><br><span>   /* K4F8E304HB-MGCJ - both logical channels  */</span><br><span>       [1] = {</span><br><span>@@ -83,6 +84,7 @@</span><br><span>          .ch0_rank_density = LP4_8Gb_DENSITY,</span><br><span>                 .ch1_rank_density = LP4_8Gb_DENSITY,</span><br><span>                 .part_num = "K4F8E304HB-MGCJ",</span><br><span style="color: hsl(120, 100%, 40%);">+              .enable_nWR_24 = 1,</span><br><span>  },</span><br><span>   /*</span><br><span>    * MT53B512M32D2NP-062WT:C - both logical channels. While the parts</span><br><span>@@ -97,6 +99,7 @@</span><br><span>              .ch1_dual_rank = 1,</span><br><span>          .part_num = "MT53B512M32D2NP",</span><br><span>             .disable_periodic_retraining = 1,</span><br><span style="color: hsl(120, 100%, 40%);">+             .enable_nWR_24 = 1,</span><br><span>  },</span><br><span>   /* MT53B256M32D1NP-062 WT:C - both logical channels */</span><br><span>       [3] = {</span><br><span>@@ -105,6 +108,7 @@</span><br><span>                .ch1_rank_density = LP4_8Gb_DENSITY,</span><br><span>                 .part_num = "MT53B256M32D1NP",</span><br><span>             .disable_periodic_retraining = 1,</span><br><span style="color: hsl(120, 100%, 40%);">+             .enable_nWR_24 = 1,</span><br><span>  },</span><br><span>   /*</span><br><span>    * H9HCNNNBPUMLHR-NLE - both logical channels. While the parts</span><br><span>@@ -118,6 +122,7 @@</span><br><span>                 .ch0_dual_rank = 1,</span><br><span>          .ch1_dual_rank = 1,</span><br><span>          .part_num = "H9HCNNNBPUMLHR",</span><br><span style="color: hsl(120, 100%, 40%);">+               .enable_nWR_24 = 1,</span><br><span>  },</span><br><span>   /* H9HCNNN8KUMLHR-NLE - both logical channels */</span><br><span>     [5] = {</span><br><span>@@ -125,6 +130,7 @@</span><br><span>                .ch0_rank_density = LP4_8Gb_DENSITY,</span><br><span>                 .ch1_rank_density = LP4_8Gb_DENSITY,</span><br><span>                 .part_num = "H9HCNNN8KUMLHR",</span><br><span style="color: hsl(120, 100%, 40%);">+               .enable_nWR_24 = 1,</span><br><span>  },</span><br><span>   /* K4F6E3S4HM-MGCJ - both logical channels */</span><br><span>        [6] = {</span><br><span>@@ -132,6 +138,7 @@</span><br><span>                .ch0_rank_density = LP4_16Gb_DENSITY,</span><br><span>                .ch1_rank_density = LP4_16Gb_DENSITY,</span><br><span>                .part_num = "K4F6E3S4HM-MGCJ",</span><br><span style="color: hsl(120, 100%, 40%);">+              .enable_nWR_24 = 1,</span><br><span>  },</span><br><span>   /* MT53E512M32D2NP-046 - both logical channels */</span><br><span>    [7] = {</span><br><span>@@ -139,6 +146,7 @@</span><br><span>                .ch0_rank_density = LP4_16Gb_DENSITY,</span><br><span>                .ch1_rank_density = LP4_16Gb_DENSITY,</span><br><span>                .part_num = "MT53E512M32D2NP",</span><br><span style="color: hsl(120, 100%, 40%);">+              .enable_nWR_24 = 1,</span><br><span>  },</span><br><span> };</span><br><span> </span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/27851">change 27851</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/27851"/><meta itemprop="name" content="View Change"/></div></div>

<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I949d30ca9d5bb8fd876fe3c6cac7a719e771e839 </div>
<div style="display:none"> Gerrit-Change-Number: 27851 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Ravishankar Sarawadi <ravishankar.sarawadi@intel.com> </div>