<p>Ravishankar Sarawadi has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/27850">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">soc/intel/apollolake: Add support for LPDDR4 nWR setting<br><br>nWR (Write-Recovery for AutoPre-charge commands), the programmed value of nWR<br>is the number of clock cycles the LPDDR4-SDRAM device uses to determine the<br>starting point of an internal Pre-charge operation after a Write burst with<br>AP (auto-pre-charge) enabled.<br><br>BUG=b:112062440<br>TEST= build test<br><br>Change-Id: I1147538f72f4e2f14e32f3657c05f1f505a56fbf<br>Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com><br>---<br>M src/soc/intel/apollolake/include/soc/meminit.h<br>M src/soc/intel/apollolake/meminit.c<br>2 files changed, 19 insertions(+), 7 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/27850/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/soc/intel/apollolake/include/soc/meminit.h b/src/soc/intel/apollolake/include/soc/meminit.h</span><br><span>index 27b6556..adea59a 100644</span><br><span>--- a/src/soc/intel/apollolake/include/soc/meminit.h</span><br><span>+++ b/src/soc/intel/apollolake/include/soc/meminit.h</span><br><span>@@ -81,6 +81,7 @@</span><br><span> enum {</span><br><span> ODT_A_B_HIGH_LOW = 0 << 1,</span><br><span> ODT_A_B_HIGH_HIGH = 1 << 1,</span><br><span style="color: hsl(120, 100%, 40%);">+ nWR = 1 << 5,</span><br><span> };</span><br><span> </span><br><span> /* Provide bit swizzling per DQS and byte swapping within a channel. */</span><br><span>@@ -116,6 +117,7 @@</span><br><span> int ch1_dual_rank;</span><br><span> const char *part_num;</span><br><span> bool disable_periodic_retraining;</span><br><span style="color: hsl(120, 100%, 40%);">+ bool enable_nWR_24;</span><br><span> };</span><br><span> </span><br><span> struct lpddr4_cfg {</span><br><span>diff --git a/src/soc/intel/apollolake/meminit.c b/src/soc/intel/apollolake/meminit.c</span><br><span>index b0a5f4a..8690040 100644</span><br><span>--- a/src/soc/intel/apollolake/meminit.c</span><br><span>+++ b/src/soc/intel/apollolake/meminit.c</span><br><span>@@ -119,13 +119,6 @@</span><br><span> cfg->Ch1_Option = 0x3;</span><br><span> cfg->Ch2_Option = 0x3;</span><br><span> cfg->Ch3_Option = 0x3;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Set CA ODT with default setting of ODT pins of LPDDR4 modules pulled</span><br><span style="color: hsl(0, 100%, 40%);">- up to 1.1V. */</span><br><span style="color: hsl(0, 100%, 40%);">- cfg->Ch0_OdtConfig = ODT_A_B_HIGH_HIGH;</span><br><span style="color: hsl(0, 100%, 40%);">- cfg->Ch1_OdtConfig = ODT_A_B_HIGH_HIGH;</span><br><span style="color: hsl(0, 100%, 40%);">- cfg->Ch2_OdtConfig = ODT_A_B_HIGH_HIGH;</span><br><span style="color: hsl(0, 100%, 40%);">- cfg->Ch3_OdtConfig = ODT_A_B_HIGH_HIGH;</span><br><span> }</span><br><span> </span><br><span> struct speed_mapping {</span><br><span>@@ -326,6 +319,7 @@</span><br><span> const struct lpddr4_cfg *lpcfg, size_t sku_id)</span><br><span> {</span><br><span> const struct lpddr4_sku *sku;</span><br><span style="color: hsl(120, 100%, 40%);">+ u8 odt_config;</span><br><span> </span><br><span> if (sku_id >= lpcfg->num_skus) {</span><br><span> printk(BIOS_ERR, "Too few LPDDR4 SKUs: 0x%zx/0x%zx\n",</span><br><span>@@ -358,6 +352,22 @@</span><br><span> }</span><br><span> </span><br><span> cfg->PeriodicRetrainingDisable = sku->disable_periodic_retraining;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /*</span><br><span style="color: hsl(120, 100%, 40%);">+ * Set CA ODT with default setting of ODT pins of LPDDR4 modules pulled</span><br><span style="color: hsl(120, 100%, 40%);">+ * up to 1.1V.</span><br><span style="color: hsl(120, 100%, 40%);">+ * Set bit 5 in Ch0_OdtConfig to enable nWR24.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+ if (sku->enable_nWR_24 == 1)</span><br><span style="color: hsl(120, 100%, 40%);">+ odt_config = ODT_A_B_HIGH_HIGH | nWR;</span><br><span style="color: hsl(120, 100%, 40%);">+ else</span><br><span style="color: hsl(120, 100%, 40%);">+ odt_config = ODT_A_B_HIGH_HIGH;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ cfg->Ch0_OdtConfig = odt_config;</span><br><span style="color: hsl(120, 100%, 40%);">+ cfg->Ch1_OdtConfig = odt_config;</span><br><span style="color: hsl(120, 100%, 40%);">+ cfg->Ch2_OdtConfig = odt_config;</span><br><span style="color: hsl(120, 100%, 40%);">+ cfg->Ch3_OdtConfig = odt_config;</span><br><span> }</span><br><span> </span><br><span> uint8_t fsp_memory_soc_version(void)</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/27850">change 27850</a>. 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<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I1147538f72f4e2f14e32f3657c05f1f505a56fbf </div>
<div style="display:none"> Gerrit-Change-Number: 27850 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Ravishankar Sarawadi <ravishankar.sarawadi@intel.com> </div>