<p><a href="https://review.coreboot.org/27766">View Change</a></p><p>5 comments:</p><ul style="list-style: none; padding: 0;"><li style="margin: 0; padding: 0;"><p><a href="https://review.coreboot.org/#/c/27766/3/src/soc/intel/cannonlake/chip.c">File src/soc/intel/cannonlake/chip.c:</a></p><ul style="list-style: none; padding: 0;"><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/27766/3/src/soc/intel/cannonlake/chip.c@253">Patch Set #3, Line 253:</a> <code style="font-family:monospace,monospace">          params->Usb2AfePredeemp[i] = config->usb2_ports[i].tx_emp_enable;</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/27766/3/src/soc/intel/cannonlake/chip.c@262">Patch Set #3, Line 262:</a> <code style="font-family:monospace,monospace">                    params->Usb3HsioTxDeEmph[i] = config->usb3_ports[i].tx_de_emp;</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/27766/3/src/soc/intel/cannonlake/chip.c@266">Patch Set #3, Line 266:</a> <code style="font-family:monospace,monospace">                       params->Usb3HsioTxDownscaleAmp[i] = config->usb3_ports[i].tx_downscale_amp;</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/27766/3/src/soc/intel/cannonlake/chip.c@295">Patch Set #3, Line 295:</a> <code style="font-family:monospace,monospace">                  params->PchScsEmmcHs400RxStrobeDll1 = config->EmmcHs400RxStrobeDll1;</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/27766/3/src/soc/intel/cannonlake/chip.c@296">Patch Set #3, Line 296:</a> <code style="font-family:monospace,monospace">                 params->PchScsEmmcHs400TxDataDll = config->EmmcHs400TxDataDll;</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li></ul></li></ul><p>To view, visit <a href="https://review.coreboot.org/27766">change 27766</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/27766"/><meta itemprop="name" content="View Change"/></div></div>

<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: comment </div>
<div style="display:none"> Gerrit-Change-Id: Ia36cfab03c4613786e5580a039d89007b630adf9 </div>
<div style="display:none"> Gerrit-Change-Number: 27766 </div>
<div style="display:none"> Gerrit-PatchSet: 3 </div>
<div style="display:none"> Gerrit-Owner: Lijian Zhao <lijian.zhao@intel.com> </div>
<div style="display:none"> Gerrit-Reviewer: Aaron Durbin <adurbin@chromium.org> </div>
<div style="display:none"> Gerrit-Reviewer: Furquan Shaikh <furquan@google.com> </div>
<div style="display:none"> Gerrit-Reviewer: Krzysztof M Sywula <krzysztof.m.sywula@intel.com> </div>
<div style="display:none"> Gerrit-Reviewer: Paul Menzel <paulepanter@users.sourceforge.net> </div>
<div style="display:none"> Gerrit-Reviewer: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com> </div>
<div style="display:none"> Gerrit-Reviewer: build bot (Jenkins) <no-reply@coreboot.org> </div>
<div style="display:none"> Gerrit-Comment-Date: Thu, 02 Aug 2018 16:26:44 +0000 </div>
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