<p>Tristan Corrick has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/27795">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">superio/nuvoton/nct6776/acpi: Add parallel port support<br><br>Exposing the parallel port via ACPI causes Linux to automatically detect<br>the parallel port and load the appropriate modules. Tested on an ASUS<br>P8H61-M LX with Linux 4.9.110 and 4.17.8.<br><br>However, no parallel port device has been tested.<br><br>Change-Id: I2529a074e24433d093ad0650a45c7b29238620f3<br>Signed-off-by: Tristan Corrick <tristan@corrick.kiwi><br>---<br>M src/superio/nuvoton/nct6776/acpi/superio.asl<br>1 file changed, 30 insertions(+), 0 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/27795/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/superio/nuvoton/nct6776/acpi/superio.asl b/src/superio/nuvoton/nct6776/acpi/superio.asl</span><br><span>index b985115..980eab9 100644</span><br><span>--- a/src/superio/nuvoton/nct6776/acpi/superio.asl</span><br><span>+++ b/src/superio/nuvoton/nct6776/acpi/superio.asl</span><br><span>@@ -23,6 +23,7 @@</span><br><span> * devices, disabling and reenabling logical devices.</span><br><span> *</span><br><span> * LDN State</span><br><span style="color: hsl(120, 100%, 40%);">+ * 0x1 PP Implemented, untested</span><br><span> * 0x2 SP1 Implemented, untested</span><br><span> * 0x5 KBC Implemented, untested</span><br><span> * 0x8 GPIO Implemented, untested</span><br><span>@@ -31,6 +32,7 @@</span><br><span> * Controllable through preprocessor defines:</span><br><span> * SUPERIO_DEV Device identifier for this SIO (e.g. SIO0)</span><br><span> * SUPERIO_PNP_BASE I/O address of the first PnP configuration register</span><br><span style="color: hsl(120, 100%, 40%);">+ * NCT6776_SHOW_PP If defined, the parallel port will be exposed.</span><br><span> * NCT6776_SHOW_SP1 If defined, Serial Port 1 will be exposed.</span><br><span> * NCT6776_SHOW_KBC If defined, the Keyboard Controller will be exposed.</span><br><span> * NCT6776_SHOW_GPIO If defined, GPIO support will be exposed.</span><br><span>@@ -85,6 +87,8 @@</span><br><span> PNP_IRQ0, 8, /* First IRQ */</span><br><span> Offset (0x72),</span><br><span> PNP_IRQ1, 8, /* Second IRQ */</span><br><span style="color: hsl(120, 100%, 40%);">+ Offset (0x74),</span><br><span style="color: hsl(120, 100%, 40%);">+ PNP_DMA0, 8, /* DRQ */</span><br><span> }</span><br><span> </span><br><span> Method (_CRS)</span><br><span>@@ -107,6 +111,32 @@</span><br><span> #define PNP_EXIT_MAGIC_1ST 0xaa</span><br><span> #include <superio/acpi/pnp_config.asl></span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+#ifdef NCT6776_SHOW_PP</span><br><span style="color: hsl(120, 100%, 40%);">+ #undef SUPERIO_PNP_HID</span><br><span style="color: hsl(120, 100%, 40%);">+ #undef SUPERIO_PNP_LDN</span><br><span style="color: hsl(120, 100%, 40%);">+ #undef SUPERIO_PNP_DDN</span><br><span style="color: hsl(120, 100%, 40%);">+ #undef SUPERIO_PNP_PM_REG</span><br><span style="color: hsl(120, 100%, 40%);">+ #undef SUPERIO_PNP_PM_VAL</span><br><span style="color: hsl(120, 100%, 40%);">+ #undef SUPERIO_PNP_PM_LDN</span><br><span style="color: hsl(120, 100%, 40%);">+ #undef SUPERIO_PNP_IO0</span><br><span style="color: hsl(120, 100%, 40%);">+ #undef SUPERIO_PNP_IO1</span><br><span style="color: hsl(120, 100%, 40%);">+ #undef SUPERIO_PNP_IO2</span><br><span style="color: hsl(120, 100%, 40%);">+ #undef SUPERIO_PNP_IRQ0</span><br><span style="color: hsl(120, 100%, 40%);">+ #undef SUPERIO_PNP_IRQ1</span><br><span style="color: hsl(120, 100%, 40%);">+ #undef SUPERIO_PNP_DMA</span><br><span style="color: hsl(120, 100%, 40%);">+ /*</span><br><span style="color: hsl(120, 100%, 40%);">+ * The extra code required to dynamically reflect ECP in the HID</span><br><span style="color: hsl(120, 100%, 40%);">+ * isn't currently justified, so the HID is hardcoded as not</span><br><span style="color: hsl(120, 100%, 40%);">+ * using ECP. "PNP0401" would indicate ECP.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+ #define SUPERIO_PNP_HID "PNP0400"</span><br><span style="color: hsl(120, 100%, 40%);">+ #define SUPERIO_PNP_LDN 1</span><br><span style="color: hsl(120, 100%, 40%);">+ #define SUPERIO_PNP_IO0 0x08, 0x08</span><br><span style="color: hsl(120, 100%, 40%);">+ #define SUPERIO_PNP_IRQ0</span><br><span style="color: hsl(120, 100%, 40%);">+ #define SUPERIO_PNP_DMA</span><br><span style="color: hsl(120, 100%, 40%);">+ #include <superio/acpi/pnp_generic.asl></span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> #ifdef NCT6776_SHOW_SP1</span><br><span> #undef SUPERIO_UART_LDN</span><br><span> #undef SUPERIO_UART_DDN</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/27795">change 27795</a>. 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<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I2529a074e24433d093ad0650a45c7b29238620f3 </div>
<div style="display:none"> Gerrit-Change-Number: 27795 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Tristan Corrick <tristan@corrick.kiwi> </div>