<p>Tristan Corrick has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/27798">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">mainboard: Add ASUS P8H61-M LX<br><br>Tested with GRUB 2.02 as a payload, booting Debian GNU/Linux 9.5 with<br>kernel 4.9. This code is based on the output of autoport.<br><br>The file `data.vbt` matches the VBT in the latest version of the vendor<br>firmware (version 4601).<br><br>This board works well under coreboot. A list of what works and what<br>doesn't can be found in the documentation part of this commit. To<br>summarise: the only known issues are that that S3 suspend/resume doesn't<br>work, and that there is no automatic fan control via the super I/O.<br><br>Change-Id: I2a0579f486d3a44de2dd927fa1e76b90c3b48f62<br>Signed-off-by: Tristan Corrick <tristan@corrick.kiwi><br>---<br>A Documentation/mainboard/asus/p8h61-m_lx.md<br>M Documentation/mainboard/index.md<br>A src/mainboard/asus/p8h61-m_lx/Kconfig<br>A src/mainboard/asus/p8h61-m_lx/Kconfig.name<br>A src/mainboard/asus/p8h61-m_lx/Makefile.inc<br>A src/mainboard/asus/p8h61-m_lx/acpi/ec.asl<br>A src/mainboard/asus/p8h61-m_lx/acpi/platform.asl<br>A src/mainboard/asus/p8h61-m_lx/acpi/superio.asl<br>A src/mainboard/asus/p8h61-m_lx/acpi_tables.c<br>A src/mainboard/asus/p8h61-m_lx/board_info.txt<br>A src/mainboard/asus/p8h61-m_lx/cmos.default<br>A src/mainboard/asus/p8h61-m_lx/cmos.layout<br>A src/mainboard/asus/p8h61-m_lx/data.vbt<br>A src/mainboard/asus/p8h61-m_lx/devicetree.cb<br>A src/mainboard/asus/p8h61-m_lx/dsdt.asl<br>A src/mainboard/asus/p8h61-m_lx/gma-mainboard.ads<br>A src/mainboard/asus/p8h61-m_lx/gpio.c<br>A src/mainboard/asus/p8h61-m_lx/hda_verb.c<br>A src/mainboard/asus/p8h61-m_lx/mainboard.c<br>A src/mainboard/asus/p8h61-m_lx/romstage.c<br>20 files changed, 892 insertions(+), 0 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/27798/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/Documentation/mainboard/asus/p8h61-m_lx.md b/Documentation/mainboard/asus/p8h61-m_lx.md</span><br><span>new file mode 100644</span><br><span>index 0000000..1ff22f8</span><br><span>--- /dev/null</span><br><span>+++ b/Documentation/mainboard/asus/p8h61-m_lx.md</span><br><span>@@ -0,0 +1,120 @@</span><br><span style="color: hsl(120, 100%, 40%);">+# ASUS P8H61-M LX</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+This page describes how to run coreboot on the [ASUS P8H61-M LX].</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+## Flashing coreboot</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+```eval_rst</span><br><span style="color: hsl(120, 100%, 40%);">++---------------------+------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| Type | Value |</span><br><span style="color: hsl(120, 100%, 40%);">++=====================+============+</span><br><span style="color: hsl(120, 100%, 40%);">+| Socketed flash | yes |</span><br><span style="color: hsl(120, 100%, 40%);">++---------------------+------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| Model | W25Q32BV |</span><br><span style="color: hsl(120, 100%, 40%);">++---------------------+------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| Size | 4 MiB |</span><br><span style="color: hsl(120, 100%, 40%);">++---------------------+------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| Package | DIP-8 |</span><br><span style="color: hsl(120, 100%, 40%);">++---------------------+------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| Write protection | no |</span><br><span style="color: hsl(120, 100%, 40%);">++---------------------+------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| Dual BIOS feature | no |</span><br><span style="color: hsl(120, 100%, 40%);">++---------------------+------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| Internal flashing | yes |</span><br><span style="color: hsl(120, 100%, 40%);">++---------------------+------------+</span><br><span style="color: hsl(120, 100%, 40%);">+```</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+### Internal programming</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+The main SPI flash can be accessed using [flashrom]. By default, only</span><br><span style="color: hsl(120, 100%, 40%);">+the BIOS region of the flash is writable. If you wish to change any</span><br><span style="color: hsl(120, 100%, 40%);">+other region (Management Engine or flash descriptor), then an external</span><br><span style="color: hsl(120, 100%, 40%);">+programmer is required.</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+The following command may be used to flash coreboot:</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+```</span><br><span style="color: hsl(120, 100%, 40%);">+$ sudo flashrom --noverify-all --ifd -i bios -p internal -w coreboot.rom</span><br><span style="color: hsl(120, 100%, 40%);">+```</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+The use of `--noverify-all` is required since the Management Engine</span><br><span style="color: hsl(120, 100%, 40%);">+region is not readable even by the host.</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+## Known issues</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+- S3 suspend/resume does not work. This is the case for both coreboot</span><br><span style="color: hsl(120, 100%, 40%);">+ and the vendor firmware, tested with Linux 4.9, Linux 4.17, and</span><br><span style="color: hsl(120, 100%, 40%);">+ OpenBSD 6.3. Interestingly, it is possible to resume from S3 with</span><br><span style="color: hsl(120, 100%, 40%);">+ Linux, but _only_ if the resume is started immediately after the</span><br><span style="color: hsl(120, 100%, 40%);">+ suspend.</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+- There is no automatic, OS-independent fan control. This is because</span><br><span style="color: hsl(120, 100%, 40%);">+ the super I/O hardware monitor can only obtain valid CPU temperature</span><br><span style="color: hsl(120, 100%, 40%);">+ readings from the PECI agent, whose complete initialisation is not</span><br><span style="color: hsl(120, 100%, 40%);">+ publicly documented. The `coretemp` driver can still be used for</span><br><span style="color: hsl(120, 100%, 40%);">+ accurate CPU temperature readings.</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+## Untested</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+- PCIe graphics</span><br><span style="color: hsl(120, 100%, 40%);">+- parallel port</span><br><span style="color: hsl(120, 100%, 40%);">+- PS/2 keyboard</span><br><span style="color: hsl(120, 100%, 40%);">+- EHCI debug</span><br><span style="color: hsl(120, 100%, 40%);">+- S/PDIF audio</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+## Working</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+- USB</span><br><span style="color: hsl(120, 100%, 40%);">+- Gigabit Ethernet</span><br><span style="color: hsl(120, 100%, 40%);">+- integrated graphics</span><br><span style="color: hsl(120, 100%, 40%);">+- PCIe</span><br><span style="color: hsl(120, 100%, 40%);">+- SATA</span><br><span style="color: hsl(120, 100%, 40%);">+- PS/2 mouse</span><br><span style="color: hsl(120, 100%, 40%);">+- serial port</span><br><span style="color: hsl(120, 100%, 40%);">+- hardware monitor (see [Known issues](#known-issues) for caveats)</span><br><span style="color: hsl(120, 100%, 40%);">+- onboard audio</span><br><span style="color: hsl(120, 100%, 40%);">+- front panel audio</span><br><span style="color: hsl(120, 100%, 40%);">+- native raminit (2 x 2GB, DDR3-1333)</span><br><span style="color: hsl(120, 100%, 40%);">+- native graphics init (libgfxinit)</span><br><span style="color: hsl(120, 100%, 40%);">+- flashrom under the vendor firmware</span><br><span style="color: hsl(120, 100%, 40%);">+- flashrom under coreboot</span><br><span style="color: hsl(120, 100%, 40%);">+- Wake-on-LAN</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+## me_cleaner</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+If using `me_cleaner` to remove modules from the Management Engine,</span><br><span style="color: hsl(120, 100%, 40%);">+you might experience some issues (incorrect super I/O readings,</span><br><span style="color: hsl(120, 100%, 40%);">+kernel warnings about loading audio codecs). If you add the argument</span><br><span style="color: hsl(120, 100%, 40%);">+`--whitelist EFFS,FOVD,MDES,FCRS` when running `me_cleaner`, the</span><br><span style="color: hsl(120, 100%, 40%);">+resulting ME should still allow correct system operation while having</span><br><span style="color: hsl(120, 100%, 40%);">+most of its code removed. You may be able to whitelist fewer modules,</span><br><span style="color: hsl(120, 100%, 40%);">+but this is not yet tested. Additionally, setting the AltMeDisable bit</span><br><span style="color: hsl(120, 100%, 40%);">+doesn't appear to cause any problems.</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+## Technology</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+```eval_rst</span><br><span style="color: hsl(120, 100%, 40%);">++------------------+--------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| Northbridge | :doc:`../../northbridge/intel/sandybridge/index` |</span><br><span style="color: hsl(120, 100%, 40%);">++------------------+--------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| Southbridge | bd82x6x |</span><br><span style="color: hsl(120, 100%, 40%);">++------------------+--------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| CPU | model_206ax |</span><br><span style="color: hsl(120, 100%, 40%);">++------------------+--------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| Super I/O | Nuvoton NCT6776 |</span><br><span style="color: hsl(120, 100%, 40%);">++------------------+--------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| EC | None |</span><br><span style="color: hsl(120, 100%, 40%);">++------------------+--------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| Coprocessor | Intel Management Engine |</span><br><span style="color: hsl(120, 100%, 40%);">++------------------+--------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+```</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+## Extra resources</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+- [Board manual]</span><br><span style="color: hsl(120, 100%, 40%);">+- [Flash chip datasheet][W25Q32BV]</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+[ASUS P8H61-M LX]: https://www.asus.com/Motherboards/P8H61M_LX/</span><br><span style="color: hsl(120, 100%, 40%);">+[W25Q32BV]: https://www.winbond.com/resource-files/w25q32bv_revi_100413_wo_automotive.pdf</span><br><span style="color: hsl(120, 100%, 40%);">+[flashrom]: https://flashrom.org/Flashrom</span><br><span style="color: hsl(120, 100%, 40%);">+[Board manual]: http://dlcdnet.asus.com/pub/ASUS/mb/LGA1155/P8H61_M_LX/E6803_P8H61-M_LX.zip</span><br><span>diff --git a/Documentation/mainboard/index.md b/Documentation/mainboard/index.md</span><br><span>index 5d41cec..8bf0963 100644</span><br><span>--- a/Documentation/mainboard/index.md</span><br><span>+++ b/Documentation/mainboard/index.md</span><br><span>@@ -2,6 +2,10 @@</span><br><span> </span><br><span> This section contains documentation about coreboot on specific mainboards.</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+## ASUS</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+- [P8H61-M LX](asus/p8h61-m_lx.md)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> ## Cavium</span><br><span> </span><br><span> - [CN81XX EVB SFF](cavium/cn8100_sff_evb.md)</span><br><span>diff --git a/src/mainboard/asus/p8h61-m_lx/Kconfig b/src/mainboard/asus/p8h61-m_lx/Kconfig</span><br><span>new file mode 100644</span><br><span>index 0000000..715ba25</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/asus/p8h61-m_lx/Kconfig</span><br><span>@@ -0,0 +1,63 @@</span><br><span style="color: hsl(120, 100%, 40%);">+##</span><br><span style="color: hsl(120, 100%, 40%);">+## This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+##</span><br><span style="color: hsl(120, 100%, 40%);">+## Copyright (C) 2018 Tristan Corrick <tristan@corrick.kiwi></span><br><span style="color: hsl(120, 100%, 40%);">+##</span><br><span style="color: hsl(120, 100%, 40%);">+## This program is free software: you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+## it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+## the Free Software Foundation, either version 2 of the License, or</span><br><span style="color: hsl(120, 100%, 40%);">+## (at your option) any later version.</span><br><span style="color: hsl(120, 100%, 40%);">+##</span><br><span style="color: hsl(120, 100%, 40%);">+## This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+## but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+## GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+##</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+if BOARD_ASUS_P8H61_M_LX</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+config BOARD_SPECIFIC_OPTIONS</span><br><span style="color: hsl(120, 100%, 40%);">+ def_bool y</span><br><span style="color: hsl(120, 100%, 40%);">+ select BOARD_ROMSIZE_KB_4096</span><br><span style="color: hsl(120, 100%, 40%);">+ select CPU_INTEL_SOCKET_LGA1155</span><br><span style="color: hsl(120, 100%, 40%);">+ select HAVE_ACPI_RESUME</span><br><span style="color: hsl(120, 100%, 40%);">+ select HAVE_ACPI_TABLES</span><br><span style="color: hsl(120, 100%, 40%);">+ select HAVE_OPTION_TABLE</span><br><span style="color: hsl(120, 100%, 40%);">+ select HAVE_CMOS_DEFAULT</span><br><span style="color: hsl(120, 100%, 40%);">+ select INTEL_GMA_HAVE_VBT</span><br><span style="color: hsl(120, 100%, 40%);">+ select INTEL_INT15</span><br><span style="color: hsl(120, 100%, 40%);">+ select MAINBOARD_HAS_LIBGFXINIT</span><br><span style="color: hsl(120, 100%, 40%);">+ select NORTHBRIDGE_INTEL_SANDYBRIDGE</span><br><span style="color: hsl(120, 100%, 40%);">+ select REALTEK_8168_RESET</span><br><span style="color: hsl(120, 100%, 40%);">+ select RT8168_SET_LED_MODE</span><br><span style="color: hsl(120, 100%, 40%);">+ select SERIRQ_CONTINUOUS_MODE</span><br><span style="color: hsl(120, 100%, 40%);">+ select SOUTHBRIDGE_INTEL_BD82X6X</span><br><span style="color: hsl(120, 100%, 40%);">+ select SUPERIO_NUVOTON_NCT6776</span><br><span style="color: hsl(120, 100%, 40%);">+ select SUPERIO_NUVOTON_NCT6776_COM_A</span><br><span style="color: hsl(120, 100%, 40%);">+ select USE_NATIVE_RAMINIT</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+config HAVE_IFD_BIN</span><br><span style="color: hsl(120, 100%, 40%);">+ bool</span><br><span style="color: hsl(120, 100%, 40%);">+ default n</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+config MAINBOARD_DIR</span><br><span style="color: hsl(120, 100%, 40%);">+ string</span><br><span style="color: hsl(120, 100%, 40%);">+ default asus/p8h61-m_lx</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+config MAINBOARD_PART_NUMBER</span><br><span style="color: hsl(120, 100%, 40%);">+ string</span><br><span style="color: hsl(120, 100%, 40%);">+ default "P8H61-M LX"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID</span><br><span style="color: hsl(120, 100%, 40%);">+ hex</span><br><span style="color: hsl(120, 100%, 40%);">+ default 0x844d</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID</span><br><span style="color: hsl(120, 100%, 40%);">+ hex</span><br><span style="color: hsl(120, 100%, 40%);">+ default 0x1043</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+config MAX_CPUS</span><br><span style="color: hsl(120, 100%, 40%);">+ int</span><br><span style="color: hsl(120, 100%, 40%);">+ default 8</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+endif</span><br><span>diff --git a/src/mainboard/asus/p8h61-m_lx/Kconfig.name b/src/mainboard/asus/p8h61-m_lx/Kconfig.name</span><br><span>new file mode 100644</span><br><span>index 0000000..d62f437</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/asus/p8h61-m_lx/Kconfig.name</span><br><span>@@ -0,0 +1,2 @@</span><br><span style="color: hsl(120, 100%, 40%);">+config BOARD_ASUS_P8H61_M_LX</span><br><span style="color: hsl(120, 100%, 40%);">+ bool "P8H61-M LX"</span><br><span>diff --git a/src/mainboard/asus/p8h61-m_lx/Makefile.inc b/src/mainboard/asus/p8h61-m_lx/Makefile.inc</span><br><span>new file mode 100644</span><br><span>index 0000000..7c1bf9e</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/asus/p8h61-m_lx/Makefile.inc</span><br><span>@@ -0,0 +1,18 @@</span><br><span style="color: hsl(120, 100%, 40%);">+##</span><br><span style="color: hsl(120, 100%, 40%);">+## This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+##</span><br><span style="color: hsl(120, 100%, 40%);">+## Copyright (C) 2018 Tristan Corrick <tristan@corrick.kiwi></span><br><span style="color: hsl(120, 100%, 40%);">+##</span><br><span style="color: hsl(120, 100%, 40%);">+## This program is free software: you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+## it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+## the Free Software Foundation, either version 2 of the License, or</span><br><span style="color: hsl(120, 100%, 40%);">+## (at your option) any later version.</span><br><span style="color: hsl(120, 100%, 40%);">+##</span><br><span style="color: hsl(120, 100%, 40%);">+## This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+## but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+## GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+##</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+romstage-y += gpio.c</span><br><span style="color: hsl(120, 100%, 40%);">+ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads</span><br><span>diff --git a/src/mainboard/asus/p8h61-m_lx/acpi/ec.asl b/src/mainboard/asus/p8h61-m_lx/acpi/ec.asl</span><br><span>new file mode 100644</span><br><span>index 0000000..e69de29</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/asus/p8h61-m_lx/acpi/ec.asl</span><br><span>diff --git a/src/mainboard/asus/p8h61-m_lx/acpi/platform.asl b/src/mainboard/asus/p8h61-m_lx/acpi/platform.asl</span><br><span>new file mode 100644</span><br><span>index 0000000..adaf51a</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/asus/p8h61-m_lx/acpi/platform.asl</span><br><span>@@ -0,0 +1,24 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2017 Tristan Corrick <tristan@corrick.kiwi></span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software: you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation, either version 2 of the License, or</span><br><span style="color: hsl(120, 100%, 40%);">+ * (at your option) any later version.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+Method(_WAK, 1)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ Return (Package() { 0, 0 })</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+Method(_PTS, 1)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span>diff --git a/src/mainboard/asus/p8h61-m_lx/acpi/superio.asl b/src/mainboard/asus/p8h61-m_lx/acpi/superio.asl</span><br><span>new file mode 100644</span><br><span>index 0000000..b671e3c</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/asus/p8h61-m_lx/acpi/superio.asl</span><br><span>@@ -0,0 +1,26 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2018 Tristan Corrick <tristan@corrick.kiwi></span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software: you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation, either version 2 of the License, or</span><br><span style="color: hsl(120, 100%, 40%);">+ * (at your option) any later version.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define SUPERIO_DEV SIO0</span><br><span style="color: hsl(120, 100%, 40%);">+#define SUPERIO_PNP_BASE 0x2e</span><br><span style="color: hsl(120, 100%, 40%);">+#define NCT6776_SHOW_PP</span><br><span style="color: hsl(120, 100%, 40%);">+#define NCT6776_SHOW_SP1</span><br><span style="color: hsl(120, 100%, 40%);">+#define NCT6776_SHOW_KBC</span><br><span style="color: hsl(120, 100%, 40%);">+#define NCT6776_SHOW_HWM</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#undef NCT6776_SHOW_GPIO</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <superio/nuvoton/nct6776/acpi/superio.asl></span><br><span>diff --git a/src/mainboard/asus/p8h61-m_lx/acpi_tables.c b/src/mainboard/asus/p8h61-m_lx/acpi_tables.c</span><br><span>new file mode 100644</span><br><span>index 0000000..1a584e0</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/asus/p8h61-m_lx/acpi_tables.c</span><br><span>@@ -0,0 +1,21 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2017 Tristan Corrick <tristan@corrick.kiwi></span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software: you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation, either version 2 of the License, or</span><br><span style="color: hsl(120, 100%, 40%);">+ * (at your option) any later version.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <southbridge/intel/bd82x6x/nvs.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+void acpi_create_gnvs(global_nvs_t *gnvs)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span>diff --git a/src/mainboard/asus/p8h61-m_lx/board_info.txt b/src/mainboard/asus/p8h61-m_lx/board_info.txt</span><br><span>new file mode 100644</span><br><span>index 0000000..9c7f972</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/asus/p8h61-m_lx/board_info.txt</span><br><span>@@ -0,0 +1,7 @@</span><br><span style="color: hsl(120, 100%, 40%);">+Category: desktop</span><br><span style="color: hsl(120, 100%, 40%);">+Board URL: https://www.asus.com/Motherboards/P8H61M_LX/</span><br><span style="color: hsl(120, 100%, 40%);">+ROM package: DIP-8</span><br><span style="color: hsl(120, 100%, 40%);">+ROM protocol: SPI</span><br><span style="color: hsl(120, 100%, 40%);">+ROM socketed: y</span><br><span style="color: hsl(120, 100%, 40%);">+Flashrom support: y</span><br><span style="color: hsl(120, 100%, 40%);">+Release year: 2011</span><br><span>diff --git a/src/mainboard/asus/p8h61-m_lx/cmos.default b/src/mainboard/asus/p8h61-m_lx/cmos.default</span><br><span>new file mode 100644</span><br><span>index 0000000..d3812ab</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/asus/p8h61-m_lx/cmos.default</span><br><span>@@ -0,0 +1,6 @@</span><br><span style="color: hsl(120, 100%, 40%);">+boot_option=Fallback</span><br><span style="color: hsl(120, 100%, 40%);">+debug_level=Debug</span><br><span style="color: hsl(120, 100%, 40%);">+gfx_uma_size=64M</span><br><span style="color: hsl(120, 100%, 40%);">+nmi=Enable</span><br><span style="color: hsl(120, 100%, 40%);">+power_on_after_fail=Disable</span><br><span style="color: hsl(120, 100%, 40%);">+sata_mode=AHCI</span><br><span>diff --git a/src/mainboard/asus/p8h61-m_lx/cmos.layout b/src/mainboard/asus/p8h61-m_lx/cmos.layout</span><br><span>new file mode 100644</span><br><span>index 0000000..9fe6fc2</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/asus/p8h61-m_lx/cmos.layout</span><br><span>@@ -0,0 +1,114 @@</span><br><span style="color: hsl(120, 100%, 40%);">+##</span><br><span style="color: hsl(120, 100%, 40%);">+## This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+##</span><br><span style="color: hsl(120, 100%, 40%);">+## Copyright (C) 2007-2008 coresystems GmbH</span><br><span style="color: hsl(120, 100%, 40%);">+## Copyright (C) 2014 Vladimir Serbinenko</span><br><span style="color: hsl(120, 100%, 40%);">+##</span><br><span style="color: hsl(120, 100%, 40%);">+## This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+## it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+## the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+##</span><br><span style="color: hsl(120, 100%, 40%);">+## This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+## but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+## GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+##</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+# -----------------------------------------------------------------</span><br><span style="color: hsl(120, 100%, 40%);">+entries</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+# -----------------------------------------------------------------</span><br><span style="color: hsl(120, 100%, 40%);">+# Status Register A</span><br><span style="color: hsl(120, 100%, 40%);">+# -----------------------------------------------------------------</span><br><span style="color: hsl(120, 100%, 40%);">+# Status Register B</span><br><span style="color: hsl(120, 100%, 40%);">+# -----------------------------------------------------------------</span><br><span style="color: hsl(120, 100%, 40%);">+# Status Register C</span><br><span style="color: hsl(120, 100%, 40%);">+#96 4 r 0 status_c_rsvd</span><br><span style="color: hsl(120, 100%, 40%);">+#100 1 r 0 uf_flag</span><br><span style="color: hsl(120, 100%, 40%);">+#101 1 r 0 af_flag</span><br><span style="color: hsl(120, 100%, 40%);">+#102 1 r 0 pf_flag</span><br><span style="color: hsl(120, 100%, 40%);">+#103 1 r 0 irqf_flag</span><br><span style="color: hsl(120, 100%, 40%);">+# -----------------------------------------------------------------</span><br><span style="color: hsl(120, 100%, 40%);">+# Status Register D</span><br><span style="color: hsl(120, 100%, 40%);">+#104 7 r 0 status_d_rsvd</span><br><span style="color: hsl(120, 100%, 40%);">+#111 1 r 0 valid_cmos_ram</span><br><span style="color: hsl(120, 100%, 40%);">+# -----------------------------------------------------------------</span><br><span style="color: hsl(120, 100%, 40%);">+# Diagnostic Status Register</span><br><span style="color: hsl(120, 100%, 40%);">+#112 8 r 0 diag_rsvd1</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+# -----------------------------------------------------------------</span><br><span style="color: hsl(120, 100%, 40%);">+0 120 r 0 reserved_memory</span><br><span style="color: hsl(120, 100%, 40%);">+#120 264 r 0 unused</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+# -----------------------------------------------------------------</span><br><span style="color: hsl(120, 100%, 40%);">+# RTC_BOOT_BYTE (coreboot hardcoded)</span><br><span style="color: hsl(120, 100%, 40%);">+384 1 e 3 boot_option</span><br><span style="color: hsl(120, 100%, 40%);">+388 4 h 0 reboot_counter</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+# -----------------------------------------------------------------</span><br><span style="color: hsl(120, 100%, 40%);">+# coreboot config options: console</span><br><span style="color: hsl(120, 100%, 40%);">+#392 3 r 0 unused</span><br><span style="color: hsl(120, 100%, 40%);">+395 4 e 4 debug_level</span><br><span style="color: hsl(120, 100%, 40%);">+#399 1 r 0 unused</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#400 8 r 0 reserved for century byte</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+# coreboot config options: southbridge</span><br><span style="color: hsl(120, 100%, 40%);">+408 1 e 1 nmi</span><br><span style="color: hsl(120, 100%, 40%);">+409 2 e 5 power_on_after_fail</span><br><span style="color: hsl(120, 100%, 40%);">+411 1 e 6 sata_mode</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+# coreboot config options: northbridge</span><br><span style="color: hsl(120, 100%, 40%);">+412 3 e 7 gfx_uma_size</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+# SandyBridge MRC Scrambler Seed values</span><br><span style="color: hsl(120, 100%, 40%);">+896 32 r 0 mrc_scrambler_seed</span><br><span style="color: hsl(120, 100%, 40%);">+928 32 r 0 mrc_scrambler_seed_s3</span><br><span style="color: hsl(120, 100%, 40%);">+960 16 r 0 mrc_scrambler_seed_chk</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+# coreboot config options: check sums</span><br><span style="color: hsl(120, 100%, 40%);">+984 16 h 0 check_sum</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+# -----------------------------------------------------------------</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+enumerations</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#ID value text</span><br><span style="color: hsl(120, 100%, 40%);">+1 0 Disable</span><br><span style="color: hsl(120, 100%, 40%);">+1 1 Enable</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+2 0 Enable</span><br><span style="color: hsl(120, 100%, 40%);">+2 1 Disable</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+3 0 Fallback</span><br><span style="color: hsl(120, 100%, 40%);">+3 1 Normal</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+4 0 Emergency</span><br><span style="color: hsl(120, 100%, 40%);">+4 1 Alert</span><br><span style="color: hsl(120, 100%, 40%);">+4 2 Critical</span><br><span style="color: hsl(120, 100%, 40%);">+4 3 Error</span><br><span style="color: hsl(120, 100%, 40%);">+4 4 Warning</span><br><span style="color: hsl(120, 100%, 40%);">+4 5 Notice</span><br><span style="color: hsl(120, 100%, 40%);">+4 6 Info</span><br><span style="color: hsl(120, 100%, 40%);">+4 7 Debug</span><br><span style="color: hsl(120, 100%, 40%);">+4 8 Spew</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+5 0 Disable</span><br><span style="color: hsl(120, 100%, 40%);">+5 1 Enable</span><br><span style="color: hsl(120, 100%, 40%);">+5 2 Keep</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+6 0 AHCI</span><br><span style="color: hsl(120, 100%, 40%);">+6 1 Compatible</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+7 0 32M</span><br><span style="color: hsl(120, 100%, 40%);">+7 1 64M</span><br><span style="color: hsl(120, 100%, 40%);">+7 2 96M</span><br><span style="color: hsl(120, 100%, 40%);">+7 3 128M</span><br><span style="color: hsl(120, 100%, 40%);">+7 4 160M</span><br><span style="color: hsl(120, 100%, 40%);">+7 5 192M</span><br><span style="color: hsl(120, 100%, 40%);">+7 6 224M</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+# -----------------------------------------------------------------</span><br><span style="color: hsl(120, 100%, 40%);">+checksums</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+checksum 392 415 984</span><br><span>diff --git a/src/mainboard/asus/p8h61-m_lx/data.vbt b/src/mainboard/asus/p8h61-m_lx/data.vbt</span><br><span>new file mode 100644</span><br><span>index 0000000..7eda3ab</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/asus/p8h61-m_lx/data.vbt</span><br><span>Binary files differ</span><br><span>diff --git a/src/mainboard/asus/p8h61-m_lx/devicetree.cb b/src/mainboard/asus/p8h61-m_lx/devicetree.cb</span><br><span>new file mode 100644</span><br><span>index 0000000..5a40b31</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/asus/p8h61-m_lx/devicetree.cb</span><br><span>@@ -0,0 +1,137 @@</span><br><span style="color: hsl(120, 100%, 40%);">+##</span><br><span style="color: hsl(120, 100%, 40%);">+## This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+##</span><br><span style="color: hsl(120, 100%, 40%);">+## Copyright (C) 2018 Tristan Corrick <tristan@corrick.kiwi></span><br><span style="color: hsl(120, 100%, 40%);">+##</span><br><span style="color: hsl(120, 100%, 40%);">+## This program is free software: you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+## it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+## the Free Software Foundation, either version 2 of the License, or</span><br><span style="color: hsl(120, 100%, 40%);">+## (at your option) any later version.</span><br><span style="color: hsl(120, 100%, 40%);">+##</span><br><span style="color: hsl(120, 100%, 40%);">+## This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+## but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+## GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+##</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+chip northbridge/intel/sandybridge</span><br><span style="color: hsl(120, 100%, 40%);">+ device cpu_cluster 0 on</span><br><span style="color: hsl(120, 100%, 40%);">+ chip cpu/intel/socket_LGA1155</span><br><span style="color: hsl(120, 100%, 40%);">+ device lapic 0 on end</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ chip cpu/intel/model_206ax</span><br><span style="color: hsl(120, 100%, 40%);">+ register "c1_acpower" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "c1_battery" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "c2_acpower" = "3"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "c2_battery" = "3"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "c3_acpower" = "5"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "c3_battery" = "5"</span><br><span style="color: hsl(120, 100%, 40%);">+ device lapic 0xacac off end</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ register "pci_mmio_size" = "2048"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ device domain 0 on</span><br><span style="color: hsl(120, 100%, 40%);">+ subsystemid 0x1043 0x844d inherit</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 00.0 on end # Host bridge</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 01.0 on end # PCIe bridge for discrete graphics</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 02.0 on end # VGA controller</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ chip southbridge/intel/bd82x6x</span><br><span style="color: hsl(120, 100%, 40%);">+ register "c2_latency" = "101"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "gen1_dec" = "0x00000295" # Super I/O HWM</span><br><span style="color: hsl(120, 100%, 40%);">+ register "p_cnt_throttling_supported" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "sata_port_map" = "0x33"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "spi_lvscc" = "0x2005"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "spi_uvscc" = "0x2005"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 16.0 on end # Management Engine interface 1</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 16.1 off end # Management Engine interface 2</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 16.2 off end # Management Engine IDE-R</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 16.3 off end # Management Engine KT</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 19.0 off end # Intel Gigabit Ethernet</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1a.0 on end # USB2 EHCI #2</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1b.0 on # HD audio controller</span><br><span style="color: hsl(120, 100%, 40%);">+ subsystemid 0x1043 0x8445</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1c.0 on end # PCIe 1x slot (PCIEX1_1)</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1c.1 on end # PCIe 1x slot (PCIEX1_2)</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1c.2 on # Realtek Gigabit Ethernet</span><br><span style="color: hsl(120, 100%, 40%);">+ subsystemid 0x1043 0x8432</span><br><span style="color: hsl(120, 100%, 40%);">+ chip drivers/net</span><br><span style="color: hsl(120, 100%, 40%);">+ register "customized_leds" = "0x00f6"</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 00.0 on end</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1c.3 off end # Unused PCIe port</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1c.4 on end # PCIe 1x slot (PCIEX1_3)</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1c.5 off end # Unused PCIe port</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1c.6 off end # Unused PCIe port</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1c.7 off end # Unused PCIe port</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1d.0 on end # USB2 EHCI #1</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1e.0 off end # PCI bridge</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1f.0 on # LPC bridge</span><br><span style="color: hsl(120, 100%, 40%);">+ chip superio/nuvoton/nct6776</span><br><span style="color: hsl(120, 100%, 40%);">+ device pnp 2e.0 off end # Floppy</span><br><span style="color: hsl(120, 100%, 40%);">+ device pnp 2e.1 on # Parallel</span><br><span style="color: hsl(120, 100%, 40%);">+ io 0x60 = 0x0378</span><br><span style="color: hsl(120, 100%, 40%);">+ irq 0x70 = 7</span><br><span style="color: hsl(120, 100%, 40%);">+ drq 0x74 = 4 # No DMA</span><br><span style="color: hsl(120, 100%, 40%);">+ irq 0xf0 = 0x3c # Printer mode</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ device pnp 2e.2 on # UART A</span><br><span style="color: hsl(120, 100%, 40%);">+ io 0x60 = 0x03f8</span><br><span style="color: hsl(120, 100%, 40%);">+ irq 0x70 = 4</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ device pnp 2e.3 off end # UART B, IR</span><br><span style="color: hsl(120, 100%, 40%);">+ device pnp 2e.5 on # PS/2 KBC</span><br><span style="color: hsl(120, 100%, 40%);">+ io 0x60 = 0x0060</span><br><span style="color: hsl(120, 100%, 40%);">+ io 0x62 = 0x0064</span><br><span style="color: hsl(120, 100%, 40%);">+ irq 0x70 = 1 # Keyboard</span><br><span style="color: hsl(120, 100%, 40%);">+ irq 0x72 = 12 # Mouse</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ device pnp 2e.6 off end # CIR</span><br><span style="color: hsl(120, 100%, 40%);">+ device pnp 2e.7 off end # GPIO8</span><br><span style="color: hsl(120, 100%, 40%);">+ device pnp 2e.107 off end # GPIO9</span><br><span style="color: hsl(120, 100%, 40%);">+ device pnp 2e.8 off end # WDT</span><br><span style="color: hsl(120, 100%, 40%);">+ device pnp 2e.108 off end # GPIO0</span><br><span style="color: hsl(120, 100%, 40%);">+ device pnp 2e.208 off end # GPIOA</span><br><span style="color: hsl(120, 100%, 40%);">+ device pnp 2e.308 off end # GPIO base</span><br><span style="color: hsl(120, 100%, 40%);">+ device pnp 2e.109 off end # GPIO1</span><br><span style="color: hsl(120, 100%, 40%);">+ device pnp 2e.209 off end # GPIO2</span><br><span style="color: hsl(120, 100%, 40%);">+ device pnp 2e.309 off end # GPIO3</span><br><span style="color: hsl(120, 100%, 40%);">+ device pnp 2e.409 off end # GPIO4</span><br><span style="color: hsl(120, 100%, 40%);">+ device pnp 2e.509 off end # GPIO5</span><br><span style="color: hsl(120, 100%, 40%);">+ device pnp 2e.609 off end # GPIO6</span><br><span style="color: hsl(120, 100%, 40%);">+ device pnp 2e.709 off end # GPIO7</span><br><span style="color: hsl(120, 100%, 40%);">+ device pnp 2e.a on # ACPI</span><br><span style="color: hsl(120, 100%, 40%);">+ # Power RAM in S3.</span><br><span style="color: hsl(120, 100%, 40%);">+ irq 0xe4 = 0x10</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ device pnp 2e.b on # HWM, LED</span><br><span style="color: hsl(120, 100%, 40%);">+ io 0x60 = 0x0290</span><br><span style="color: hsl(120, 100%, 40%);">+ io 0x62 = 0x0200</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ # Global registers to select</span><br><span style="color: hsl(120, 100%, 40%);">+ # HWM/LED functions instead of</span><br><span style="color: hsl(120, 100%, 40%);">+ # floppy functions.</span><br><span style="color: hsl(120, 100%, 40%);">+ irq 0x1c = 0x03</span><br><span style="color: hsl(120, 100%, 40%);">+ irq 0x24 = 0x24</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ device pnp 2e.d off end # VID</span><br><span style="color: hsl(120, 100%, 40%);">+ device pnp 2e.e off end # CIR wake-up</span><br><span style="color: hsl(120, 100%, 40%);">+ device pnp 2e.f off end # GPIO PP/OD</span><br><span style="color: hsl(120, 100%, 40%);">+ device pnp 2e.14 off end # SVID</span><br><span style="color: hsl(120, 100%, 40%);">+ device pnp 2e.16 off end # Deep sleep</span><br><span style="color: hsl(120, 100%, 40%);">+ device pnp 2e.17 off end # GPIOA</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1f.2 on end # SATA controller 1</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1f.3 on end # SMBus</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1f.5 off end # SATA controller 2</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1f.6 off end # Thermal</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+end</span><br><span>diff --git a/src/mainboard/asus/p8h61-m_lx/dsdt.asl b/src/mainboard/asus/p8h61-m_lx/dsdt.asl</span><br><span>new file mode 100644</span><br><span>index 0000000..60cbde3</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/asus/p8h61-m_lx/dsdt.asl</span><br><span>@@ -0,0 +1,41 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2017 Tristan Corrick <tristan@corrick.kiwi></span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software: you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation, either version 2 of the License, or</span><br><span style="color: hsl(120, 100%, 40%);">+ * (at your option) any later version.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+DefinitionBlock(</span><br><span style="color: hsl(120, 100%, 40%);">+ "dsdt.aml",</span><br><span style="color: hsl(120, 100%, 40%);">+ "DSDT",</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x03, /* DSDT Revision: ACPI v3.0 */</span><br><span style="color: hsl(120, 100%, 40%);">+ "COREv4", /* OEM ID */</span><br><span style="color: hsl(120, 100%, 40%);">+ "COREBOOT", /* OEM Table ID */</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x20171231 /* OEM Revision */</span><br><span style="color: hsl(120, 100%, 40%);">+)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ #include "acpi/platform.asl"</span><br><span style="color: hsl(120, 100%, 40%);">+ #include <cpu/intel/model_206ax/acpi/cpu.asl></span><br><span style="color: hsl(120, 100%, 40%);">+ #include <southbridge/intel/bd82x6x/acpi/platform.asl></span><br><span style="color: hsl(120, 100%, 40%);">+ #include <southbridge/intel/bd82x6x/acpi/globalnvs.asl></span><br><span style="color: hsl(120, 100%, 40%);">+ #include <southbridge/intel/bd82x6x/acpi/sleepstates.asl></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ Scope (\_SB)</span><br><span style="color: hsl(120, 100%, 40%);">+ {</span><br><span style="color: hsl(120, 100%, 40%);">+ Device (PCI0)</span><br><span style="color: hsl(120, 100%, 40%);">+ {</span><br><span style="color: hsl(120, 100%, 40%);">+ #include <northbridge/intel/sandybridge/acpi/sandybridge.asl></span><br><span style="color: hsl(120, 100%, 40%);">+ #include <drivers/intel/gma/acpi/default_brightness_levels.asl></span><br><span style="color: hsl(120, 100%, 40%);">+ #include <southbridge/intel/bd82x6x/acpi/pch.asl></span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span>diff --git a/src/mainboard/asus/p8h61-m_lx/gma-mainboard.ads b/src/mainboard/asus/p8h61-m_lx/gma-mainboard.ads</span><br><span>new file mode 100644</span><br><span>index 0000000..652fa3f</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/asus/p8h61-m_lx/gma-mainboard.ads</span><br><span>@@ -0,0 +1,29 @@</span><br><span style="color: hsl(120, 100%, 40%);">+--</span><br><span style="color: hsl(120, 100%, 40%);">+-- This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+--</span><br><span style="color: hsl(120, 100%, 40%);">+-- Copyright (C) 2018 Tristan Corrick <tristan@corrick.kiwi></span><br><span style="color: hsl(120, 100%, 40%);">+--</span><br><span style="color: hsl(120, 100%, 40%);">+-- This program is free software: you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+-- it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+-- the Free Software Foundation, either version 2 of the License, or</span><br><span style="color: hsl(120, 100%, 40%);">+-- (at your option) any later version.</span><br><span style="color: hsl(120, 100%, 40%);">+--</span><br><span style="color: hsl(120, 100%, 40%);">+-- This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+-- but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+-- GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+--</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+with HW.GFX.GMA;</span><br><span style="color: hsl(120, 100%, 40%);">+with HW.GFX.GMA.Display_Probing;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+use HW.GFX.GMA;</span><br><span style="color: hsl(120, 100%, 40%);">+use HW.GFX.GMA.Display_Probing;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+private package GMA.Mainboard is</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ ports : constant Port_List :=</span><br><span style="color: hsl(120, 100%, 40%);">+ (Analog,</span><br><span style="color: hsl(120, 100%, 40%);">+ others => Disabled);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+end GMA.Mainboard;</span><br><span>diff --git a/src/mainboard/asus/p8h61-m_lx/gpio.c b/src/mainboard/asus/p8h61-m_lx/gpio.c</span><br><span>new file mode 100644</span><br><span>index 0000000..2a66322</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/asus/p8h61-m_lx/gpio.c</span><br><span>@@ -0,0 +1,140 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2018 Tristan Corrick <tristan@corrick.kiwi></span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software: you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation, either version 2 of the License, or</span><br><span style="color: hsl(120, 100%, 40%);">+ * (at your option) any later version.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <southbridge/intel/common/gpio.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static const struct pch_gpio_set1 pch_gpio_set1_mode = {</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio0 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio1 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio6 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio7 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio8 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio12 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio13 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio15 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio16 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio17 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio24 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio27 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio28 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio29 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio31 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static const struct pch_gpio_set1 pch_gpio_set1_direction = {</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio0 = GPIO_DIR_OUTPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio1 = GPIO_DIR_INPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio6 = GPIO_DIR_INPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio7 = GPIO_DIR_INPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio8 = GPIO_DIR_INPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio12 = GPIO_DIR_INPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio13 = GPIO_DIR_INPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio15 = GPIO_DIR_OUTPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio16 = GPIO_DIR_INPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio17 = GPIO_DIR_INPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio24 = GPIO_DIR_OUTPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio27 = GPIO_DIR_INPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio28 = GPIO_DIR_OUTPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio29 = GPIO_DIR_INPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio31 = GPIO_DIR_OUTPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static const struct pch_gpio_set1 pch_gpio_set1_level = {</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio0 = GPIO_LEVEL_LOW,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio15 = GPIO_LEVEL_LOW,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio24 = GPIO_LEVEL_LOW,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio28 = GPIO_LEVEL_LOW,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio31 = GPIO_LEVEL_LOW,</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static const struct pch_gpio_set1 pch_gpio_set1_reset = {</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static const struct pch_gpio_set1 pch_gpio_set1_invert = {</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio1 = GPIO_INVERT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio6 = GPIO_INVERT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio13 = GPIO_INVERT,</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static const struct pch_gpio_set1 pch_gpio_set1_blink = {</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static const struct pch_gpio_set2 pch_gpio_set2_mode = {</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio32 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio33 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio34 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio46 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio49 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio57 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static const struct pch_gpio_set2 pch_gpio_set2_direction = {</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio32 = GPIO_DIR_OUTPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio33 = GPIO_DIR_OUTPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio34 = GPIO_DIR_INPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio46 = GPIO_DIR_INPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio49 = GPIO_DIR_INPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio57 = GPIO_DIR_INPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static const struct pch_gpio_set2 pch_gpio_set2_level = {</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio32 = GPIO_LEVEL_HIGH,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio33 = GPIO_LEVEL_HIGH,</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static const struct pch_gpio_set2 pch_gpio_set2_reset = {</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static const struct pch_gpio_set3 pch_gpio_set3_mode = {</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio68 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio69 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio72 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static const struct pch_gpio_set3 pch_gpio_set3_direction = {</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio68 = GPIO_DIR_INPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio69 = GPIO_DIR_INPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio72 = GPIO_DIR_INPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static const struct pch_gpio_set3 pch_gpio_set3_level = {</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static const struct pch_gpio_set3 pch_gpio_set3_reset = {</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+const struct pch_gpio_map mainboard_gpio_map = {</span><br><span style="color: hsl(120, 100%, 40%);">+ .set1 = {</span><br><span style="color: hsl(120, 100%, 40%);">+ .mode = &pch_gpio_set1_mode,</span><br><span style="color: hsl(120, 100%, 40%);">+ .direction = &pch_gpio_set1_direction,</span><br><span style="color: hsl(120, 100%, 40%);">+ .level = &pch_gpio_set1_level,</span><br><span style="color: hsl(120, 100%, 40%);">+ .blink = &pch_gpio_set1_blink,</span><br><span style="color: hsl(120, 100%, 40%);">+ .invert = &pch_gpio_set1_invert,</span><br><span style="color: hsl(120, 100%, 40%);">+ .reset = &pch_gpio_set1_reset,</span><br><span style="color: hsl(120, 100%, 40%);">+ },</span><br><span style="color: hsl(120, 100%, 40%);">+ .set2 = {</span><br><span style="color: hsl(120, 100%, 40%);">+ .mode = &pch_gpio_set2_mode,</span><br><span style="color: hsl(120, 100%, 40%);">+ .direction = &pch_gpio_set2_direction,</span><br><span style="color: hsl(120, 100%, 40%);">+ .level = &pch_gpio_set2_level,</span><br><span style="color: hsl(120, 100%, 40%);">+ .reset = &pch_gpio_set2_reset,</span><br><span style="color: hsl(120, 100%, 40%);">+ },</span><br><span style="color: hsl(120, 100%, 40%);">+ .set3 = {</span><br><span style="color: hsl(120, 100%, 40%);">+ .mode = &pch_gpio_set3_mode,</span><br><span style="color: hsl(120, 100%, 40%);">+ .direction = &pch_gpio_set3_direction,</span><br><span style="color: hsl(120, 100%, 40%);">+ .level = &pch_gpio_set3_level,</span><br><span style="color: hsl(120, 100%, 40%);">+ .reset = &pch_gpio_set3_reset,</span><br><span style="color: hsl(120, 100%, 40%);">+ },</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span>diff --git a/src/mainboard/asus/p8h61-m_lx/hda_verb.c b/src/mainboard/asus/p8h61-m_lx/hda_verb.c</span><br><span>new file mode 100644</span><br><span>index 0000000..fb56759</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/asus/p8h61-m_lx/hda_verb.c</span><br><span>@@ -0,0 +1,43 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2018 Tristan Corrick <tristan@corrick.kiwi></span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software: you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation, either version 2 of the License, or</span><br><span style="color: hsl(120, 100%, 40%);">+ * (at your option) any later version.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <stdint.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <device/azalia_device.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+const u32 cim_verb_data[] = {</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x10ec0887, /* Realtek ALC887-VD */</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x10438445, /* Subsystem ID */</span><br><span style="color: hsl(120, 100%, 40%);">+ 15, /* Number of entries */</span><br><span style="color: hsl(120, 100%, 40%);">+ AZALIA_SUBVENDOR(0x0, 0x10438445),</span><br><span style="color: hsl(120, 100%, 40%);">+ AZALIA_PIN_CFG(0x0, 0x11, 0x99430130),</span><br><span style="color: hsl(120, 100%, 40%);">+ AZALIA_PIN_CFG(0x0, 0x12, 0x411111f0),</span><br><span style="color: hsl(120, 100%, 40%);">+ AZALIA_PIN_CFG(0x0, 0x14, 0x01014010),</span><br><span style="color: hsl(120, 100%, 40%);">+ AZALIA_PIN_CFG(0x0, 0x15, 0x411111f0),</span><br><span style="color: hsl(120, 100%, 40%);">+ AZALIA_PIN_CFG(0x0, 0x16, 0x411111f0),</span><br><span style="color: hsl(120, 100%, 40%);">+ AZALIA_PIN_CFG(0x0, 0x17, 0x411111f0),</span><br><span style="color: hsl(120, 100%, 40%);">+ AZALIA_PIN_CFG(0x0, 0x18, 0x01a19840),</span><br><span style="color: hsl(120, 100%, 40%);">+ AZALIA_PIN_CFG(0x0, 0x19, 0x02a19c50),</span><br><span style="color: hsl(120, 100%, 40%);">+ AZALIA_PIN_CFG(0x0, 0x1a, 0x0181304f),</span><br><span style="color: hsl(120, 100%, 40%);">+ AZALIA_PIN_CFG(0x0, 0x1b, 0x02214c20),</span><br><span style="color: hsl(120, 100%, 40%);">+ AZALIA_PIN_CFG(0x0, 0x1c, 0x411111f0),</span><br><span style="color: hsl(120, 100%, 40%);">+ AZALIA_PIN_CFG(0x0, 0x1d, 0x4004c601),</span><br><span style="color: hsl(120, 100%, 40%);">+ AZALIA_PIN_CFG(0x0, 0x1e, 0x411111f0),</span><br><span style="color: hsl(120, 100%, 40%);">+ AZALIA_PIN_CFG(0x0, 0x1f, 0x411111f0),</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+const u32 pc_beep_verbs[] = {};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+AZALIA_ARRAY_SIZES;</span><br><span>diff --git a/src/mainboard/asus/p8h61-m_lx/mainboard.c b/src/mainboard/asus/p8h61-m_lx/mainboard.c</span><br><span>new file mode 100644</span><br><span>index 0000000..54176c4</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/asus/p8h61-m_lx/mainboard.c</span><br><span>@@ -0,0 +1,29 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2018 Tristan Corrick <tristan@corrick.kiwi></span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software: you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation, either version 2 of the License, or</span><br><span style="color: hsl(120, 100%, 40%);">+ * (at your option) any later version.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <device/device.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <drivers/intel/gma/int15.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static void mainboard_enable(struct device *dev)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_NONE,</span><br><span style="color: hsl(120, 100%, 40%);">+ GMA_INT15_PANEL_FIT_DEFAULT,</span><br><span style="color: hsl(120, 100%, 40%);">+ GMA_INT15_BOOT_DISPLAY_DEFAULT, 0);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+struct chip_operations mainboard_ops = {</span><br><span style="color: hsl(120, 100%, 40%);">+ .enable_dev = mainboard_enable,</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span>diff --git a/src/mainboard/asus/p8h61-m_lx/romstage.c b/src/mainboard/asus/p8h61-m_lx/romstage.c</span><br><span>new file mode 100644</span><br><span>index 0000000..76fc8aa</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/asus/p8h61-m_lx/romstage.c</span><br><span>@@ -0,0 +1,68 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2018 Tristan Corrick <tristan@corrick.kiwi></span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software: you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation, either version 2 of the License, or</span><br><span style="color: hsl(120, 100%, 40%);">+ * (at your option) any later version.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <arch/io.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <device/pci_ops.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <device/dram/ddr3.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <northbridge/intel/sandybridge/raminit_native.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <northbridge/intel/sandybridge/sandybridge.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <southbridge/intel/bd82x6x/pch.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <superio/nuvoton/common/nuvoton.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <superio/nuvoton/nct6776/nct6776.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define SERIAL_DEV PNP_DEV(0x2e, NCT6776_SP1)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+const struct southbridge_usb_port mainboard_usb_ports[] = {</span><br><span style="color: hsl(120, 100%, 40%);">+ { 1, 0, 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ { 1, 0, 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ { 1, 0, 1 },</span><br><span style="color: hsl(120, 100%, 40%);">+ { 1, 0, 1 },</span><br><span style="color: hsl(120, 100%, 40%);">+ { 1, 0, 2 },</span><br><span style="color: hsl(120, 100%, 40%);">+ { 1, 0, 2 },</span><br><span style="color: hsl(120, 100%, 40%);">+ { 1, 0, 3 },</span><br><span style="color: hsl(120, 100%, 40%);">+ { 1, 0, 3 },</span><br><span style="color: hsl(120, 100%, 40%);">+ { 1, 0, 4 },</span><br><span style="color: hsl(120, 100%, 40%);">+ { 1, 0, 4 },</span><br><span style="color: hsl(120, 100%, 40%);">+ { 1, 0, 5 },</span><br><span style="color: hsl(120, 100%, 40%);">+ { 1, 0, 5 },</span><br><span style="color: hsl(120, 100%, 40%);">+ { 1, 0, 6 },</span><br><span style="color: hsl(120, 100%, 40%);">+ { 1, 0, 6 },</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+void pch_enable_lpc(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_or_config16(PCH_LPC_DEV, LPC_EN,</span><br><span style="color: hsl(120, 100%, 40%);">+ CNF1_LPC_EN | KBC_LPC_EN | LPT_LPC_EN | COMA_LPC_EN);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+void mainboard_rcba_config(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+void mainboard_early_init(int s3resume)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+void mainboard_config_superio(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+void mainboard_get_spd(spd_raw_data *spd, bool id_only)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ read_spd(&spd[0], 0x50, id_only);</span><br><span style="color: hsl(120, 100%, 40%);">+ read_spd(&spd[2], 0x52, id_only);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/27798">change 27798</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/27798"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I2a0579f486d3a44de2dd927fa1e76b90c3b48f62 </div>
<div style="display:none"> Gerrit-Change-Number: 27798 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Tristan Corrick <tristan@corrick.kiwi> </div>