<p>Matt DeVillier has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/27787">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">mb/google/auron,cyan: Remove interrupt from devicetree LPC TPM chip driver<br><br>These boards require polling vs interrupts, so remove the IRQ definition to<br>prevent it being added to the SSDT device entry.<br><br>Test: Boot Linux on various auron and cyan variants, verify no error for<br>'TPM interrupt not working' present in kernel boot log.<br><br>Change-Id: Ia1139389f075934d41e823ce5190011c90c7cc88<br>Signed-off-by: Matt DeVillier <matt.devillier@gmail.com><br>---<br>M src/mainboard/google/auron/variants/auron_paine/devicetree.cb<br>M src/mainboard/google/auron/variants/auron_yuna/devicetree.cb<br>M src/mainboard/google/auron/variants/gandof/devicetree.cb<br>M src/mainboard/google/auron/variants/lulu/devicetree.cb<br>M src/mainboard/google/auron/variants/samus/devicetree.cb<br>M src/mainboard/google/cyan/variants/banon/devicetree.cb<br>M src/mainboard/google/cyan/variants/celes/devicetree.cb<br>M src/mainboard/google/cyan/variants/cyan/devicetree.cb<br>M src/mainboard/google/cyan/variants/edgar/devicetree.cb<br>M src/mainboard/google/cyan/variants/kefka/devicetree.cb<br>M src/mainboard/google/cyan/variants/reks/devicetree.cb<br>M src/mainboard/google/cyan/variants/relm/devicetree.cb<br>M src/mainboard/google/cyan/variants/setzer/devicetree.cb<br>M src/mainboard/google/cyan/variants/terra/devicetree.cb<br>M src/mainboard/google/cyan/variants/ultima/devicetree.cb<br>M src/mainboard/google/cyan/variants/wizpig/devicetree.cb<br>16 files changed, 17 insertions(+), 81 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/27787/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/mainboard/google/auron/variants/auron_paine/devicetree.cb b/src/mainboard/google/auron/variants/auron_paine/devicetree.cb</span><br><span>index 5872cf2..b31d829 100644</span><br><span>--- a/src/mainboard/google/auron/variants/auron_paine/devicetree.cb</span><br><span>+++ b/src/mainboard/google/auron/variants/auron_paine/devicetree.cb</span><br><span>@@ -91,11 +91,7 @@</span><br><span> device pci 1e.0 off end # PCI bridge</span><br><span> device pci 1f.0 on</span><br><span> chip drivers/pc80/tpm</span><br><span style="color: hsl(0, 100%, 40%);">- # Rising edge interrupt</span><br><span style="color: hsl(0, 100%, 40%);">- register "irq_polarity" = "2"</span><br><span style="color: hsl(0, 100%, 40%);">- device pnp 0c31.0 on</span><br><span style="color: hsl(0, 100%, 40%);">- irq 0x70 = 10</span><br><span style="color: hsl(0, 100%, 40%);">- end</span><br><span style="color: hsl(120, 100%, 40%);">+ device pnp 0c31.0 on end</span><br><span> end</span><br><span> chip ec/google/chromeec</span><br><span> device pnp 0c09.0 on end</span><br><span>diff --git a/src/mainboard/google/auron/variants/auron_yuna/devicetree.cb b/src/mainboard/google/auron/variants/auron_yuna/devicetree.cb</span><br><span>index 34051a7..3c00ec9 100644</span><br><span>--- a/src/mainboard/google/auron/variants/auron_yuna/devicetree.cb</span><br><span>+++ b/src/mainboard/google/auron/variants/auron_yuna/devicetree.cb</span><br><span>@@ -91,11 +91,7 @@</span><br><span> device pci 1e.0 off end # PCI bridge</span><br><span> device pci 1f.0 on</span><br><span> chip drivers/pc80/tpm</span><br><span style="color: hsl(0, 100%, 40%);">- # Rising edge interrupt</span><br><span style="color: hsl(0, 100%, 40%);">- register "irq_polarity" = "2"</span><br><span style="color: hsl(0, 100%, 40%);">- device pnp 0c31.0 on</span><br><span style="color: hsl(0, 100%, 40%);">- irq 0x70 = 10</span><br><span style="color: hsl(0, 100%, 40%);">- end</span><br><span style="color: hsl(120, 100%, 40%);">+ device pnp 0c31.0 on end</span><br><span> end</span><br><span> chip ec/google/chromeec</span><br><span> device pnp 0c09.0 on end</span><br><span>diff --git a/src/mainboard/google/auron/variants/gandof/devicetree.cb b/src/mainboard/google/auron/variants/gandof/devicetree.cb</span><br><span>index 06ff8ae..118e646 100644</span><br><span>--- a/src/mainboard/google/auron/variants/gandof/devicetree.cb</span><br><span>+++ b/src/mainboard/google/auron/variants/gandof/devicetree.cb</span><br><span>@@ -90,12 +90,8 @@</span><br><span> device pci 1d.0 on end # USB2 EHCI</span><br><span> device pci 1e.0 off end # PCI bridge</span><br><span> device pci 1f.0 on</span><br><span style="color: hsl(0, 100%, 40%);">- chip drivers/pc80/tpm</span><br><span style="color: hsl(0, 100%, 40%);">- # Rising edge interrupt</span><br><span style="color: hsl(0, 100%, 40%);">- register "irq_polarity" = "2"</span><br><span style="color: hsl(0, 100%, 40%);">- device pnp 0c31.0 on</span><br><span style="color: hsl(0, 100%, 40%);">- irq 0x70 = 10</span><br><span style="color: hsl(0, 100%, 40%);">- end</span><br><span style="color: hsl(120, 100%, 40%);">+ chip drivers/pc80/tpm</span><br><span style="color: hsl(120, 100%, 40%);">+ device pnp 0c31.0 on end</span><br><span> end</span><br><span> chip ec/google/chromeec</span><br><span> device pnp 0c09.0 on end</span><br><span>diff --git a/src/mainboard/google/auron/variants/lulu/devicetree.cb b/src/mainboard/google/auron/variants/lulu/devicetree.cb</span><br><span>index 84fc8c4..622ea34 100644</span><br><span>--- a/src/mainboard/google/auron/variants/lulu/devicetree.cb</span><br><span>+++ b/src/mainboard/google/auron/variants/lulu/devicetree.cb</span><br><span>@@ -92,11 +92,7 @@</span><br><span> device pci 1e.0 off end # PCI bridge</span><br><span> device pci 1f.0 on</span><br><span> chip drivers/pc80/tpm</span><br><span style="color: hsl(0, 100%, 40%);">- # Rising edge interrupt</span><br><span style="color: hsl(0, 100%, 40%);">- register "irq_polarity" = "2"</span><br><span style="color: hsl(0, 100%, 40%);">- device pnp 0c31.0 on</span><br><span style="color: hsl(0, 100%, 40%);">- irq 0x70 = 10</span><br><span style="color: hsl(0, 100%, 40%);">- end</span><br><span style="color: hsl(120, 100%, 40%);">+ device pnp 0c31.0 on end</span><br><span> end</span><br><span> chip ec/google/chromeec</span><br><span> device pnp 0c09.0 on end</span><br><span>diff --git a/src/mainboard/google/auron/variants/samus/devicetree.cb b/src/mainboard/google/auron/variants/samus/devicetree.cb</span><br><span>index d12762d..a6c2fea 100644</span><br><span>--- a/src/mainboard/google/auron/variants/samus/devicetree.cb</span><br><span>+++ b/src/mainboard/google/auron/variants/samus/devicetree.cb</span><br><span>@@ -95,11 +95,7 @@</span><br><span> device pci 1e.0 off end # PCI bridge</span><br><span> device pci 1f.0 on</span><br><span> chip drivers/pc80/tpm</span><br><span style="color: hsl(0, 100%, 40%);">- # Rising edge interrupt</span><br><span style="color: hsl(0, 100%, 40%);">- register "irq_polarity" = "2"</span><br><span style="color: hsl(0, 100%, 40%);">- device pnp 0c31.0 on</span><br><span style="color: hsl(0, 100%, 40%);">- irq 0x70 = 10</span><br><span style="color: hsl(0, 100%, 40%);">- end</span><br><span style="color: hsl(120, 100%, 40%);">+ device pnp 0c31.0 on end</span><br><span> end</span><br><span> chip ec/google/chromeec</span><br><span> device pnp 0c09.0 on end</span><br><span>diff --git a/src/mainboard/google/cyan/variants/banon/devicetree.cb b/src/mainboard/google/cyan/variants/banon/devicetree.cb</span><br><span>index 8d16d04..60076c2 100644</span><br><span>--- a/src/mainboard/google/cyan/variants/banon/devicetree.cb</span><br><span>+++ b/src/mainboard/google/cyan/variants/banon/devicetree.cb</span><br><span>@@ -135,11 +135,7 @@</span><br><span> device pci 1e.7 off end # 8086 22ac - SPI 3</span><br><span> device pci 1f.0 on # 8086 229c - LPC bridge</span><br><span> chip drivers/pc80/tpm</span><br><span style="color: hsl(0, 100%, 40%);">- # Rising edge interrupt</span><br><span style="color: hsl(0, 100%, 40%);">- register "irq_polarity" = "2"</span><br><span style="color: hsl(0, 100%, 40%);">- device pnp 0c31.0 on</span><br><span style="color: hsl(0, 100%, 40%);">- irq 0x70 = 10</span><br><span style="color: hsl(0, 100%, 40%);">- end</span><br><span style="color: hsl(120, 100%, 40%);">+ device pnp 0c31.0 on end</span><br><span> end</span><br><span> chip ec/google/chromeec</span><br><span> device pnp 0c09.0 on end</span><br><span>diff --git a/src/mainboard/google/cyan/variants/celes/devicetree.cb b/src/mainboard/google/cyan/variants/celes/devicetree.cb</span><br><span>index 84edd74..2e708af 100644</span><br><span>--- a/src/mainboard/google/cyan/variants/celes/devicetree.cb</span><br><span>+++ b/src/mainboard/google/cyan/variants/celes/devicetree.cb</span><br><span>@@ -135,11 +135,7 @@</span><br><span> device pci 1e.7 off end # 8086 22ac - SPI 3</span><br><span> device pci 1f.0 on # 8086 229c - LPC bridge</span><br><span> chip drivers/pc80/tpm</span><br><span style="color: hsl(0, 100%, 40%);">- # Rising edge interrupt</span><br><span style="color: hsl(0, 100%, 40%);">- register "irq_polarity" = "2"</span><br><span style="color: hsl(0, 100%, 40%);">- device pnp 0c31.0 on</span><br><span style="color: hsl(0, 100%, 40%);">- irq 0x70 = 10</span><br><span style="color: hsl(0, 100%, 40%);">- end</span><br><span style="color: hsl(120, 100%, 40%);">+ device pnp 0c31.0 on end</span><br><span> end</span><br><span> chip ec/google/chromeec</span><br><span> device pnp 0c09.0 on end</span><br><span>diff --git a/src/mainboard/google/cyan/variants/cyan/devicetree.cb b/src/mainboard/google/cyan/variants/cyan/devicetree.cb</span><br><span>index 0454650..dd9b05e 100644</span><br><span>--- a/src/mainboard/google/cyan/variants/cyan/devicetree.cb</span><br><span>+++ b/src/mainboard/google/cyan/variants/cyan/devicetree.cb</span><br><span>@@ -128,11 +128,7 @@</span><br><span> device pci 1e.7 off end # 8086 22ac - SPI 3</span><br><span> device pci 1f.0 on # 8086 229c - LPC bridge</span><br><span> chip drivers/pc80/tpm</span><br><span style="color: hsl(0, 100%, 40%);">- # Rising edge interrupt</span><br><span style="color: hsl(0, 100%, 40%);">- register "irq_polarity" = "2"</span><br><span style="color: hsl(0, 100%, 40%);">- device pnp 0c31.0 on</span><br><span style="color: hsl(0, 100%, 40%);">- irq 0x70 = 10</span><br><span style="color: hsl(0, 100%, 40%);">- end</span><br><span style="color: hsl(120, 100%, 40%);">+ device pnp 0c31.0 on end</span><br><span> end</span><br><span> chip ec/google/chromeec</span><br><span> device pnp 0c09.0 on end</span><br><span>diff --git a/src/mainboard/google/cyan/variants/edgar/devicetree.cb b/src/mainboard/google/cyan/variants/edgar/devicetree.cb</span><br><span>index 2033f9e..0ba221e 100644</span><br><span>--- a/src/mainboard/google/cyan/variants/edgar/devicetree.cb</span><br><span>+++ b/src/mainboard/google/cyan/variants/edgar/devicetree.cb</span><br><span>@@ -129,11 +129,7 @@</span><br><span> device pci 1e.7 off end # 8086 22ac - SPI 3</span><br><span> device pci 1f.0 on # 8086 229c - LPC bridge</span><br><span> chip drivers/pc80/tpm</span><br><span style="color: hsl(0, 100%, 40%);">- # Rising edge interrupt</span><br><span style="color: hsl(0, 100%, 40%);">- register "irq_polarity" = "2"</span><br><span style="color: hsl(0, 100%, 40%);">- device pnp 0c31.0 on</span><br><span style="color: hsl(0, 100%, 40%);">- irq 0x70 = 10</span><br><span style="color: hsl(0, 100%, 40%);">- end</span><br><span style="color: hsl(120, 100%, 40%);">+ device pnp 0c31.0 on end</span><br><span> end</span><br><span> chip ec/google/chromeec</span><br><span> device pnp 0c09.0 on end</span><br><span>diff --git a/src/mainboard/google/cyan/variants/kefka/devicetree.cb b/src/mainboard/google/cyan/variants/kefka/devicetree.cb</span><br><span>index e6542cb..1ce056f 100644</span><br><span>--- a/src/mainboard/google/cyan/variants/kefka/devicetree.cb</span><br><span>+++ b/src/mainboard/google/cyan/variants/kefka/devicetree.cb</span><br><span>@@ -142,11 +142,7 @@</span><br><span> device pci 1e.7 off end # 8086 22ac - SPI 3</span><br><span> device pci 1f.0 on # 8086 229c - LPC bridge</span><br><span> chip drivers/pc80/tpm</span><br><span style="color: hsl(0, 100%, 40%);">- # Rising edge interrupt</span><br><span style="color: hsl(0, 100%, 40%);">- register "irq_polarity" = "2"</span><br><span style="color: hsl(0, 100%, 40%);">- device pnp 0c31.0 on</span><br><span style="color: hsl(0, 100%, 40%);">- irq 0x70 = 10</span><br><span style="color: hsl(0, 100%, 40%);">- end</span><br><span style="color: hsl(120, 100%, 40%);">+ device pnp 0c31.0 on end</span><br><span> end</span><br><span> chip ec/google/chromeec</span><br><span> device pnp 0c09.0 on end</span><br><span>diff --git a/src/mainboard/google/cyan/variants/reks/devicetree.cb b/src/mainboard/google/cyan/variants/reks/devicetree.cb</span><br><span>index 53239b5..302f2da 100644</span><br><span>--- a/src/mainboard/google/cyan/variants/reks/devicetree.cb</span><br><span>+++ b/src/mainboard/google/cyan/variants/reks/devicetree.cb</span><br><span>@@ -126,11 +126,7 @@</span><br><span> device pci 1e.7 off end # 8086 22ac - SPI 3</span><br><span> device pci 1f.0 on # 8086 229c - LPC bridge</span><br><span> chip drivers/pc80/tpm</span><br><span style="color: hsl(0, 100%, 40%);">- # Rising edge interrupt</span><br><span style="color: hsl(0, 100%, 40%);">- register "irq_polarity" = "2"</span><br><span style="color: hsl(0, 100%, 40%);">- device pnp 0c31.0 on</span><br><span style="color: hsl(0, 100%, 40%);">- irq 0x70 = 10</span><br><span style="color: hsl(0, 100%, 40%);">- end</span><br><span style="color: hsl(120, 100%, 40%);">+ device pnp 0c31.0 on end</span><br><span> end</span><br><span> chip ec/google/chromeec</span><br><span> device pnp 0c09.0 on end</span><br><span>diff --git a/src/mainboard/google/cyan/variants/relm/devicetree.cb b/src/mainboard/google/cyan/variants/relm/devicetree.cb</span><br><span>index eb48ace..65e662c 100644</span><br><span>--- a/src/mainboard/google/cyan/variants/relm/devicetree.cb</span><br><span>+++ b/src/mainboard/google/cyan/variants/relm/devicetree.cb</span><br><span>@@ -142,11 +142,7 @@</span><br><span> device pci 1e.7 off end # 8086 22ac - SPI 3</span><br><span> device pci 1f.0 on # 8086 229c - LPC bridge</span><br><span> chip drivers/pc80/tpm</span><br><span style="color: hsl(0, 100%, 40%);">- # Rising edge interrupt</span><br><span style="color: hsl(0, 100%, 40%);">- register "irq_polarity" = "2"</span><br><span style="color: hsl(0, 100%, 40%);">- device pnp 0c31.0 on</span><br><span style="color: hsl(0, 100%, 40%);">- irq 0x70 = 10</span><br><span style="color: hsl(0, 100%, 40%);">- end</span><br><span style="color: hsl(120, 100%, 40%);">+ device pnp 0c31.0 on end</span><br><span> end</span><br><span> chip ec/google/chromeec</span><br><span> device pnp 0c09.0 on end</span><br><span>diff --git a/src/mainboard/google/cyan/variants/setzer/devicetree.cb b/src/mainboard/google/cyan/variants/setzer/devicetree.cb</span><br><span>index b8480a3..f0b2c6f 100644</span><br><span>--- a/src/mainboard/google/cyan/variants/setzer/devicetree.cb</span><br><span>+++ b/src/mainboard/google/cyan/variants/setzer/devicetree.cb</span><br><span>@@ -135,11 +135,7 @@</span><br><span> device pci 1e.7 off end # 8086 22ac - SPI 3</span><br><span> device pci 1f.0 on # 8086 229c - LPC bridge</span><br><span> chip drivers/pc80/tpm</span><br><span style="color: hsl(0, 100%, 40%);">- # Rising edge interrupt</span><br><span style="color: hsl(0, 100%, 40%);">- register "irq_polarity" = "2"</span><br><span style="color: hsl(0, 100%, 40%);">- device pnp 0c31.0 on</span><br><span style="color: hsl(0, 100%, 40%);">- irq 0x70 = 10</span><br><span style="color: hsl(0, 100%, 40%);">- end</span><br><span style="color: hsl(120, 100%, 40%);">+ device pnp 0c31.0 on end</span><br><span> end</span><br><span> chip ec/google/chromeec</span><br><span> device pnp 0c09.0 on end</span><br><span>diff --git a/src/mainboard/google/cyan/variants/terra/devicetree.cb b/src/mainboard/google/cyan/variants/terra/devicetree.cb</span><br><span>index 2feb1a3..d7d0f1f 100644</span><br><span>--- a/src/mainboard/google/cyan/variants/terra/devicetree.cb</span><br><span>+++ b/src/mainboard/google/cyan/variants/terra/devicetree.cb</span><br><span>@@ -135,11 +135,7 @@</span><br><span> device pci 1e.7 off end # 8086 22ac - SPI 3</span><br><span> device pci 1f.0 on # 8086 229c - LPC bridge</span><br><span> chip drivers/pc80/tpm</span><br><span style="color: hsl(0, 100%, 40%);">- # Rising edge interrupt</span><br><span style="color: hsl(0, 100%, 40%);">- register "irq_polarity" = "2"</span><br><span style="color: hsl(0, 100%, 40%);">- device pnp 0c31.0 on</span><br><span style="color: hsl(0, 100%, 40%);">- irq 0x70 = 10</span><br><span style="color: hsl(0, 100%, 40%);">- end</span><br><span style="color: hsl(120, 100%, 40%);">+ device pnp 0c31.0 on end</span><br><span> end</span><br><span> chip ec/google/chromeec</span><br><span> device pnp 0c09.0 on end</span><br><span>diff --git a/src/mainboard/google/cyan/variants/ultima/devicetree.cb b/src/mainboard/google/cyan/variants/ultima/devicetree.cb</span><br><span>index 287dd02..d4ed38b 100644</span><br><span>--- a/src/mainboard/google/cyan/variants/ultima/devicetree.cb</span><br><span>+++ b/src/mainboard/google/cyan/variants/ultima/devicetree.cb</span><br><span>@@ -129,11 +129,7 @@</span><br><span> device pci 1e.7 off end # 8086 22ac - SPI 3</span><br><span> device pci 1f.0 on # 8086 229c - LPC bridge</span><br><span> chip drivers/pc80/tpm</span><br><span style="color: hsl(0, 100%, 40%);">- # Rising edge interrupt</span><br><span style="color: hsl(0, 100%, 40%);">- register "irq_polarity" = "2"</span><br><span style="color: hsl(0, 100%, 40%);">- device pnp 0c31.0 on</span><br><span style="color: hsl(0, 100%, 40%);">- irq 0x70 = 10</span><br><span style="color: hsl(0, 100%, 40%);">- end</span><br><span style="color: hsl(120, 100%, 40%);">+ device pnp 0c31.0 on end</span><br><span> end</span><br><span> chip ec/google/chromeec</span><br><span> device pnp 0c09.0 on end</span><br><span>diff --git a/src/mainboard/google/cyan/variants/wizpig/devicetree.cb b/src/mainboard/google/cyan/variants/wizpig/devicetree.cb</span><br><span>index 3fb3053..7be7a0f 100644</span><br><span>--- a/src/mainboard/google/cyan/variants/wizpig/devicetree.cb</span><br><span>+++ b/src/mainboard/google/cyan/variants/wizpig/devicetree.cb</span><br><span>@@ -136,11 +136,7 @@</span><br><span> device pci 1e.7 off end # 8086 22ac - SPI 3</span><br><span> device pci 1f.0 on # 8086 229c - LPC bridge</span><br><span> chip drivers/pc80/tpm</span><br><span style="color: hsl(0, 100%, 40%);">- # Rising edge interrupt</span><br><span style="color: hsl(0, 100%, 40%);">- register "irq_polarity" = "2"</span><br><span style="color: hsl(0, 100%, 40%);">- device pnp 0c31.0 on</span><br><span style="color: hsl(0, 100%, 40%);">- irq 0x70 = 10</span><br><span style="color: hsl(0, 100%, 40%);">- end</span><br><span style="color: hsl(120, 100%, 40%);">+ device pnp 0c31.0 on end</span><br><span> end</span><br><span> chip ec/google/chromeec</span><br><span> device pnp 0c09.0 on end</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/27787">change 27787</a>. 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<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: Ia1139389f075934d41e823ce5190011c90c7cc88 </div>
<div style="display:none"> Gerrit-Change-Number: 27787 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Matt DeVillier <matt.devillier@gmail.com> </div>