<p>Felix Held has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/27754">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">sandybridge/raminit_common: use MCHBAR AND/OR macros in remaining places<br><br>Change-Id: I1c81eb7c8ed0b819bb76196208cc1269180aca55<br>Signed-off-by: Felix Held <felix-coreboot@felixheld.de><br>---<br>M src/northbridge/intel/sandybridge/raminit_common.c<br>1 file changed, 21 insertions(+), 41 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/27754/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c</span><br><span>index 2e5fe70..d806066 100644</span><br><span>--- a/src/northbridge/intel/sandybridge/raminit_common.c</span><br><span>+++ b/src/northbridge/intel/sandybridge/raminit_common.c</span><br><span>@@ -195,7 +195,7 @@</span><br><span> static void dram_odt_stretch(ramctr_timing *ctrl, int channel)</span><br><span> {</span><br><span> struct cpuid_result cpures;</span><br><span style="color: hsl(0, 100%, 40%);">- u32 reg, addr, cpu, stretch;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 cpu, stretch;</span><br><span> </span><br><span> stretch = ctrl->ref_card_offset[channel];</span><br><span> /* ODT stretch: Delay ODT signal by stretch value.</span><br><span>@@ -205,19 +205,13 @@</span><br><span> if (IS_SANDY_CPU(cpu) && IS_SANDY_CPU_C(cpu)) {</span><br><span> if (stretch == 2)</span><br><span> stretch = 3;</span><br><span style="color: hsl(0, 100%, 40%);">- addr = 0x400 * channel + 0x401c;</span><br><span style="color: hsl(0, 100%, 40%);">- reg = MCHBAR32(addr) & 0xffffc3ff;</span><br><span style="color: hsl(0, 100%, 40%);">- reg |= (stretch << 12);</span><br><span style="color: hsl(0, 100%, 40%);">- reg |= (stretch << 10);</span><br><span style="color: hsl(0, 100%, 40%);">- MCHBAR32(addr) = reg;</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32_AND_OR(0x401c + 0x400 * channel, 0xffffc3ff,</span><br><span style="color: hsl(120, 100%, 40%);">+ (stretch << 12) | (stretch << 10));</span><br><span> printram("OTHP Workaround [%x] = %x\n", addr, reg);</span><br><span> } else {</span><br><span> // OTHP</span><br><span style="color: hsl(0, 100%, 40%);">- addr = 0x400 * channel + 0x400c;</span><br><span style="color: hsl(0, 100%, 40%);">- reg = MCHBAR32(addr) & 0xfff0ffff;</span><br><span style="color: hsl(0, 100%, 40%);">- reg |= (stretch << 16);</span><br><span style="color: hsl(0, 100%, 40%);">- reg |= (stretch << 18);</span><br><span style="color: hsl(0, 100%, 40%);">- MCHBAR32(addr) = reg;</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32_AND_OR(0x400c + 0x400 * channel, 0xfff0ffff,</span><br><span style="color: hsl(120, 100%, 40%);">+ (stretch << 16) | (stretch << 18));</span><br><span> printram("OTHP [%x] = %x\n", addr, reg);</span><br><span> }</span><br><span> }</span><br><span>@@ -262,7 +256,7 @@</span><br><span> </span><br><span> MCHBAR32(0x400 * channel + 0x4014) = 0;</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- MCHBAR32(addr) |= 0x00020000;</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32_OR(addr, 0x00020000);</span><br><span> </span><br><span> dram_odt_stretch(ctrl, channel);</span><br><span> </span><br><span>@@ -280,7 +274,7 @@</span><br><span> printram("REFI [%x] = %x\n", 0x400 * channel + 0x4298, reg);</span><br><span> MCHBAR32(0x400 * channel + 0x4298) = reg;</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- MCHBAR32(0x400 * channel + 0x4294) |= 0xff;</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32_OR(0x400 * channel + 0x4294, 0xff);</span><br><span> </span><br><span> // SRFTP</span><br><span> reg = 0;</span><br><span>@@ -656,7 +650,7 @@</span><br><span> </span><br><span> void dram_jedecreset(ramctr_timing * ctrl)</span><br><span> {</span><br><span style="color: hsl(0, 100%, 40%);">- u32 reg, addr;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 reg;</span><br><span> int channel;</span><br><span> </span><br><span> while (!(MCHBAR32(0x5084) & 0x10000));</span><br><span>@@ -672,37 +666,33 @@</span><br><span> MCHBAR32(0x5030) = reg;</span><br><span> </span><br><span> // Assert dimm reset signal</span><br><span style="color: hsl(0, 100%, 40%);">- reg = MCHBAR32(0x5030);</span><br><span style="color: hsl(0, 100%, 40%);">- reg &= ~0x2;</span><br><span style="color: hsl(0, 100%, 40%);">- MCHBAR32(0x5030) = reg;</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32_AND(0x5030, ~0x2);</span><br><span> </span><br><span> // Wait 200us</span><br><span> udelay(200);</span><br><span> </span><br><span> // Deassert dimm reset signal</span><br><span style="color: hsl(0, 100%, 40%);">- MCHBAR32(0x5030) |= 2;</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32_OR(0x5030, 2);</span><br><span> </span><br><span> // Wait 500us</span><br><span> udelay(500);</span><br><span> </span><br><span> // Enable DCLK</span><br><span style="color: hsl(0, 100%, 40%);">- MCHBAR32(0x5030) |= 4;</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32_OR(0x5030, 4);</span><br><span> </span><br><span> // XXX Wait 20ns</span><br><span> udelay(1);</span><br><span> </span><br><span> FOR_ALL_CHANNELS {</span><br><span> // Set valid rank CKE</span><br><span style="color: hsl(0, 100%, 40%);">- reg = 0;</span><br><span style="color: hsl(0, 100%, 40%);">- reg = (reg & ~0xf) | ctrl->rankmap[channel];</span><br><span style="color: hsl(0, 100%, 40%);">- addr = 0x400 * channel + 0x42a0;</span><br><span style="color: hsl(0, 100%, 40%);">- MCHBAR32(addr) = reg;</span><br><span style="color: hsl(120, 100%, 40%);">+ reg = ctrl->rankmap[channel];</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x42a0 + 0x400 * channel) = reg;</span><br><span> </span><br><span> // Wait 10ns for ranks to settle</span><br><span> //udelay(0.01);</span><br><span> </span><br><span> reg = (reg & ~0xf0) | (ctrl->rankmap[channel] << 4);</span><br><span style="color: hsl(0, 100%, 40%);">- MCHBAR32(addr) = reg;</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x42a0 + 0x400 * channel) = reg;</span><br><span> </span><br><span> // Write reset using a NOP</span><br><span> write_reset(ctrl);</span><br><span>@@ -862,7 +852,6 @@</span><br><span> void dram_mrscommands(ramctr_timing * ctrl)</span><br><span> {</span><br><span> u8 slotrank;</span><br><span style="color: hsl(0, 100%, 40%);">- u32 reg, addr;</span><br><span> int channel;</span><br><span> </span><br><span> FOR_ALL_POPULATED_CHANNELS {</span><br><span>@@ -903,13 +892,10 @@</span><br><span> }</span><br><span> </span><br><span> // Refresh enable</span><br><span style="color: hsl(0, 100%, 40%);">- MCHBAR32(0x5030) |= 8;</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32_OR(0x5030, 8);</span><br><span> </span><br><span> FOR_ALL_POPULATED_CHANNELS {</span><br><span style="color: hsl(0, 100%, 40%);">- addr = 0x400 * channel + 0x4020;</span><br><span style="color: hsl(0, 100%, 40%);">- reg = MCHBAR32(addr);</span><br><span style="color: hsl(0, 100%, 40%);">- reg &= ~0x200000;</span><br><span style="color: hsl(0, 100%, 40%);">- MCHBAR32(addr) = reg;</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32_AND(0x4020 + 0x400 * channel, ~0x200000);</span><br><span> </span><br><span> wait_428c(channel);</span><br><span> </span><br><span>@@ -1478,9 +1464,7 @@</span><br><span> MCHBAR32(0x4230 + 0x400 * channel) =</span><br><span> (max((ctrl->tFAW >> 2) + 1, ctrl->tRRD) << 10)</span><br><span> | 4 | (ctrl->tRCD << 16);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span> MCHBAR32(0x4200 + 0x400 * channel) = (slotrank << 24) | (6 << 16);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span> MCHBAR32(0x4210 + 0x400 * channel) = 0x244;</span><br><span> </span><br><span> /* DRAM command NOP */</span><br><span>@@ -1518,9 +1502,7 @@</span><br><span> MCHBAR32(0x4234 + 0x400 * channel) =</span><br><span> (max(ctrl->tRRD, (ctrl->tFAW >> 2) + 1) << 10)</span><br><span> | 8 | (ctrl->CAS << 16);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span> MCHBAR32(0x4204 + 0x400 * channel) = (slotrank << 24) | 0x60000;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span> MCHBAR32(0x4214 + 0x400 * channel) = 0x244;</span><br><span> </span><br><span> /* DRAM command RD */</span><br><span>@@ -1553,7 +1535,7 @@</span><br><span> /* DRAM command PREA */</span><br><span> MCHBAR32(0x4220 + 0x400 * channel) = 0x1f002;</span><br><span> MCHBAR32(0x4230 + 0x400 * channel) = 0xc01 | (ctrl->tRP << 16);</span><br><span style="color: hsl(0, 100%, 40%);">- MCHBAR32(0x4200 + 0x400 * channel) = (slotrank << 24) | 0x60400;</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x4200 + 0x400 * channel) = (slotrank << 24) | 0x60400;</span><br><span> MCHBAR32(0x4210 + 0x400 * channel) = 0x240;</span><br><span> </span><br><span> // execute command queue</span><br><span>@@ -1725,7 +1707,6 @@</span><br><span> MCHBAR32(0x422c + 0x400 * channel) = 0x1f000;</span><br><span> MCHBAR32(0x423c + 0x400 * channel) =</span><br><span> 0xc01 | (ctrl->tMOD << 16);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span> MCHBAR32(0x420c + 0x400 * channel) =</span><br><span> (slotrank << 24) | 0x360000;</span><br><span> MCHBAR32(0x421c + 0x400 * channel) = 0;</span><br><span>@@ -2095,11 +2076,10 @@</span><br><span> MCHBAR32(0x4230 + 0x400 * channel) =</span><br><span> ((max(ctrl->tRRD, (ctrl->tFAW >> 2) + 1)) << 10)</span><br><span> | 8 | (ctrl->tRCD << 16);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span> MCHBAR32(0x4200 + 0x400 * channel) =</span><br><span> (slotrank << 24) | ctr | 0x60000;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span> MCHBAR32(0x4210 + 0x400 * channel) = 0x244;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> /* DRAM command WR */</span><br><span> MCHBAR32(0x4224 + 0x400 * channel) = 0x1f201;</span><br><span> MCHBAR32(0x4234 + 0x400 * channel) =</span><br><span>@@ -3059,7 +3039,7 @@</span><br><span> </span><br><span> FOR_ALL_POPULATED_CHANNELS {</span><br><span> // Always drive command bus</span><br><span style="color: hsl(0, 100%, 40%);">- MCHBAR32(0x4004 + 0x400 * channel) |= 0x20000000;</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32_OR(0x4004 + 0x400 * channel, 0x20000000);</span><br><span> }</span><br><span> </span><br><span> udelay(1);</span><br><span>@@ -3170,8 +3150,8 @@</span><br><span> FOR_ALL_CHANNELS</span><br><span> MCHBAR32_AND_OR(0x4294 + 0x400 * channel, ~0x30000, 1 << 16);</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- MCHBAR32(0x5030) |= 1;</span><br><span style="color: hsl(0, 100%, 40%);">- MCHBAR32(0x5030) |= 0x80;</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32_OR(0x5030, 1);</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32_OR(0x5030, 0x80);</span><br><span> MCHBAR32(0x5f18) = 0xfa;</span><br><span> </span><br><span> /* Find a populated channel. */</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/27754">change 27754</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/27754"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I1c81eb7c8ed0b819bb76196208cc1269180aca55 </div>
<div style="display:none"> Gerrit-Change-Number: 27754 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Felix Held <felix-coreboot@felixheld.de> </div>