<p>Matt DeVillier has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/27764">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">google/banon: Add support for additional RAM types/configs<br><br>Adapted from chromium commits 831a372 and cc96c27<br>[Banon: board 2nd source DDR memory]<br><br>Add support for hynix/H9CCNNN8GTALAR-NUD and Nanya/NT6CL256T32CM-H1<br><br>Original-Change-Id: Ifd161ba5ade44e71c88655f760ca66668b5c5178<br>Original-Change-Id: I5cba13701ed8e037e21d34ed55162ee56291a842<br>Original-Signed-off-by: T.H. Lin <T.H_Lin@quantatw.com><br>Original-Tested-by: TH Lin <t.h_lin@quanta.corp-partner.google.com><br>Original-Reviewed-by: Vincent Wang <vwang@chromium.org><br>Original-Reviewed-by: YH Lin <yueherngl@chromium.org><br>Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org><br><br>Change-Id: I2166d1025ede33148c7ab623ba59190a342c4736<br>Signed-off-by: Matt DeVillier <matt.devillier@gmail.com><br>---<br>M src/mainboard/google/cyan/variants/banon/Makefile.inc<br>M src/mainboard/google/cyan/variants/banon/spd_util.c<br>2 files changed, 12 insertions(+), 1 deletion(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/27764/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/mainboard/google/cyan/variants/banon/Makefile.inc b/src/mainboard/google/cyan/variants/banon/Makefile.inc</span><br><span>index f6a1f46..7210f15 100644</span><br><span>--- a/src/mainboard/google/cyan/variants/banon/Makefile.inc</span><br><span>+++ b/src/mainboard/google/cyan/variants/banon/Makefile.inc</span><br><span>@@ -26,6 +26,8 @@</span><br><span> SPD_SOURCES += empty</span><br><span> SPD_SOURCES += hynix_2GiB_dimm_H9CCNNN8GTMLAR-NUD</span><br><span> SPD_SOURCES += micron_2GiB_dimm_MT52L256M32D1PF</span><br><span style="color: hsl(120, 100%, 40%);">+SPD_SOURCES += hynix_dimm_H9CCNNN8GTALAR-NUD</span><br><span style="color: hsl(120, 100%, 40%);">+SPD_SOURCES += nayna_dimm_NT6CL256T32CM-H1</span><br><span> </span><br><span> SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f).spd.hex)</span><br><span> </span><br><span>diff --git a/src/mainboard/google/cyan/variants/banon/spd_util.c b/src/mainboard/google/cyan/variants/banon/spd_util.c</span><br><span>index 2c9181e..442a5ba 100644</span><br><span>--- a/src/mainboard/google/cyan/variants/banon/spd_util.c</span><br><span>+++ b/src/mainboard/google/cyan/variants/banon/spd_util.c</span><br><span>@@ -23,11 +23,14 @@</span><br><span>  * 0b0001 - 4GiB total - 2 x 2GiB Samsung K4E8E324EB-EGCF</span><br><span>  * 0b0011 - 4GiB total - 2 x 2GiB Hynix H9CCNNN8JTBLAR</span><br><span>  * 0b0100 - 4GiB total - 2 x 2GiB Micron MT52L256M32D1PF</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(120, 100%, 40%);">+ * 0b0101 - 4GiB total - 2 x 2GiB Hynix H9CCNNN8GTALAR</span><br><span style="color: hsl(120, 100%, 40%);">+ * 0b0110 - 4GiB total - 2 x 2GiB NY NT6CL256T32CM-H1</span><br><span>  * 0b1000 - 2GiB total - 1 x 2GiB Samsung K4E8E304EE-EGCE</span><br><span>  * 0b1001 - 2GiB total - 1 x 2GiB Samsung K4E8E324EB-EGCF</span><br><span>  * 0b1011 - 2GiB total - 1 x 2GiB Hynix H9CCNNN8JTBLAR</span><br><span>  * 0b1100 - 2GiB total - 1 x 2GiB Micron MT52L256M32D1PF</span><br><span style="color: hsl(120, 100%, 40%);">+ * 0b1101 - 2GiB total - 1 x 2GiB Hynix H9CCNNN8GTALAR</span><br><span style="color: hsl(120, 100%, 40%);">+ * 0b1110 - 2GiB total - 1 x 2GiB NY NT6CL256T32CM-H1</span><br><span>  */</span><br><span> </span><br><span> int get_variant_spd_index(int ram_id, int *dual)</span><br><span>@@ -56,7 +59,13 @@</span><br><span>   case 4:</span><br><span>              printk(BIOS_DEBUG, "Micron MT52L256M32D1PF\n");</span><br><span>            break;</span><br><span style="color: hsl(120, 100%, 40%);">+        case 5:</span><br><span style="color: hsl(120, 100%, 40%);">+               printk(BIOS_DEBUG, "Hynix H9CCNNN8GTALAR\n");</span><br><span style="color: hsl(120, 100%, 40%);">+               break;</span><br><span>       }</span><br><span style="color: hsl(120, 100%, 40%);">+     case 6:</span><br><span style="color: hsl(120, 100%, 40%);">+               printk(BIOS_DEBUG, "Nanya NT6CL256T32CM-H1\n");</span><br><span style="color: hsl(120, 100%, 40%);">+             break;</span><br><span> </span><br><span>   return spd_index;</span><br><span> }</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/27764">change 27764</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/27764"/><meta itemprop="name" content="View Cha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<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I2166d1025ede33148c7ab623ba59190a342c4736 </div>
<div style="display:none"> Gerrit-Change-Number: 27764 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Matt DeVillier <matt.devillier@gmail.com> </div>