<p>Matt DeVillier has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/27761">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">google/cyan: Mask Audio IRQ on boot<br><br>Adapted from chromium commit cf18ab6<br>[Strago: mask Audio IRQ on boot]<br><br>Do not start with audio interrupt unmasked; this causes interrupt storms<br>on newer kernels that no longer mask all interrupts when initializing<br>Cherryview pincontrol driver.<br><br>TEST=Boot various cyan boards with kernels 3.18 and 4.14;<br>verify everything works.<br><br>Original-Change-Id: Id621682d3b59fea3ac54fb0ab92c8df9c78a6d43<br>Original-Signed-off-by: Dmitry Torokhov <dtor@chromium.org><br>Original-Reviewed-on: https://chromium-review.googlesource.com/894688<br>Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org><br><br>Change-Id: Icb55c885ea661c41168d3bd24109d2cdbb225546<br>Signed-off-by: Matt DeVillier <matt.devillier@gmail.com><br>---<br>M src/mainboard/google/cyan/variants/celes/gpio.c<br>M src/mainboard/google/cyan/variants/cyan/gpio.c<br>M src/mainboard/google/cyan/variants/edgar/gpio.c<br>M src/mainboard/google/cyan/variants/kefka/gpio.c<br>M src/mainboard/google/cyan/variants/reks/gpio.c<br>M src/mainboard/google/cyan/variants/relm/gpio.c<br>M src/mainboard/google/cyan/variants/setzer/gpio.c<br>M src/mainboard/google/cyan/variants/terra/gpio.c<br>M src/mainboard/google/cyan/variants/ultima/gpio.c<br>M src/mainboard/google/cyan/variants/wizpig/gpio.c<br>10 files changed, 10 insertions(+), 10 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/61/27761/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/mainboard/google/cyan/variants/celes/gpio.c b/src/mainboard/google/cyan/variants/celes/gpio.c</span><br><span>index 10ca3b0..d011428 100644</span><br><span>--- a/src/mainboard/google/cyan/variants/celes/gpio.c</span><br><span>+++ b/src/mainboard/google/cyan/variants/celes/gpio.c</span><br><span>@@ -140,7 +140,7 @@</span><br><span> Native_M1, /* 92 GP_SSP_2_CLK */</span><br><span> NATIVE_PU20K(1), /* 93 PCIE_CLKREQ2B/PCIE_CLKREQ_WLAN# */</span><br><span> Native_M1, /* 94 GP_SSP_2_RXD */</span><br><span style="color: hsl(0, 100%, 40%);">- GPI(trig_edge_both, L1, P_5K_H, non_maskable, en_edge_detect, NA, NA),</span><br><span style="color: hsl(120, 100%, 40%);">+ GPI(trig_edge_both, L1, P_5K_H, 0, en_edge_detect, NA, NA),</span><br><span> /* 95 PCIE_CLKREQ3B/AUDIO_CODEC_IRQ */</span><br><span> Native_M1, /* 96 GP_SSP_2_FS */</span><br><span> NATIVE_FUNC(1, 0, inv_tx_enable), /* 97 GP_SSP_2f_TXD */</span><br><span>diff --git a/src/mainboard/google/cyan/variants/cyan/gpio.c b/src/mainboard/google/cyan/variants/cyan/gpio.c</span><br><span>index 62fcb5e..4139f76 100644</span><br><span>--- a/src/mainboard/google/cyan/variants/cyan/gpio.c</span><br><span>+++ b/src/mainboard/google/cyan/variants/cyan/gpio.c</span><br><span>@@ -138,7 +138,7 @@</span><br><span> Native_M1, /* 92 GP_SSP_2_CLK */</span><br><span> NATIVE_PU20K(1), /* 93 PCIE_CLKREQ2B/PCIE_CLKREQ_WLAN# */</span><br><span> Native_M1, /* 94 GP_SSP_2_RXD */</span><br><span style="color: hsl(0, 100%, 40%);">- GPI(trig_edge_both, L1, P_5K_H, non_maskable, en_edge_detect, NA, NA),</span><br><span style="color: hsl(120, 100%, 40%);">+ GPI(trig_edge_both, L1, P_5K_H, 0, en_edge_detect, NA, NA),</span><br><span> /* 95 PCIE_CLKREQ3B/AUDIO_CODEC_IRQ */</span><br><span> Native_M1, /* 96 GP_SSP_2_FS */</span><br><span> NATIVE_FUNC(1, 0, inv_tx_enable), /* 97 GP_SSP_2f_TXD */</span><br><span>diff --git a/src/mainboard/google/cyan/variants/edgar/gpio.c b/src/mainboard/google/cyan/variants/edgar/gpio.c</span><br><span>index 97e2dd1..d9d2648 100644</span><br><span>--- a/src/mainboard/google/cyan/variants/edgar/gpio.c</span><br><span>+++ b/src/mainboard/google/cyan/variants/edgar/gpio.c</span><br><span>@@ -137,7 +137,7 @@</span><br><span> Native_M1, /* 92 GP_SSP_2_CLK */</span><br><span> NATIVE_PU20K(1), /* 93 PCIE_CLKREQ2B/PCIE_CLKREQ_WLAN# */</span><br><span> Native_M1, /* 94 GP_SSP_2_RXD */</span><br><span style="color: hsl(0, 100%, 40%);">- GPI(trig_edge_both, L1, P_5K_H, non_maskable, en_edge_detect, NA, NA),</span><br><span style="color: hsl(120, 100%, 40%);">+ GPI(trig_edge_both, L1, P_5K_H, 0, en_edge_detect, NA, NA),</span><br><span> /* 95 PCIE_CLKREQ3B/AUDIO_CODEC_IRQ */</span><br><span> Native_M1, /* 96 GP_SSP_2_FS */</span><br><span> NATIVE_FUNC(1, 0, inv_tx_enable), /* 97 GP_SSP_2f_TXD */</span><br><span>diff --git a/src/mainboard/google/cyan/variants/kefka/gpio.c b/src/mainboard/google/cyan/variants/kefka/gpio.c</span><br><span>index 8340f1a..76549ba4 100644</span><br><span>--- a/src/mainboard/google/cyan/variants/kefka/gpio.c</span><br><span>+++ b/src/mainboard/google/cyan/variants/kefka/gpio.c</span><br><span>@@ -137,7 +137,7 @@</span><br><span> Native_M1, /* 92 GP_SSP_2_CLK */</span><br><span> NATIVE_PU20K(1), /* 93 PCIE_CLKREQ2B/PCIE_CLKREQ_WLAN# */</span><br><span> Native_M1, /* 94 GP_SSP_2_RXD */</span><br><span style="color: hsl(0, 100%, 40%);">- GPI(trig_edge_both, L1, P_5K_H, non_maskable, en_edge_detect, NA, NA),</span><br><span style="color: hsl(120, 100%, 40%);">+ GPI(trig_edge_both, L1, P_5K_H, 0, en_edge_detect, NA, NA),</span><br><span> /* 95 PCIE_CLKREQ3B/AUDIO_CODEC_IRQ */</span><br><span> Native_M1, /* 96 GP_SSP_2_FS */</span><br><span> NATIVE_FUNC(1, 0, inv_tx_enable), /* 97 GP_SSP_2f_TXD */</span><br><span>diff --git a/src/mainboard/google/cyan/variants/reks/gpio.c b/src/mainboard/google/cyan/variants/reks/gpio.c</span><br><span>index 74792bd..1a9e540 100644</span><br><span>--- a/src/mainboard/google/cyan/variants/reks/gpio.c</span><br><span>+++ b/src/mainboard/google/cyan/variants/reks/gpio.c</span><br><span>@@ -139,7 +139,7 @@</span><br><span> Native_M1, /* 92 GP_SSP_2_CLK */</span><br><span> NATIVE_PU20K(1), /* 93 PCIE_CLKREQ2B/PCIE_CLKREQ_WLAN# */</span><br><span> Native_M1, /* 94 GP_SSP_2_RXD */</span><br><span style="color: hsl(0, 100%, 40%);">- GPI(trig_edge_both, L1, P_5K_H, non_maskable, en_edge_detect, NA, NA),</span><br><span style="color: hsl(120, 100%, 40%);">+ GPI(trig_edge_both, L1, P_5K_H, 0, en_edge_detect, NA, NA),</span><br><span> /* 95 PCIE_CLKREQ3B/AUDIO_CODEC_IRQ */</span><br><span> Native_M1, /* 96 GP_SSP_2_FS */</span><br><span> NATIVE_FUNC(1, 0, inv_tx_enable), /* 97 GP_SSP_2f_TXD */</span><br><span>diff --git a/src/mainboard/google/cyan/variants/relm/gpio.c b/src/mainboard/google/cyan/variants/relm/gpio.c</span><br><span>index 6b75a84..6c1dbdc 100644</span><br><span>--- a/src/mainboard/google/cyan/variants/relm/gpio.c</span><br><span>+++ b/src/mainboard/google/cyan/variants/relm/gpio.c</span><br><span>@@ -140,7 +140,7 @@</span><br><span> Native_M1, /* 92 GP_SSP_2_CLK */</span><br><span> NATIVE_PU20K(1), /* 93 PCIE_CLKREQ2B/PCIE_CLKREQ_WLAN# */</span><br><span> Native_M1, /* 94 GP_SSP_2_RXD */</span><br><span style="color: hsl(0, 100%, 40%);">- GPI(trig_edge_both, L1, P_5K_H, non_maskable, en_edge_detect, NA, NA),</span><br><span style="color: hsl(120, 100%, 40%);">+ GPI(trig_edge_both, L1, P_5K_H, 0, en_edge_detect, NA, NA),</span><br><span> /* 95 PCIE_CLKREQ3B/AUDIO_CODEC_IRQ */</span><br><span> Native_M1, /* 96 GP_SSP_2_FS */</span><br><span> NATIVE_FUNC(1, 0, inv_tx_enable), /* 97 GP_SSP_2f_TXD */</span><br><span>diff --git a/src/mainboard/google/cyan/variants/setzer/gpio.c b/src/mainboard/google/cyan/variants/setzer/gpio.c</span><br><span>index a1564c1..df1bff1 100644</span><br><span>--- a/src/mainboard/google/cyan/variants/setzer/gpio.c</span><br><span>+++ b/src/mainboard/google/cyan/variants/setzer/gpio.c</span><br><span>@@ -138,7 +138,7 @@</span><br><span> Native_M1, /* 92 GP_SSP_2_CLK */</span><br><span> NATIVE_PU20K(1), /* 93 PCIE_CLKREQ2B/PCIE_CLKREQ_WLAN# */</span><br><span> Native_M1, /* 94 GP_SSP_2_RXD */</span><br><span style="color: hsl(0, 100%, 40%);">- GPI(trig_edge_both, L1, P_5K_H, non_maskable, en_edge_detect, NA, NA),</span><br><span style="color: hsl(120, 100%, 40%);">+ GPI(trig_edge_both, L1, P_5K_H, 0, en_edge_detect, NA, NA),</span><br><span> /* 95 PCIE_CLKREQ3B/AUDIO_CODEC_IRQ */</span><br><span> Native_M1, /* 96 GP_SSP_2_FS */</span><br><span> NATIVE_FUNC(1, 0, inv_tx_enable), /* 97 GP_SSP_2f_TXD */</span><br><span>diff --git a/src/mainboard/google/cyan/variants/terra/gpio.c b/src/mainboard/google/cyan/variants/terra/gpio.c</span><br><span>index 3f5c19d..8328edd 100644</span><br><span>--- a/src/mainboard/google/cyan/variants/terra/gpio.c</span><br><span>+++ b/src/mainboard/google/cyan/variants/terra/gpio.c</span><br><span>@@ -136,7 +136,7 @@</span><br><span> Native_M1, /* 92 GP_SSP_2_CLK */</span><br><span> NATIVE_PU20K(1), /* 93 PCIE_CLKREQ2B/PCIE_CLKREQ_WLAN# */</span><br><span> Native_M1, /* 94 GP_SSP_2_RXD */</span><br><span style="color: hsl(0, 100%, 40%);">- GPI(trig_edge_both, L1, P_5K_H, non_maskable, en_edge_detect, NA, NA),</span><br><span style="color: hsl(120, 100%, 40%);">+ GPI(trig_edge_both, L1, P_5K_H, 0, en_edge_detect, NA, NA),</span><br><span> /* 95 PCIE_CLKREQ3B/AUDIO_CODEC_IRQ */</span><br><span> Native_M1, /* 96 GP_SSP_2_FS */</span><br><span> NATIVE_FUNC(1, 0, inv_tx_enable), /* 97 GP_SSP_2f_TXD */</span><br><span>diff --git a/src/mainboard/google/cyan/variants/ultima/gpio.c b/src/mainboard/google/cyan/variants/ultima/gpio.c</span><br><span>index 4e4f0f6..c6875b4 100644</span><br><span>--- a/src/mainboard/google/cyan/variants/ultima/gpio.c</span><br><span>+++ b/src/mainboard/google/cyan/variants/ultima/gpio.c</span><br><span>@@ -139,7 +139,7 @@</span><br><span> Native_M1, /* 92 GP_SSP_2_CLK */</span><br><span> NATIVE_PU20K(1), /* 93 PCIE_CLKREQ2B/PCIE_CLKREQ_WLAN# */</span><br><span> Native_M1, /* 94 GP_SSP_2_RXD */</span><br><span style="color: hsl(0, 100%, 40%);">- GPI(trig_edge_both, L1, P_5K_H, non_maskable, en_edge_detect, NA, NA),</span><br><span style="color: hsl(120, 100%, 40%);">+ GPI(trig_edge_both, L1, P_5K_H, 0, en_edge_detect, NA, NA),</span><br><span> /* 95 PCIE_CLKREQ3B/AUDIO_CODEC_IRQ */</span><br><span> Native_M1, /* 96 GP_SSP_2_FS */</span><br><span> NATIVE_FUNC(1, 0, inv_tx_enable), /* 97 GP_SSP_2f_TXD */</span><br><span>diff --git a/src/mainboard/google/cyan/variants/wizpig/gpio.c b/src/mainboard/google/cyan/variants/wizpig/gpio.c</span><br><span>index cadaf02..3611439 100644</span><br><span>--- a/src/mainboard/google/cyan/variants/wizpig/gpio.c</span><br><span>+++ b/src/mainboard/google/cyan/variants/wizpig/gpio.c</span><br><span>@@ -138,7 +138,7 @@</span><br><span> Native_M1, /* 92 GP_SSP_2_CLK */</span><br><span> NATIVE_PU20K(1), /* 93 PCIE_CLKREQ2B/PCIE_CLKREQ_WLAN# */</span><br><span> Native_M1, /* 94 GP_SSP_2_RXD */</span><br><span style="color: hsl(0, 100%, 40%);">- GPI(trig_edge_both, L1, P_5K_H, non_maskable, en_edge_detect, NA, NA),</span><br><span style="color: hsl(120, 100%, 40%);">+ GPI(trig_edge_both, L1, P_5K_H, 0, en_edge_detect, NA, NA),</span><br><span> /* 95 PCIE_CLKREQ3B/AUDIO_CODEC_IRQ */</span><br><span> Native_M1, /* 96 GP_SSP_2_FS */</span><br><span> NATIVE_FUNC(1, 0, inv_tx_enable), /* 97 GP_SSP_2f_TXD */</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/27761">change 27761</a>. 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<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: Icb55c885ea661c41168d3bd24109d2cdbb225546 </div>
<div style="display:none"> Gerrit-Change-Number: 27761 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Matt DeVillier <matt.devillier@gmail.com> </div>