<p>John Zhao has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/27746">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">soc/intel/apollolake: Force USB-C into host mode<br><br>When USB OTG is set, GLK FSP enables xHCI SW ID pin and configures<br>USB-C as device mode. Force USB-C into host mode.<br><br>BUG=b:111623911<br>TEST=Verified that USB-C being host mode once USB OTG is set.<br><br>Change-Id: Iaca3d25a1159f922b743963cbc508d8defa7b6ff<br>Signed-off-by: John Zhao <john.zhao@intel.com><br>---<br>M src/soc/intel/apollolake/chip.c<br>M src/soc/intel/apollolake/chip.h<br>2 files changed, 46 insertions(+), 0 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/27746/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c</span><br><span>index 081bba3..347a8e1 100644</span><br><span>--- a/src/soc/intel/apollolake/chip.c</span><br><span>+++ b/src/soc/intel/apollolake/chip.c</span><br><span>@@ -49,6 +49,8 @@</span><br><span> #include <soc/cpu.h></span><br><span> #include <soc/pm.h></span><br><span> #include <soc/systemagent.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <security/vboot/vboot_common.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <timer.h></span><br><span> </span><br><span> #include "chip.h"</span><br><span> </span><br><span>@@ -666,6 +668,42 @@</span><br><span> * security.</span><br><span> */</span><br><span> drop_privilege_all();</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /*</span><br><span style="color: hsl(120, 100%, 40%);">+ * When USB OTG is set, GLK FSP enables xHCI SW ID pin and configures</span><br><span style="color: hsl(120, 100%, 40%);">+ * USB-C as device mode. Force USB-C into host mode.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+ if (IS_ENABLED(CONFIG_SOC_INTEL_GLK) && vboot_can_enable_udc()) {</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t *cfg0;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t *cfg1;</span><br><span style="color: hsl(120, 100%, 40%);">+ const struct resource *res;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t reg;</span><br><span style="color: hsl(120, 100%, 40%);">+ struct stopwatch sw;</span><br><span style="color: hsl(120, 100%, 40%);">+ struct device *xhci_dev = PCH_DEV_XHCI;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ printk(BIOS_INFO, "Putting xHCI port 0 into host mode.\n");</span><br><span style="color: hsl(120, 100%, 40%);">+ res = find_resource(xhci_dev, PCI_BASE_ADDRESS_0);</span><br><span style="color: hsl(120, 100%, 40%);">+ cfg0 = (void *)(uintptr_t)(res->base + DUAL_ROLE_CFG0);</span><br><span style="color: hsl(120, 100%, 40%);">+ cfg1 = (void *)(uintptr_t)(res->base + DUAL_ROLE_CFG1);</span><br><span style="color: hsl(120, 100%, 40%);">+ reg = read32(cfg0);</span><br><span style="color: hsl(120, 100%, 40%);">+ if (reg && SW_IDPIN_EN_MASK) {</span><br><span style="color: hsl(120, 100%, 40%);">+ reg &= ~SW_IDPIN_MASK;</span><br><span style="color: hsl(120, 100%, 40%);">+ reg |= SW_IDPIN_HOST;</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ write32(cfg0, reg);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ stopwatch_init_msecs_expire(&sw, 10);</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Wait for the host mode status bit. */</span><br><span style="color: hsl(120, 100%, 40%);">+ while ((read32(cfg1) & DRD_MODE_MASK) != DRD_MODE_HOST) {</span><br><span style="color: hsl(120, 100%, 40%);">+ if (stopwatch_expired(&sw)) {</span><br><span style="color: hsl(120, 100%, 40%);">+ printk(BIOS_INFO, "Timed out waiting for host mode.\n");</span><br><span style="color: hsl(120, 100%, 40%);">+ break;</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ printk(BIOS_INFO, "xHCI port 0 host switch over took %lu ms\n",</span><br><span style="color: hsl(120, 100%, 40%);">+ stopwatch_duration_msecs(&sw));</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span> }</span><br><span> }</span><br><span> </span><br><span>diff --git a/src/soc/intel/apollolake/chip.h b/src/soc/intel/apollolake/chip.h</span><br><span>index 61ddeda..508965c 100644</span><br><span>--- a/src/soc/intel/apollolake/chip.h</span><br><span>+++ b/src/soc/intel/apollolake/chip.h</span><br><span>@@ -33,6 +33,14 @@</span><br><span> #define MAX_PCIE_PORTS 6</span><br><span> #define CLKREQ_DISABLED 0xf</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+#define DUAL_ROLE_CFG0 0x80d8</span><br><span style="color: hsl(120, 100%, 40%);">+#define SW_IDPIN_EN_MASK (1 << 21)</span><br><span style="color: hsl(120, 100%, 40%);">+#define SW_IDPIN_MASK (1 << 20)</span><br><span style="color: hsl(120, 100%, 40%);">+#define SW_IDPIN_HOST (0 << 20)</span><br><span style="color: hsl(120, 100%, 40%);">+#define DUAL_ROLE_CFG1 0x80dc</span><br><span style="color: hsl(120, 100%, 40%);">+#define DRD_MODE_MASK (1 << 29)</span><br><span style="color: hsl(120, 100%, 40%);">+#define DRD_MODE_HOST (1 << 29)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> enum pnp_settings {</span><br><span> PNP_PERF,</span><br><span> PNP_POWER,</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/27746">change 27746</a>. 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<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: Iaca3d25a1159f922b743963cbc508d8defa7b6ff </div>
<div style="display:none"> Gerrit-Change-Number: 27746 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: John Zhao <john.zhao@intel.com> </div>