<p>Felix Held has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/27717">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">x4x/raminit_ddr23: use MCHBAR AND/OR/AND_OR macros [1/2]<br><br>When using reproducible builds and coreboot crossgcc 6.3.0, the checksum of the<br>resulting binary doesn't change with applying this commit.<br><br>Change-Id: I057abe314622e92000c7e4ff2faa4595edb5244b<br>Signed-off-by: Felix Held <felix-coreboot@felixheld.de><br>---<br>M src/northbridge/intel/x4x/raminit_ddr23.c<br>1 file changed, 224 insertions(+), 222 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/27717/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/northbridge/intel/x4x/raminit_ddr23.c b/src/northbridge/intel/x4x/raminit_ddr23.c</span><br><span>index 6cc5e32..71130e0 100644</span><br><span>--- a/src/northbridge/intel/x4x/raminit_ddr23.c</span><br><span>+++ b/src/northbridge/intel/x4x/raminit_ddr23.c</span><br><span>@@ -53,7 +53,7 @@</span><br><span> {</span><br><span> u8 i, j;</span><br><span> u32 reg32;</span><br><span style="color: hsl(0, 100%, 40%);">- MCHBAR16(0xc1c) = MCHBAR16(0xc1c) | (1 << 15);</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR16_OR(0xc1c, (1 << 15));</span><br><span> </span><br><span> static const u32 clkxtab[6][3][13] = {</span><br><span> /* MEMCLK 400 N/A */</span><br><span>@@ -125,7 +125,7 @@</span><br><span> }</span><br><span> MCHBAR32(0xc50) = reg32;</span><br><span> MCHBAR32(0xc54) = clkxtab[i][j][2];</span><br><span style="color: hsl(0, 100%, 40%);">- MCHBAR8(0xc08) = MCHBAR8(0xc08) | (1 << 7);</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR8_OR(0xc08, (1 << 7));</span><br><span> MCHBAR32(0x6d8) = clkxtab[i][j][3];</span><br><span> MCHBAR32(0x6e0) = clkxtab[i][j][3];</span><br><span> MCHBAR32(0x6dc) = clkxtab[i][j][4];</span><br><span>@@ -143,29 +143,29 @@</span><br><span> static void setioclk_dram(struct sysinfo *s)</span><br><span> {</span><br><span> MCHBAR32(0x1bc) = 0x08060402;</span><br><span style="color: hsl(0, 100%, 40%);">- MCHBAR16(0x1c0) = MCHBAR16(0x1c0) | 0x200;</span><br><span style="color: hsl(0, 100%, 40%);">- MCHBAR16(0x1c0) = MCHBAR16(0x1c0) | 0x100;</span><br><span style="color: hsl(0, 100%, 40%);">- MCHBAR16(0x1c0) = MCHBAR16(0x1c0) | 0x20;</span><br><span style="color: hsl(0, 100%, 40%);">- MCHBAR16(0x1c0) = MCHBAR16(0x1c0) & ~1;</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR16_OR(0x1c0, 0x200);</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR16_OR(0x1c0, 0x100);</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR16_OR(0x1c0, 0x20);</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR16_AND(0x1c0, ~1);</span><br><span> switch (s->selected_timings.mem_clk) {</span><br><span> default:</span><br><span> case MEM_CLOCK_800MHz:</span><br><span> case MEM_CLOCK_1066MHz:</span><br><span style="color: hsl(0, 100%, 40%);">- MCHBAR8(0x5d9) = (MCHBAR8(0x5d9) & ~0x2) | 0x2;</span><br><span style="color: hsl(0, 100%, 40%);">- MCHBAR8(0x9d9) = (MCHBAR8(0x9d9) & ~0x2) | 0x2;</span><br><span style="color: hsl(0, 100%, 40%);">- MCHBAR8(0x189) = (MCHBAR8(0x189) & ~0xf0) | 0xc0;</span><br><span style="color: hsl(0, 100%, 40%);">- MCHBAR8(0x189) = (MCHBAR8(0x189) & ~0xf0) | 0xe0;</span><br><span style="color: hsl(0, 100%, 40%);">- MCHBAR8(0x189) = (MCHBAR8(0x189) & ~0xf0) | 0xa0;</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR8_AND_OR(0x5d9, ~0x2, 0x2);</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR8_AND_OR(0x9d9, ~0x2, 0x2);</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR8_AND_OR(0x189, ~0xf0, 0xc0);</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR8_AND_OR(0x189, ~0xf0, 0xe0);</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR8_AND_OR(0x189, ~0xf0, 0xa0);</span><br><span> break;</span><br><span> case MEM_CLOCK_667MHz:</span><br><span> case MEM_CLOCK_1333MHz:</span><br><span style="color: hsl(0, 100%, 40%);">- MCHBAR8(0x5d9) = MCHBAR8(0x5d9) & ~0x2;</span><br><span style="color: hsl(0, 100%, 40%);">- MCHBAR8(0x9d9) = MCHBAR8(0x9d9) & ~0x2;</span><br><span style="color: hsl(0, 100%, 40%);">- MCHBAR8(0x189) = (MCHBAR8(0x189) & ~0xf0) | 0x40;</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR8_AND(0x5d9, ~0x2);</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR8_AND(0x9d9, ~0x2);</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR8_AND_OR(0x189, ~0xf0, 0x40);</span><br><span> break;</span><br><span> }</span><br><span style="color: hsl(0, 100%, 40%);">- MCHBAR32(0x594) = MCHBAR32(0x594) | (1 << 31);</span><br><span style="color: hsl(0, 100%, 40%);">- MCHBAR32(0x994) = MCHBAR32(0x994) | (1 << 31);</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32_OR(0x594, 1 << 31);</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32_OR(0x994, 1 << 31);</span><br><span> }</span><br><span> </span><br><span> static void launch_dram(struct sysinfo *s)</span><br><span>@@ -253,14 +253,14 @@</span><br><span> MCHBAR32(0x400*i + 0x220) = launch1;</span><br><span> MCHBAR32(0x400*i + 0x224) = launch2;</span><br><span> MCHBAR32(0x400*i + 0x21c) = 0;</span><br><span style="color: hsl(0, 100%, 40%);">- MCHBAR32(0x400*i + 0x248) = MCHBAR32(0x400*i + 0x248) | (1 << 23);</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32_OR(0x400*i + 0x248, 1 << 23);</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- MCHBAR32(0x2c0) = (MCHBAR32(0x2c0) & ~0x58000000) | 0x48000000;</span><br><span style="color: hsl(0, 100%, 40%);">- MCHBAR32(0x2c0) = MCHBAR32(0x2c0) | 0x1e0;</span><br><span style="color: hsl(0, 100%, 40%);">- MCHBAR32(0x2c4) = (MCHBAR32(0x2c4) & ~0xf) | 0xc;</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32_AND_OR(0x2c0, ~0x58000000, 0x48000000);</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32_OR(0x2c0, 0x1e0);</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32_AND_OR(0x2c4, ~0xf, 0xc);</span><br><span> if (s->spd_type == DDR3)</span><br><span style="color: hsl(0, 100%, 40%);">- MCHBAR32(0x2c4) = MCHBAR32(0x2c4) | 0x100;</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32_OR(0x2c4, 0x100);</span><br><span> }</span><br><span> </span><br><span> static void clkset0(u8 ch, const struct dll_setting *setting)</span><br><span>@@ -541,10 +541,10 @@</span><br><span> }</span><br><span> </span><br><span> FOR_EACH_POPULATED_CHANNEL(s->dimms, i) {</span><br><span style="color: hsl(0, 100%, 40%);">- MCHBAR8(0x400*i + 0x26f) = MCHBAR8(0x400*i + 0x26f) | 0x3;</span><br><span style="color: hsl(0, 100%, 40%);">- MCHBAR8(0x400*i + 0x228) = (MCHBAR8(0x400*i + 0x228) & ~0x7) | 0x2;</span><br><span style="color: hsl(0, 100%, 40%);">- MCHBAR8(0x400*i + 0x240) = (MCHBAR8(0x400*i + 0x240) & ~0xf0)</span><br><span style="color: hsl(0, 100%, 40%);">- | (0 << 4); /* tWL - x ?? */</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR8_OR(0x400*i + 0x26f, 0x3);</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR8_AND_OR(0x400*i + 0x228, ~0x7, 0x2);</span><br><span style="color: hsl(120, 100%, 40%);">+ /* tWL - x ?? */</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR8_AND_OR(0x400*i + 0x240, ~0xf0, 0 << 4);</span><br><span> MCHBAR8(0x400*i + 0x240) = (MCHBAR8(0x400*i + 0x240) & ~0xf) |</span><br><span> adjusted_cas;</span><br><span> MCHBAR16(0x400*i + 0x265) = (MCHBAR16(0x400*i + 0x265) & ~0x3f00) |</span><br><span>@@ -628,13 +628,13 @@</span><br><span> }</span><br><span> reg16 |= flag1 << 8;</span><br><span> reg16 |= flag2 << 9;</span><br><span style="color: hsl(0, 100%, 40%);">- MCHBAR16(0x400*i + 0x24d) = (MCHBAR16(0x400*i + 0x24d) & ~0x1ff) | reg16;</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR16_AND_OR(0x400*i + 0x24d, ~0x1ff, reg16);</span><br><span> MCHBAR16(0x400*i + 0x25e) = 0x15a5;</span><br><span style="color: hsl(0, 100%, 40%);">- MCHBAR32(0x400*i + 0x265) = MCHBAR32(0x400*i + 0x265) & ~0x1f;</span><br><span style="color: hsl(0, 100%, 40%);">- MCHBAR32(0x400*i + 0x269) = (MCHBAR32(0x400*i + 0x269) & ~0x000fffff) |</span><br><span style="color: hsl(0, 100%, 40%);">- (0x3f << 14) | lut1[s->selected_timings.mem_clk];</span><br><span style="color: hsl(0, 100%, 40%);">- MCHBAR8(0x400*i + 0x274) = MCHBAR8(0x400*i + 0x274) | 1;</span><br><span style="color: hsl(0, 100%, 40%);">- MCHBAR8(0x400*i + 0x24c) = MCHBAR8(0x400*i + 0x24c) & ~0x3;</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32_AND(0x400*i + 0x265, ~0x1f);</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32_AND_OR(0x400*i + 0x269, ~0x000fffff,</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x3f << 14) | lut1[s->selected_timings.mem_clk]);</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR8_OR(0x400*i + 0x274, 1);</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR8_AND(0x400*i + 0x24c, ~0x3);</span><br><span> </span><br><span> reg16 = 0;</span><br><span> if (s->spd_type == DDR2) {</span><br><span>@@ -666,36 +666,36 @@</span><br><span> reg16 &= 0x7;</span><br><span> reg16 += twl + 9;</span><br><span> reg16 <<= 10;</span><br><span style="color: hsl(0, 100%, 40%);">- MCHBAR16(0x400*i + 0x24d) = (MCHBAR16(0x400*i + 0x24d) & ~0x7c00) | reg16;</span><br><span style="color: hsl(0, 100%, 40%);">- MCHBAR8(0x400*i + 0x267) = (MCHBAR8(0x400*i + 0x267) & ~0x3f) | 0x13;</span><br><span style="color: hsl(0, 100%, 40%);">- MCHBAR8(0x400*i + 0x268) = (MCHBAR8(0x400*i + 0x268) & ~0xff) | 0x4a;</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR16_AND_OR(0x400*i + 0x24d, ~0x7c00, reg16);</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR8_AND_OR(0x400*i + 0x267, ~0x3f, 0x13);</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR8_AND_OR(0x400*i + 0x268, ~0xff, 0x4a);</span><br><span> </span><br><span> reg16 = (MCHBAR16(0x400*i + 0x269) & 0xc000) >> 2;</span><br><span> reg16 += 2 << 12;</span><br><span> reg16 |= (0x15 << 6) | 0x1f;</span><br><span style="color: hsl(0, 100%, 40%);">- MCHBAR16(0x400*i + 0x26d) = (MCHBAR16(0x400*i + 0x26d) & ~0x7fff) | reg16;</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR16_AND_OR(0x400*i + 0x26d, ~0x7fff, reg16);</span><br><span> </span><br><span> reg32 = (1 << 25) | (6 << 27);</span><br><span style="color: hsl(0, 100%, 40%);">- MCHBAR32(0x400*i + 0x269) = (MCHBAR32(0x400*i + 0x269) & ~0xfa300000) | reg32;</span><br><span style="color: hsl(0, 100%, 40%);">- MCHBAR8(0x400*i + 0x271) = MCHBAR8(0x400*i + 0x271) & ~0x80;</span><br><span style="color: hsl(0, 100%, 40%);">- MCHBAR8(0x400*i + 0x274) = MCHBAR8(0x400*i + 0x274) & ~0x6;</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32_AND_OR(0x400*i + 0x269, ~0xfa300000, reg32);</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR8_AND(0x400*i + 0x271, ~0x80);</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR8_AND(0x400*i + 0x274, ~0x6);</span><br><span> } // END EACH POPULATED CHANNEL</span><br><span> </span><br><span> reg16 = 0x1f << 5;</span><br><span> reg16 |= 0xe << 10;</span><br><span style="color: hsl(0, 100%, 40%);">- MCHBAR16(0x125) = (MCHBAR16(0x125) & ~0x3fe0) | reg16;</span><br><span style="color: hsl(0, 100%, 40%);">- MCHBAR16(0x127) = (MCHBAR16(0x127) & ~0x7ff) | 0x540;</span><br><span style="color: hsl(0, 100%, 40%);">- MCHBAR8(0x129) = MCHBAR8(0x129) | 0x1f;</span><br><span style="color: hsl(0, 100%, 40%);">- MCHBAR8(0x12c) = MCHBAR8(0x12c) | 0xa0;</span><br><span style="color: hsl(0, 100%, 40%);">- MCHBAR32(0x241) = (MCHBAR32(0x241) & ~0x1ffff) | 0x11;</span><br><span style="color: hsl(0, 100%, 40%);">- MCHBAR32(0x641) = (MCHBAR32(0x641) & ~0x1ffff) | 0x11;</span><br><span style="color: hsl(0, 100%, 40%);">- MCHBAR8(0x246) = MCHBAR8(0x246) & ~0x10;</span><br><span style="color: hsl(0, 100%, 40%);">- MCHBAR8(0x646) = MCHBAR8(0x646) & ~0x10;</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR16_AND_OR(0x125, ~0x3fe0, reg16);</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR16_AND_OR(0x127, ~0x7ff, 0x540);</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR8_OR(0x129, 0x1f);</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR8_OR(0x12c, 0xa0);</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32_AND_OR(0x241, ~0x1ffff, 0x11);</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32_AND_OR(0x641, ~0x1ffff, 0x11);</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR8_AND(0x246, ~0x10);</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR8_AND(0x646, ~0x10);</span><br><span> MCHBAR32(0x120) = (2 << 29) | (1 << 28) | (1 << 23) | 0xd7f5f;</span><br><span> reg8 = (u8)((MCHBAR32(0x252) & 0x1e000) >> 13);</span><br><span style="color: hsl(0, 100%, 40%);">- MCHBAR8(0x12d) = (MCHBAR8(0x12d) & ~0xf0) | (reg8 << 4);</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR8_AND_OR(0x12d, ~0xf0, reg8 << 4);</span><br><span> reg8 = (u8)((MCHBAR32(0x258) & 0x1e0000) >> 17);</span><br><span style="color: hsl(0, 100%, 40%);">- MCHBAR8(0x12d) = (MCHBAR8(0x12d) & ~0xf) | reg8;</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR8_AND_OR(0x12d, ~0xf, reg8);</span><br><span> MCHBAR8(0x12f) = 0x4c;</span><br><span> reg32 = (1 << 31) | (0x80 << 14) | (1 << 13) | (0xa << 9);</span><br><span> if (s->spd_type == DDR3) {</span><br><span>@@ -706,8 +706,8 @@</span><br><span> reg16 &= 0x1ff;</span><br><span> reg32 = (reg16 << 22) | (0x80 << 14) | (0xa << 9);</span><br><span> }</span><br><span style="color: hsl(0, 100%, 40%);">- MCHBAR32(0x6c0) = (MCHBAR32(0x6c0) & ~0xffffff00) | reg32;</span><br><span style="color: hsl(0, 100%, 40%);">- MCHBAR8(0x6c4) = (MCHBAR8(0x6c4) & ~0x7) | 0x2;</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32_AND_OR(0x6c0, ~0xffffff00, reg32);</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR8_AND_OR(0x6c4, ~0x7, 0x2);</span><br><span> }</span><br><span> </span><br><span> static void program_dll(struct sysinfo *s)</span><br><span>@@ -719,11 +719,11 @@</span><br><span> const u8 rank2clken[8] = { 0x04, 0x01, 0x20, 0x08, 0x01, 0x04,</span><br><span> 0x08, 0x10 };</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- MCHBAR16(0x180) = (MCHBAR16(0x180) & ~0x7e06) | 0xc04;</span><br><span style="color: hsl(0, 100%, 40%);">- MCHBAR16(0x182) = (MCHBAR16(0x182) & ~0x3ff) | 0xc8;</span><br><span style="color: hsl(0, 100%, 40%);">- MCHBAR16(0x18a) = (MCHBAR16(0x18a) & ~0x1f1f) | 0x0f0f;</span><br><span style="color: hsl(0, 100%, 40%);">- MCHBAR16(0x1b4) = (MCHBAR16(0x1b4) & ~0x8020) | 0x100;</span><br><span style="color: hsl(0, 100%, 40%);">- MCHBAR8(0x194) = (MCHBAR8(0x194) & ~0x77) | 0x33;</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR16_AND_OR(0x180, ~0x7e06, 0xc04);</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR16_AND_OR(0x182, ~0x3ff, 0xc8);</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR16_AND_OR(0x18a, ~0x1f1f, 0x0f0f);</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR16_AND_OR(0x1b4, ~0x8020, 0x100);</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR8_AND_OR(0x194, ~0x77, 0x33);</span><br><span> switch (s->selected_timings.mem_clk) {</span><br><span> default:</span><br><span> case MEM_CLOCK_667MHz:</span><br><span>@@ -737,41 +737,41 @@</span><br><span> reg16 = (0x7 << 9) | 0x7;</span><br><span> break;</span><br><span> }</span><br><span style="color: hsl(0, 100%, 40%);">- MCHBAR16(0x19c) = (MCHBAR16(0x19c) & ~0x1e0f) | reg16;</span><br><span style="color: hsl(0, 100%, 40%);">- MCHBAR16(0x19c) = (MCHBAR16(0x19c) & ~0x2030) | 0x2010;</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR16_AND_OR(0x19c, ~0x1e0f, reg16);</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR16_AND_OR(0x19c, ~0x2030, 0x2010);</span><br><span> udelay(1);</span><br><span style="color: hsl(0, 100%, 40%);">- MCHBAR16(0x198) = MCHBAR16(0x198) & ~0x100;</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR16_AND(0x198, ~0x100);</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- MCHBAR16(0x1c8) = (MCHBAR16(0x1c8) & ~0x1f) | 0xd;</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR16_AND_OR(0x1c8, ~0x1f, 0xd);</span><br><span> </span><br><span> udelay(1);</span><br><span style="color: hsl(0, 100%, 40%);">- MCHBAR8(0x190) = MCHBAR8(0x190) & ~1;</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR8_AND(0x190, ~1);</span><br><span> udelay(1); // 533ns</span><br><span style="color: hsl(0, 100%, 40%);">- MCHBAR32(0x198) = MCHBAR32(0x198) & ~0x11554000;</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32_AND(0x198, ~0x11554000);</span><br><span> udelay(1);</span><br><span style="color: hsl(0, 100%, 40%);">- MCHBAR32(0x198) = MCHBAR32(0x198) & ~0x1455;</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32_AND(0x198, ~0x1455);</span><br><span> udelay(1);</span><br><span style="color: hsl(0, 100%, 40%);">- MCHBAR8(0x583) = MCHBAR8(0x583) & ~0x1c;</span><br><span style="color: hsl(0, 100%, 40%);">- MCHBAR8(0x983) = MCHBAR8(0x983) & ~0x1c;</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR8_AND(0x583, ~0x1c);</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR8_AND(0x983, ~0x1c);</span><br><span> udelay(1); // 533ns</span><br><span style="color: hsl(0, 100%, 40%);">- MCHBAR8(0x583) = MCHBAR8(0x583) & ~0x3;</span><br><span style="color: hsl(0, 100%, 40%);">- MCHBAR8(0x983) = MCHBAR8(0x983) & ~0x3;</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR8_AND(0x583, ~0x3);</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR8_AND(0x983, ~0x3);</span><br><span> udelay(1); // 533ns</span><br><span> </span><br><span> // ME related</span><br><span style="color: hsl(0, 100%, 40%);">- MCHBAR32(0x1a0) = (MCHBAR32(0x1a0) & ~0x7ffffff)</span><br><span style="color: hsl(0, 100%, 40%);">- | (s->spd_type == DDR2 ? 0x551803 : 0x555801);</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32_AND_OR(0x1a0, ~0x7ffffff,</span><br><span style="color: hsl(120, 100%, 40%);">+ s->spd_type == DDR2 ? 0x551803 : 0x555801);</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- MCHBAR16(0x1b4) = MCHBAR16(0x1b4) & ~0x800;</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR16_AND(0x1b4, ~0x800);</span><br><span> if (s->spd_type == DDR2) {</span><br><span style="color: hsl(0, 100%, 40%);">- MCHBAR8(0x1a8) = MCHBAR8(0x1a8) | 0xf0;</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR8_OR(0x1a8, 0xf0);</span><br><span> } else { /* DDR3 */</span><br><span> reg8 = 0x9; /* 0x9 << 4 ?? */</span><br><span> if (s->dimms[0].ranks == 2)</span><br><span> reg8 &= ~0x80;</span><br><span> if (s->dimms[3].ranks == 2)</span><br><span> reg8 &= ~0x10;</span><br><span style="color: hsl(0, 100%, 40%);">- MCHBAR8(0x1a8) = (MCHBAR8(0x1a8) & ~0xf0) | reg8;</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR8_AND_OR(0x1a8, ~0xf0, reg8);</span><br><span> }</span><br><span> </span><br><span> FOR_EACH_CHANNEL(i) {</span><br><span>@@ -787,8 +787,8 @@</span><br><span> reg32 |= 0x111 << r;</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- MCHBAR32(0x400*i + 0x59c) = (MCHBAR32(0x400*i + 0x59c) & ~0xfff) | reg32;</span><br><span style="color: hsl(0, 100%, 40%);">- MCHBAR8(0x400*i + 0x594) = MCHBAR8(0x400*i + 0x594) & ~1;</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32_AND_OR(0x400*i + 0x59c, ~0xfff, reg32);</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR8_AND(0x400*i + 0x594, ~1);</span><br><span> </span><br><span> if (s->spd_type == DDR2) {</span><br><span> if (!CHANNEL_IS_POPULATED(s->dimms, i)) {</span><br><span>@@ -813,8 +813,8 @@</span><br><span> } else {</span><br><span> die("Unhandled case\n");</span><br><span> }</span><br><span style="color: hsl(0, 100%, 40%);">- MCHBAR32(0x400*i + 0x5a0) = (MCHBAR32(0x400*i + 0x5a0)</span><br><span style="color: hsl(0, 100%, 40%);">- & ~0x3f000000) | ((u32)(reg8 << 24));</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32_AND_OR(0x400*i + 0x5a0, ~0x3f000000,</span><br><span style="color: hsl(120, 100%, 40%);">+ (u32)(reg8 << 24));</span><br><span> </span><br><span> } else { /* DDR3 */</span><br><span> FOR_EACH_POPULATED_RANK_IN_CHANNEL(s->dimms, i, r) {</span><br><span>@@ -828,25 +828,25 @@</span><br><span> } // END EACH CHANNEL</span><br><span> </span><br><span> if (s->spd_type == DDR2) {</span><br><span style="color: hsl(0, 100%, 40%);">- MCHBAR8(0x1a8) = MCHBAR8(0x1a8) | 1;</span><br><span style="color: hsl(0, 100%, 40%);">- MCHBAR8(0x1a8) = MCHBAR8(0x1a8) & ~0x4;</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR8_OR(0x1a8, 1);</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR8_AND(0x1a8, ~0x4);</span><br><span> } else { /* DDR3 */</span><br><span style="color: hsl(0, 100%, 40%);">- MCHBAR8(0x1a8) = MCHBAR8(0x1a8) & ~1;</span><br><span style="color: hsl(0, 100%, 40%);">- MCHBAR8(0x1a8) = MCHBAR8(0x1a8) | 0x4;</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR8_AND(0x1a8, ~1);</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR8_OR(0x1a8, 0x4);</span><br><span> }</span><br><span> </span><br><span> // Update DLL timing</span><br><span style="color: hsl(0, 100%, 40%);">- MCHBAR8(0x1a4) = MCHBAR8(0x1a4) & ~0x80;</span><br><span style="color: hsl(0, 100%, 40%);">- MCHBAR8(0x1a4) = MCHBAR8(0x1a4) | 0x40;</span><br><span style="color: hsl(0, 100%, 40%);">- MCHBAR16(0x5f0) = (MCHBAR16(0x5f0) & ~0x400) | 0x400;</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR8_AND(0x1a4, ~0x80);</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR8_OR(0x1a4, 0x40);</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR16_AND_OR(0x5f0, ~0x400, 0x400);</span><br><span> </span><br><span> FOR_EACH_POPULATED_CHANNEL(s->dimms, i) {</span><br><span style="color: hsl(0, 100%, 40%);">- MCHBAR16(0x400*i + 0x5f0) = (MCHBAR16(0x400*i + 0x5f0) & ~0x3fc) | 0x3fc;</span><br><span style="color: hsl(0, 100%, 40%);">- MCHBAR32(0x400*i + 0x5fc) = MCHBAR32(0x400*i + 0x5fc) & ~0xcccccccc;</span><br><span style="color: hsl(0, 100%, 40%);">- MCHBAR8(0x400*i + 0x5d9) = (MCHBAR8(0x400*i + 0x5d9) & ~0xf0)</span><br><span style="color: hsl(0, 100%, 40%);">- | (s->spd_type == DDR2 ? 0x70 : 0x60);</span><br><span style="color: hsl(0, 100%, 40%);">- MCHBAR16(0x400*i + 0x590) = (MCHBAR16(0x400*i + 0x590) & ~0xffff)</span><br><span style="color: hsl(0, 100%, 40%);">- | (s->spd_type == DDR2 ? 0x5555 : 0xa955);</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR16_AND_OR(0x400*i + 0x5f0, ~0x3fc, 0x3fc);</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32_AND(0x400*i + 0x5fc, ~0xcccccccc);</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR8_AND_OR(0x400*i + 0x5d9, ~0xf0,</span><br><span style="color: hsl(120, 100%, 40%);">+ s->spd_type == DDR2 ? 0x70 : 0x60);</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR16_AND_OR(0x400*i + 0x590, ~0xffff,</span><br><span style="color: hsl(120, 100%, 40%);">+ s->spd_type == DDR2 ? 0x5555 : 0xa955);</span><br><span> }</span><br><span> </span><br><span> FOR_EACH_POPULATED_CHANNEL(s->dimms, i) {</span><br><span>@@ -881,12 +881,12 @@</span><br><span> }</span><br><span> </span><br><span> // XXX if not async mode</span><br><span style="color: hsl(0, 100%, 40%);">- MCHBAR16(0x180) = MCHBAR16(0x180) & ~0x8200;</span><br><span style="color: hsl(0, 100%, 40%);">- MCHBAR8(0x180) = MCHBAR8(0x180) | 0x4;</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR16_AND(0x180, ~0x8200);</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR8_OR(0x180, 0x4);</span><br><span> j = 0;</span><br><span> for (i = 0; i < 16; i++) {</span><br><span style="color: hsl(0, 100%, 40%);">- MCHBAR8(0x1c8) = (MCHBAR8(0x1c8) & ~0x1f) | i;</span><br><span style="color: hsl(0, 100%, 40%);">- MCHBAR8(0x180) = MCHBAR8(0x180) | 0x10;</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR8_AND_OR(0x1c8, ~0x1f, i);</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR8_OR(0x180, 0x10);</span><br><span> while (MCHBAR8(0x180) & 0x10)</span><br><span> ;</span><br><span> if (MCHBAR32(0x184) == 0xffffffff) {</span><br><span>@@ -906,8 +906,8 @@</span><br><span> j = 0;</span><br><span> i++;</span><br><span> for (; i < 16; i++) {</span><br><span style="color: hsl(0, 100%, 40%);">- MCHBAR8(0x1c8) = (MCHBAR8(0x1c8) & ~0x1f) | i;</span><br><span style="color: hsl(0, 100%, 40%);">- MCHBAR8(0x180) = MCHBAR8(0x180) | 0x4;</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR8_AND_OR(0x1c8, ~0x1f, i);</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR8_OR(0x180, 0x4);</span><br><span> while (MCHBAR8(0x180) & 0x10)</span><br><span> ;</span><br><span> if (MCHBAR32(0x184) == 0) {</span><br><span>@@ -916,8 +916,8 @@</span><br><span> }</span><br><span> }</span><br><span> for (; i < 16; i++) {</span><br><span style="color: hsl(0, 100%, 40%);">- MCHBAR8(0x1c8) = (MCHBAR8(0x1c8) & ~0x1f) | i;</span><br><span style="color: hsl(0, 100%, 40%);">- MCHBAR8(0x180) = MCHBAR8(0x180) | 0x10;</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR8_AND_OR(0x1c8, ~0x1f, i);</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR8_OR(0x180, 0x10);</span><br><span> while (MCHBAR8(0x180) & 0x10)</span><br><span> ;</span><br><span> if (MCHBAR32(0x184) == 0xffffffff) {</span><br><span>@@ -929,8 +929,8 @@</span><br><span> }</span><br><span> }</span><br><span> if (j < 2) {</span><br><span style="color: hsl(0, 100%, 40%);">- MCHBAR8(0x1c8) = MCHBAR8(0x1c8) & ~0x1f;</span><br><span style="color: hsl(0, 100%, 40%);">- MCHBAR8(0x180) = MCHBAR8(0x180) | 0x10;</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR8_AND(0x1c8, ~0x1f);</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR8_OR(0x180, 0x10);</span><br><span> while (MCHBAR8(0x180) & 0x10)</span><br><span> ;</span><br><span> j = 2;</span><br><span>@@ -938,7 +938,7 @@</span><br><span> }</span><br><span> </span><br><span> if (j < 2) {</span><br><span style="color: hsl(0, 100%, 40%);">- MCHBAR8(0x1c8) = MCHBAR8(0x1c8) & ~0x1f;</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR8_AND(0x1c8, ~0x1f);</span><br><span> async = 1;</span><br><span> }</span><br><span> </span><br><span>@@ -968,7 +968,7 @@</span><br><span> if (async != 1)</span><br><span> reg8 = MCHBAR8(0x188) & 0x1e;</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- MCHBAR8(0x180) = MCHBAR8(0x180) & ~0x80;</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR8_AND(0x180, ~0x80);</span><br><span> </span><br><span> if ((s->spd_type == DDR3 && s->selected_timings.mem_clk == MEM_CLOCK_1066MHz)</span><br><span> || (s->spd_type == DDR2 && s->selected_timings.fsb_clk == FSB_CLOCK_800MHz</span><br><span>@@ -978,8 +978,8 @@</span><br><span> i = (i + 10) % 14;</span><br><span> else /* DDR3 */</span><br><span> i = (i + 3) % 12;</span><br><span style="color: hsl(0, 100%, 40%);">- MCHBAR8(0x1c8) = (MCHBAR8(0x1c8) & ~0x1f) | i;</span><br><span style="color: hsl(0, 100%, 40%);">- MCHBAR8(0x180) = MCHBAR8(0x180) | 0x10;</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR8_AND_OR(0x1c8, ~0x1f, i);</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR8_OR(0x180, 0x10);</span><br><span> while (MCHBAR8(0x180) & 0x10)</span><br><span> ;</span><br><span> }</span><br><span>@@ -993,7 +993,7 @@</span><br><span> MCHBAR8(0x188) = reg8;</span><br><span> </span><br><span> if (s->selected_timings.mem_clk == MEM_CLOCK_1333MHz)</span><br><span style="color: hsl(0, 100%, 40%);">- MCHBAR8(0x18c) = MCHBAR8(0x18c) | 1;</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR8_OR(0x18c, 1);</span><br><span> }</span><br><span> </span><br><span> static void select_default_dq_dqs_settings(struct sysinfo *s)</span><br><span>@@ -1145,8 +1145,8 @@</span><br><span> MCHBAR32(0x400*i + addr[j]) =</span><br><span> (MCHBAR32(0x400*i + addr[j]) & ~0xff000)</span><br><span> | 0xaa000;</span><br><span style="color: hsl(0, 100%, 40%);">- MCHBAR16(0x400*i + 0x320) = (MCHBAR16(0x400*i + 0x320)</span><br><span style="color: hsl(0, 100%, 40%);">- & ~0xffff) | 0x6666;</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR16_AND_OR(0x400*i + 0x320, ~0xffff,</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x6666);</span><br><span> for (k = 0; k < 8; k++) {</span><br><span> MCHBAR32(0x400*i + addr[j] + 0xe + (k << 2)) =</span><br><span> (MCHBAR32(0x400*i + addr[j] + 0xe + (k << 2))</span><br><span>@@ -1196,23 +1196,23 @@</span><br><span> MCHBAR8(0x400*i + addr[j]) = (MCHBAR8(0x400*i + addr[j]) & ~1) | bit[j];</span><br><span> }</span><br><span> reg8 = (s->spd_type == DDR2) ? 0x12 : 0x36;</span><br><span style="color: hsl(0, 100%, 40%);">- MCHBAR8(0x400*i + 0x45a) = (MCHBAR8(0x400*i + 0x45a) & ~0x3f) | reg8;</span><br><span style="color: hsl(0, 100%, 40%);">- MCHBAR8(0x400*i + 0x45e) = (MCHBAR8(0x400*i + 0x45e) & ~0x3f) | reg8;</span><br><span style="color: hsl(0, 100%, 40%);">- MCHBAR8(0x400*i + 0x462) = (MCHBAR8(0x400*i + 0x462) & ~0x3f) | reg8;</span><br><span style="color: hsl(0, 100%, 40%);">- MCHBAR8(0x400*i + 0x466) = (MCHBAR8(0x400*i + 0x466) & ~0x3f) | reg8;</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR8_AND_OR(0x400*i + 0x45a, ~0x3f, reg8);</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR8_AND_OR(0x400*i + 0x45e, ~0x3f, reg8);</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR8_AND_OR(0x400*i + 0x462, ~0x3f, reg8);</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR8_AND_OR(0x400*i + 0x466, ~0x3f, reg8);</span><br><span> } // END EACH POPULATED CHANNEL</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- MCHBAR32(0x134) = (MCHBAR32(0x134) & ~0x63c00) | 0x63c00;</span><br><span style="color: hsl(0, 100%, 40%);">- MCHBAR16(0x174) = (MCHBAR16(0x174) & ~0x63ff) | 0x63ff;</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32_AND_OR(0x134, ~0x63c00, 0x63c00);</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR16_AND_OR(0x174, ~0x63ff, 0x63ff);</span><br><span> MCHBAR16(0x178) = 0x0135;</span><br><span style="color: hsl(0, 100%, 40%);">- MCHBAR32(0x130) = (MCHBAR32(0x130) & ~0x7bdffe0) | 0x7a9ffa0;</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32_AND_OR(0x130, ~0x7bdffe0, 0x7a9ffa0);</span><br><span> </span><br><span> if (!CHANNEL_IS_POPULATED(s->dimms, 0))</span><br><span style="color: hsl(0, 100%, 40%);">- MCHBAR32(0x130) = MCHBAR32(0x130) & ~(1 << 27);</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32_AND(0x130, ~(1 << 27));</span><br><span> if (!CHANNEL_IS_POPULATED(s->dimms, 1))</span><br><span style="color: hsl(0, 100%, 40%);">- MCHBAR32(0x130) = MCHBAR32(0x130) & ~(1 << 28);</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32_AND(0x130, ~(1 << 28));</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- MCHBAR8(0x130) = MCHBAR8(0x130) | 1;</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR8_OR(0x130, 1);</span><br><span> }</span><br><span> </span><br><span> static void program_odt(struct sysinfo *s)</span><br><span>@@ -1306,8 +1306,8 @@</span><br><span> * by the SPD.</span><br><span> */</span><br><span> /* Set rank 0-3 populated */</span><br><span style="color: hsl(0, 100%, 40%);">- MCHBAR32(C0CKECTRL) = (MCHBAR32(C0CKECTRL) & ~1) | 0xf00000;</span><br><span style="color: hsl(0, 100%, 40%);">- MCHBAR32(C1CKECTRL) = (MCHBAR32(C1CKECTRL) & ~1) | 0xf00000;</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32_AND_OR(C0CKECTRL, ~1, 0xf00000);</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32_AND_OR(C1CKECTRL, ~1, 0xf00000);</span><br><span> /* Set size of each rank to 128M */</span><br><span> MCHBAR16(C0DRA01) = 0x0101;</span><br><span> MCHBAR16(C0DRA23) = 0x0101;</span><br><span>@@ -1323,7 +1323,7 @@</span><br><span> /* In stacked mode the last present rank on ch1 needs to have its</span><br><span> size doubled in c1drbx */</span><br><span> MCHBAR16(C1DRB3) = 0x0010;</span><br><span style="color: hsl(0, 100%, 40%);">- MCHBAR8(0x111) = MCHBAR8(0x111) | STACKED_MEM;</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR8_OR(0x111, STACKED_MEM);</span><br><span> MCHBAR32(0x104) = 0;</span><br><span> MCHBAR16(0x102) = 0x400;</span><br><span> MCHBAR8(0x110) = (2 << 5) | (3 << 3);</span><br><span>@@ -1371,8 +1371,8 @@</span><br><span> data8 = (u8)mirror_shift_bit(data8, 4);</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- MCHBAR8(0x271) = (MCHBAR8(0x271) & ~0x3e) | data8;</span><br><span style="color: hsl(0, 100%, 40%);">- MCHBAR8(0x671) = (MCHBAR8(0x671) & ~0x3e) | data8;</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR8_AND_OR(0x271, ~0x3e, data8);</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR8_AND_OR(0x671, ~0x3e, data8);</span><br><span> data32 = val;</span><br><span> if (s->spd_type == DDR3 && (r & 1)</span><br><span> && s->dimms[ch * 2 + (r >> 1)].mirrored) {</span><br><span>@@ -1384,8 +1384,8 @@</span><br><span> </span><br><span> rubbish = read32((void *)((data32 | addr)));</span><br><span> udelay(10);</span><br><span style="color: hsl(0, 100%, 40%);">- MCHBAR8(0x271) = (MCHBAR8(0x271) & ~0x3e) | NORMALOP_CMD;</span><br><span style="color: hsl(0, 100%, 40%);">- MCHBAR8(0x671) = (MCHBAR8(0x671) & ~0x3e) | NORMALOP_CMD;</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR8_AND_OR(0x271, ~0x3e, NORMALOP_CMD);</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR8_AND_OR(0x671, ~0x3e, NORMALOP_CMD);</span><br><span> }</span><br><span> </span><br><span> static void jedec_ddr2(struct sysinfo *s)</span><br><span>@@ -1611,23 +1611,22 @@</span><br><span> MCHBAR32(0x208) = c0dra;</span><br><span> MCHBAR32(0x608) = c1dra;</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- MCHBAR8(0x262) = (MCHBAR8(0x262) & ~0xf0) | ((rankpop0 << 4) & 0xf0);</span><br><span style="color: hsl(0, 100%, 40%);">- MCHBAR8(0x662) = (MCHBAR8(0x662) & ~0xf0) | ((rankpop1 << 4) & 0xf0);</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR8_AND_OR(0x262, ~0xf0, (rankpop0 << 4) & 0xf0);</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR8_AND_OR(0x662, ~0xf0, (rankpop1 << 4) & 0xf0);</span><br><span> </span><br><span> if (s->spd_type == DDR3) {</span><br><span> FOR_EACH_POPULATED_CHANNEL(s->dimms, ch) {</span><br><span> /* ZQCAL enable */</span><br><span style="color: hsl(0, 100%, 40%);">- MCHBAR32(0x269 + 0x400 * ch) =</span><br><span style="color: hsl(0, 100%, 40%);">- MCHBAR32(0x269 + 0x400 * ch) | (1 << 26);</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32_OR(0x269 + 0x400 * ch, 1 << 26);</span><br><span> }</span><br><span> }</span><br><span> </span><br><span> if (ONLY_DIMMA_IS_POPULATED(s->dimms, 0) ||</span><br><span> ONLY_DIMMB_IS_POPULATED(s->dimms, 0))</span><br><span style="color: hsl(0, 100%, 40%);">- MCHBAR8(0x260) = MCHBAR8(0x260) | 1;</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR8_OR(0x260, 1);</span><br><span> if (ONLY_DIMMA_IS_POPULATED(s->dimms, 1) ||</span><br><span> ONLY_DIMMB_IS_POPULATED(s->dimms, 1))</span><br><span style="color: hsl(0, 100%, 40%);">- MCHBAR8(0x660) = MCHBAR8(0x660) | 1;</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR8_OR(0x660, 1);</span><br><span> </span><br><span> // DRB</span><br><span> lastrank_ch1 = 0;</span><br><span>@@ -1671,10 +1670,10 @@</span><br><span> size_me = ME_UMA_SIZEMB;</span><br><span> </span><br><span> if (s->stacked_mode) {</span><br><span style="color: hsl(0, 100%, 40%);">- MCHBAR8(0x111) = MCHBAR8(0x111) | STACKED_MEM;</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR8_OR(0x111, STACKED_MEM);</span><br><span> } else {</span><br><span style="color: hsl(0, 100%, 40%);">- MCHBAR8(0x111) = MCHBAR8(0x111) & ~STACKED_MEM;</span><br><span style="color: hsl(0, 100%, 40%);">- MCHBAR8(0x111) = MCHBAR8(0x111) | (1 << 4);</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR8_AND(0x111, ~STACKED_MEM);</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR8_OR(0x111, 1 << 4);</span><br><span> }</span><br><span> </span><br><span> if (s->stacked_mode) {</span><br><span>@@ -1690,7 +1689,7 @@</span><br><span> /* Set ME UMA size in MiB */</span><br><span> MCHBAR16(0x100) = size_me;</span><br><span> /* Set ME UMA Present bit */</span><br><span style="color: hsl(0, 100%, 40%);">- MCHBAR32(0x111) = MCHBAR32(0x111) | 1;</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32_OR(0x111, 1);</span><br><span> }</span><br><span> dual_channel_size = MIN(size_ch0 - size_me, size_ch1) * 2;</span><br><span> }</span><br><span>@@ -1822,21 +1821,21 @@</span><br><span> MCHBAR32(0xfbc) = 0xf;</span><br><span> MCHBAR32(0xfc4) = 0xfe22244;</span><br><span> MCHBAR8(0x12f) = 0x5c;</span><br><span style="color: hsl(0, 100%, 40%);">- MCHBAR8(0xfb0) = (MCHBAR8(0xfb0) & ~1) | 1;</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR8_OR(0xfb0, 1);</span><br><span> if (s->selected_timings.mem_clk <= MEM_CLOCK_800MHz)</span><br><span style="color: hsl(0, 100%, 40%);">- MCHBAR8(0x12f) = MCHBAR8(0x12f) | 0x2;</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR8_OR(0x12f, 0x2);</span><br><span> else</span><br><span style="color: hsl(0, 100%, 40%);">- MCHBAR8(0x12f) = MCHBAR8(0x12f) & ~0x2;</span><br><span style="color: hsl(0, 100%, 40%);">- MCHBAR8(0x6c0) = (MCHBAR8(0x6c0) & ~0xf0) | 0xa0;</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR8_AND(0x12f, ~0x2);</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR8_AND_OR(0x6c0, ~0xf0, 0xa0);</span><br><span> MCHBAR32(0xfa8) = 0x30d400;</span><br><span> </span><br><span> FOR_EACH_POPULATED_CHANNEL(s->dimms, ch) {</span><br><span style="color: hsl(0, 100%, 40%);">- MCHBAR8(0x400*ch + 0x26c) = MCHBAR8(0x400*ch + 0x26c) | 1;</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR8_OR(0x400*ch + 0x26c, 1);</span><br><span> MCHBAR32(0x400*ch + 0x278) = 0x88141881;</span><br><span> MCHBAR16(0x400*ch + 0x27c) = 0x0041;</span><br><span> MCHBAR8(0x400*ch + 0x292) = 0xf2;</span><br><span style="color: hsl(0, 100%, 40%);">- MCHBAR16(0x400*ch + 0x272) = MCHBAR16(0x400*ch + 0x272) | 0x100;</span><br><span style="color: hsl(0, 100%, 40%);">- MCHBAR8(0x400*ch + 0x243) = (MCHBAR8(0x400*ch + 0x243) & ~0x2) | 1;</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR16_OR(0x400*ch + 0x272, 0x100);</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR8_AND_OR(0x400*ch + 0x243, ~0x2, 1);</span><br><span> MCHBAR32(0x400*ch + 0x288) = 0x8040200;</span><br><span> MCHBAR32(0x400*ch + 0x28c) = 0xff402010;</span><br><span> MCHBAR32(0x400*ch + 0x290) = 0x4f2091c;</span><br><span>@@ -1855,7 +1854,7 @@</span><br><span> } else if (s->selected_timings.fsb_clk == FSB_CLOCK_1066MHz) {</span><br><span> reg32 &= ~0x10000;</span><br><span> }</span><br><span style="color: hsl(0, 100%, 40%);">- MCHBAR32(0xfa4) = (MCHBAR32(0xfa4) & ~0x219100c3) | reg32;</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32_AND_OR(0xfa4, ~0x219100c3, reg32);</span><br><span> reg32 = 0x44a00;</span><br><span> switch (s->selected_timings.fsb_clk) {</span><br><span> case FSB_CLOCK_1333MHz:</span><br><span>@@ -1881,7 +1880,7 @@</span><br><span> reg32 = 0x8f038000;</span><br><span> if (s->selected_timings.fsb_clk == FSB_CLOCK_1333MHz)</span><br><span> reg32 &= ~0x4000000;</span><br><span style="color: hsl(0, 100%, 40%);">- MCHBAR32(0x40) = (MCHBAR32(0x40) & ~0x8f038000) | reg32;</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32_AND_OR(0x40, ~0x8f038000, reg32);</span><br><span> reg32 = 0x00013001;</span><br><span> if (s->selected_timings.fsb_clk < FSB_CLOCK_1333MHz)</span><br><span> reg32 |= 0x20000;</span><br><span>@@ -1954,47 +1953,50 @@</span><br><span> MCHBAR32(0x14) = 0x0010691f;</span><br><span> MCHBAR32(0x18) = 0xdf6437f7;</span><br><span> MCHBAR32(0x1c) = 0x0;</span><br><span style="color: hsl(0, 100%, 40%);">- MCHBAR32(0x24) = (MCHBAR32(0x24) & ~0xe0000000) | 0x60000000;</span><br><span style="color: hsl(0, 100%, 40%);">- MCHBAR32(0x44) = (MCHBAR32(0x44) & ~0x1fef0000) | 0x6b0000;</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32_AND_OR(0x24, ~0xe0000000, 0x60000000);</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32_AND_OR(0x44, ~0x1fef0000, 0x6b0000);</span><br><span> MCHBAR16(0x115) = (u16) reg1;</span><br><span style="color: hsl(0, 100%, 40%);">- MCHBAR32(0x117) = (MCHBAR32(0x117) & ~0xffffff) | reg2;</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32_AND_OR(0x117, ~0xffffff, reg2);</span><br><span> MCHBAR8(0x124) = 0x7;</span><br><span style="color: hsl(0, 100%, 40%);">- MCHBAR16(0x12a) = (MCHBAR16(0x12a) & 0) | 0x80;</span><br><span style="color: hsl(0, 100%, 40%);">- MCHBAR8(0x12c) = (MCHBAR8(0x12c) & 0) | 0xa0;</span><br><span style="color: hsl(0, 100%, 40%);">- MCHBAR16(0x174) = MCHBAR16(0x174) & ~(1 << 15);</span><br><span style="color: hsl(0, 100%, 40%);">- MCHBAR16(0x188) = (MCHBAR16(0x188) & ~0x1f00) | 0x1f00;</span><br><span style="color: hsl(0, 100%, 40%);">- MCHBAR8(0x18c) = MCHBAR8(0x18c) & ~0x8;</span><br><span style="color: hsl(0, 100%, 40%);">- MCHBAR8(0x192) = (MCHBAR8(0x192) & ~1) | 1;</span><br><span style="color: hsl(0, 100%, 40%);">- MCHBAR8(0x193) = (MCHBAR8(0x193) & ~0xf) | 0xf;</span><br><span style="color: hsl(0, 100%, 40%);">- MCHBAR16(0x1b4) = (MCHBAR16(0x1b4) & ~0x480) | 0x80;</span><br><span style="color: hsl(0, 100%, 40%);">- MCHBAR16(0x210) = (MCHBAR16(0x210) & ~0x1fff) | 0x3f; // | clockgatingiii</span><br><span style="color: hsl(0, 100%, 40%);">- MCHBAR32(0x6d1) = (MCHBAR32(0x6d1) & ~0xff03ff) | 0x100 | clkgate;</span><br><span style="color: hsl(0, 100%, 40%);">- MCHBAR8(0x212) = (MCHBAR8(0x212) & ~0x7f) | 0x7f;</span><br><span style="color: hsl(0, 100%, 40%);">- MCHBAR32(0x2c0) = (MCHBAR32(0x2c0) & ~0xffff0) | 0xcc5f0;</span><br><span style="color: hsl(0, 100%, 40%);">- MCHBAR8(0x2c4) = (MCHBAR8(0x2c4) & ~0x70) | 0x70;</span><br><span style="color: hsl(0, 100%, 40%);">- MCHBAR32(0x2d1) = (MCHBAR32(0x2d1) & ~0xffffff) | 0xff2831; // | clockgatingi</span><br><span style="color: hsl(120, 100%, 40%);">+ // not sure if dummy reads are needed</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR16_AND_OR(0x12a, 0, 0x80);</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR8_AND_OR(0x12c, 0, 0xa0);</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR16_AND(0x174, ~(1 << 15));</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR16_AND_OR(0x188, ~0x1f00, 0x1f00);</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR8_AND(0x18c, ~0x8);</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR8_OR(0x192, 1);</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR8_OR(0x193, 0xf);</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR16_AND_OR(0x1b4, ~0x480, 0x80);</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR16_AND_OR(0x210, ~0x1fff, 0x3f); // | clockgatingiii</span><br><span style="color: hsl(120, 100%, 40%);">+ // non-aligned access: possible bug?</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32_AND_OR(0x6d1, ~0xff03ff, 0x100 | clkgate);</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR8_AND_OR(0x212, ~0x7f, 0x7f);</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32_AND_OR(0x2c0, ~0xffff0, 0xcc5f0);</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR8_AND_OR(0x2c4, ~0x70, 0x70);</span><br><span style="color: hsl(120, 100%, 40%);">+ // non-aligned access: possible bug?</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32_AND_OR(0x2d1, ~0xffffff, 0xff2831); // | clockgatingi</span><br><span> MCHBAR32(0x2d4) = 0x40453600;</span><br><span> MCHBAR32(0x300) = 0xc0b0a08;</span><br><span> MCHBAR32(0x304) = 0x6040201;</span><br><span style="color: hsl(0, 100%, 40%);">- MCHBAR32(0x30c) = (MCHBAR32(0x30c) & ~0x43c0f) | 0x41405;</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32_AND_OR(0x30c, ~0x43c0f, 0x41405);</span><br><span> MCHBAR16(0x610) = reg3;</span><br><span> MCHBAR16(0x612) = reg4;</span><br><span style="color: hsl(0, 100%, 40%);">- MCHBAR32(0x62c) = (MCHBAR32(0x62c) & ~0xc000000) | 0x4000000;</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32_AND_OR(0x62c, ~0xc000000, 0x4000000);</span><br><span> MCHBAR32(0xae4) = 0;</span><br><span style="color: hsl(0, 100%, 40%);">- MCHBAR32(0xc00) = (MCHBAR32(0xc00) & ~0xf0000) | 0x10000;</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32_AND_OR(0xc00, ~0xf0000, 0x10000);</span><br><span> MCHBAR32(0xf00) = 0x393a3b3c;</span><br><span> MCHBAR32(0xf04) = 0x3d3e3f40;</span><br><span> MCHBAR32(0xf08) = 0x393a3b3c;</span><br><span> MCHBAR32(0xf0c) = 0x3d3e3f40;</span><br><span style="color: hsl(0, 100%, 40%);">- MCHBAR32(0xf18) = MCHBAR32(0xf18) & ~0xfff00001;</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32_AND(0xf18, ~0xfff00001);</span><br><span> MCHBAR32(0xf48) = 0xfff0ffe0;</span><br><span> MCHBAR32(0xf4c) = 0xffc0ff00;</span><br><span> MCHBAR32(0xf50) = 0xfc00f000;</span><br><span> MCHBAR32(0xf54) = 0xc0008000;</span><br><span style="color: hsl(0, 100%, 40%);">- MCHBAR32(0xf6c) = (MCHBAR32(0xf6c) & ~0xffff0000) | 0xffff0000;</span><br><span style="color: hsl(0, 100%, 40%);">- MCHBAR32(0xfac) = MCHBAR32(0xfac) & ~0x80000000;</span><br><span style="color: hsl(0, 100%, 40%);">- MCHBAR32(0xfb8) = MCHBAR32(0xfb8) & ~0xff000000;</span><br><span style="color: hsl(0, 100%, 40%);">- MCHBAR32(0xfbc) = (MCHBAR32(0xfbc) & ~0x7f800) | 0xf000;</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32_AND_OR(0xf6c, ~0xffff0000, 0xffff0000);</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32_AND(0xfac, ~0x80000000);</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32_AND(0xfb8, ~0xff000000);</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32_AND_OR(0xfbc, ~0x7f800, 0xf000);</span><br><span> MCHBAR32(0x1104) = 0x3003232;</span><br><span> MCHBAR32(0x1108) = 0x74;</span><br><span> if (s->selected_timings.fsb_clk == FSB_CLOCK_800MHz)</span><br><span>@@ -2010,31 +2012,31 @@</span><br><span> FOR_EACH_POPULATED_CHANNEL(s->dimms, ch) {</span><br><span> MCHBAR8(0x400*ch + 0x239) = twl + 15;</span><br><span> MCHBAR16(0x400*ch + 0x23c) = x23c;</span><br><span style="color: hsl(0, 100%, 40%);">- MCHBAR32(0x400*ch + 0x248) = (MCHBAR32(0x400*ch + 0x248) & ~0x706033) | 0x406033;</span><br><span style="color: hsl(0, 100%, 40%);">- MCHBAR32(0x400*ch + 0x260) = (MCHBAR32(0x400*ch + 0x260) & ~(1 << 16)) | (1 << 16);</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32_AND_OR(0x400*ch + 0x248, ~0x706033, 0x406033);</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32_AND_OR(0x400*ch + 0x260, ~(1 << 16), 1 << 16);</span><br><span> MCHBAR8(0x400*ch + 0x264) = x264;</span><br><span style="color: hsl(0, 100%, 40%);">- MCHBAR8(0x400*ch + 0x592) = (MCHBAR8(0x400*ch + 0x592) & ~0x3f) | (0x3c & x592);</span><br><span style="color: hsl(0, 100%, 40%);">- MCHBAR8(0x400*ch + 0x593) = (MCHBAR8(0x400*ch + 0x593) & ~0x1f) | 0x1e;</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR8_AND_OR(0x400*ch + 0x592, ~0x3f, 0x3c & x592);</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR8_AND_OR(0x400*ch + 0x593, ~0x1f, 0x1e);</span><br><span> }</span><br><span> </span><br><span> for (lane = 0; lane < 8; lane++)</span><br><span style="color: hsl(0, 100%, 40%);">- MCHBAR8(0x561 + (lane << 2)) = MCHBAR8(0x561 + (lane << 2)) & ~(1 << 3);</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR8_AND(0x561 + (lane << 2), ~(1 << 3));</span><br><span> }</span><br><span> </span><br><span> static void software_ddr3_reset(struct sysinfo *s)</span><br><span> {</span><br><span> printk(BIOS_DEBUG, "Software initiated DDR3 reset.\n");</span><br><span style="color: hsl(0, 100%, 40%);">- MCHBAR8(0x1a8) = MCHBAR8(0x1a8) | 0x02;</span><br><span style="color: hsl(0, 100%, 40%);">- MCHBAR8(0x5da) = MCHBAR8(0x5da) & ~0x80;</span><br><span style="color: hsl(0, 100%, 40%);">- MCHBAR8(0x1a8) = MCHBAR8(0x1a8) & ~0x02;</span><br><span style="color: hsl(0, 100%, 40%);">- MCHBAR8(0x5da) = (MCHBAR8(0x5da) & ~0x03) | 1;</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR8_OR(0x1a8, 0x02);</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR8_AND(0x5da, ~0x80);</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR8_AND(0x1a8, ~0x02);</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR8_AND_OR(0x5da, ~0x03, 1);</span><br><span> udelay(200);</span><br><span style="color: hsl(0, 100%, 40%);">- MCHBAR8(0x1a8) = MCHBAR8(0x1a8) & ~0x02;</span><br><span style="color: hsl(0, 100%, 40%);">- MCHBAR8(0x5da) = MCHBAR8(0x5da) | 0x80;</span><br><span style="color: hsl(0, 100%, 40%);">- MCHBAR8(0x5da) = MCHBAR8(0x5da) & ~0x80;</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR8_AND(0x1a8, ~0x02);</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR8_OR(0x5da, 0x80);</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR8_AND(0x5da, ~0x80);</span><br><span> udelay(500);</span><br><span style="color: hsl(0, 100%, 40%);">- MCHBAR8(0x5da) = MCHBAR8(0x5da) | 0x03;</span><br><span style="color: hsl(0, 100%, 40%);">- MCHBAR8(0x5da) = MCHBAR8(0x5da) & ~0x03;</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR8_OR(0x5da, 0x03);</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR8_AND(0x5da, ~0x03);</span><br><span> /* After write leveling the dram needs to be reset and reinitialised */</span><br><span> jedec_ddr3(s);</span><br><span> }</span><br><span>@@ -2051,17 +2053,17 @@</span><br><span> | PMSTS_BOTH_SELFREFRESH;</span><br><span> </span><br><span> // Clear host clk gate reg</span><br><span style="color: hsl(0, 100%, 40%);">- MCHBAR32(0x1c) = MCHBAR32(0x1c) | 0xffffffff;</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32_OR(0x1c, 0xffffffff);</span><br><span> </span><br><span> // Select type</span><br><span> if (s->spd_type == DDR2)</span><br><span style="color: hsl(0, 100%, 40%);">- MCHBAR8(0x1a8) = MCHBAR8(0x1a8) & ~0x4;</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR8_AND(0x1a8, ~0x4);</span><br><span> else</span><br><span style="color: hsl(0, 100%, 40%);">- MCHBAR8(0x1a8) = MCHBAR8(0x1a8) | 0x4;</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR8_OR(0x1a8, 0x4);</span><br><span> </span><br><span> // Set freq</span><br><span style="color: hsl(0, 100%, 40%);">- MCHBAR32(0xc00) = (MCHBAR32(0xc00) & ~0x70) |</span><br><span style="color: hsl(0, 100%, 40%);">- (s->selected_timings.mem_clk << 4) | (1 << 10);</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32_AND_OR(0xc00, ~0x70,</span><br><span style="color: hsl(120, 100%, 40%);">+ (s->selected_timings.mem_clk << 4) | (1 << 10));</span><br><span> </span><br><span> // Overwrite freq if chipset rejects it</span><br><span> s->selected_timings.mem_clk = (MCHBAR8(0xc00) & 0x70) >> 4;</span><br><span>@@ -2104,7 +2106,7 @@</span><br><span> </span><br><span> // RCOMP update</span><br><span> if (s->boot_path != BOOT_PATH_WARM_RESET) {</span><br><span style="color: hsl(0, 100%, 40%);">- while ((MCHBAR8(0x130) & 1) != 0)</span><br><span style="color: hsl(120, 100%, 40%);">+ while (MCHBAR8(0x130) & 1)</span><br><span> ;</span><br><span> printk(BIOS_DEBUG, "Done RCOMP update\n");</span><br><span> }</span><br><span>@@ -2113,36 +2115,36 @@</span><br><span> </span><br><span> // IOBUFACT</span><br><span> if (CHANNEL_IS_POPULATED(s->dimms, 0)) {</span><br><span style="color: hsl(0, 100%, 40%);">- MCHBAR8(0x5dd) = (MCHBAR8(0x5dd) & ~0x3f) | 0x3f;</span><br><span style="color: hsl(0, 100%, 40%);">- MCHBAR8(0x5d8) = MCHBAR8(0x5d8) | 0x7;</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR8_AND_OR(0x5dd, ~0x3f, 0x3f);</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR8_OR(0x5d8, 0x7);</span><br><span> }</span><br><span> if (CHANNEL_IS_POPULATED(s->dimms, 1)) {</span><br><span> if (pci_read_config8(PCI_DEV(0, 0, 0), 0x8) < 2) {</span><br><span style="color: hsl(0, 100%, 40%);">- MCHBAR8(0x5dd) = (MCHBAR8(0x5dd) & ~0x3f) | 0x3f;</span><br><span style="color: hsl(0, 100%, 40%);">- MCHBAR8(0x5d8) = MCHBAR8(0x5d8) | 1;</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR8_AND_OR(0x5dd, ~0x3f, 0x3f);</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR8_OR(0x5d8, 1);</span><br><span> }</span><br><span style="color: hsl(0, 100%, 40%);">- MCHBAR8(0x9dd) = (MCHBAR8(0x9dd) & ~0x3f) | 0x3f;</span><br><span style="color: hsl(0, 100%, 40%);">- MCHBAR8(0x9d8) = MCHBAR8(0x9d8) | 0x7;</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR8_OR(0x9dd, 0x3f);</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR8_OR(0x9d8, 0x7);</span><br><span> }</span><br><span> </span><br><span> /* DDR3 reset */</span><br><span> if ((s->spd_type == DDR3) && (s->boot_path != BOOT_PATH_RESUME)) {</span><br><span> printk(BIOS_DEBUG, "DDR3 Reset.\n");</span><br><span style="color: hsl(0, 100%, 40%);">- MCHBAR8(0x1a8) = MCHBAR8(0x1a8) & ~0x2;</span><br><span style="color: hsl(0, 100%, 40%);">- MCHBAR8(0x5da) = MCHBAR8(0x5da) | 0x80;</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR8_AND(0x1a8, ~0x2);</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR8_OR(0x5da, 0x80);</span><br><span> udelay(500);</span><br><span style="color: hsl(0, 100%, 40%);">- MCHBAR8(0x1a8) = MCHBAR8(0x1a8) & ~0x2;</span><br><span style="color: hsl(0, 100%, 40%);">- MCHBAR8(0x5da) = MCHBAR8(0x5da) & ~0x80;</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR8_AND(0x1a8, ~0x2);</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR8_AND(0x5da, ~0x80);</span><br><span> udelay(500);</span><br><span> }</span><br><span> </span><br><span> // Pre jedec</span><br><span style="color: hsl(0, 100%, 40%);">- MCHBAR8(0x40) = MCHBAR8(0x40) | 0x2;</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR8_OR(0x40, 0x2);</span><br><span> FOR_EACH_POPULATED_CHANNEL(s->dimms, ch) {</span><br><span style="color: hsl(0, 100%, 40%);">- MCHBAR32(0x400*ch + 0x260) = MCHBAR32(0x400*ch + 0x260) | (1 << 27);</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32_OR(0x400*ch + 0x260, 1 << 27);</span><br><span> }</span><br><span style="color: hsl(0, 100%, 40%);">- MCHBAR16(0x212) = (MCHBAR16(0x212) & ~0xf000) | 0xf000;</span><br><span style="color: hsl(0, 100%, 40%);">- MCHBAR16(0x212) = (MCHBAR16(0x212) & ~0xf00) | 0xf00;</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR16_OR(0x212, 0xf000);</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR16_OR(0x212, 0xf00);</span><br><span> printk(BIOS_DEBUG, "Done pre-jedec\n");</span><br><span> </span><br><span> // JEDEC reset</span><br><span>@@ -2163,7 +2165,7 @@</span><br><span> }</span><br><span> </span><br><span> // After JEDEC reset</span><br><span style="color: hsl(0, 100%, 40%);">- MCHBAR8(0x40) = MCHBAR8(0x40) & ~0x2;</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR8_AND(0x40, ~0x2);</span><br><span> FOR_EACH_POPULATED_CHANNEL(s->dimms, ch) {</span><br><span> reg32 = (2 << 18);</span><br><span> reg32 |= post_jedec_tab[s->selected_timings.fsb_clk]</span><br><span>@@ -2180,23 +2182,23 @@</span><br><span> [s->selected_timings.mem_clk - MEM_CLOCK_667MHz][1]</span><br><span> << 8;</span><br><span> }</span><br><span style="color: hsl(0, 100%, 40%);">- MCHBAR32(0x400*ch + 0x274) = (MCHBAR32(0x400*ch + 0x274) & ~0xfff00) | reg32;</span><br><span style="color: hsl(0, 100%, 40%);">- MCHBAR8(0x400*ch + 0x274) = MCHBAR8(0x400*ch + 0x274) & ~0x80;</span><br><span style="color: hsl(0, 100%, 40%);">- MCHBAR8(0x400*ch + 0x26c) = MCHBAR8(0x400*ch + 0x26c) | 1;</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32_AND_OR(0x400*ch + 0x274, ~0xfff00, reg32);</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR8_AND(0x400*ch + 0x274, ~0x80);</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR8_OR(0x400*ch + 0x26c, 1);</span><br><span> MCHBAR32(0x400*ch + 0x278) = 0x88141881;</span><br><span> MCHBAR16(0x400*ch + 0x27c) = 0x41;</span><br><span> MCHBAR8(0x400*ch + 0x292) = 0xf2;</span><br><span style="color: hsl(0, 100%, 40%);">- MCHBAR8(0x400*ch + 0x271) = (MCHBAR8(0x400*ch + 0x271) & ~0xe) | 0xe;</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR8_OR(0x400*ch + 0x271, 0xe);</span><br><span> }</span><br><span style="color: hsl(0, 100%, 40%);">- MCHBAR8(0x2c4) = MCHBAR8(0x2c4) | 0x8;</span><br><span style="color: hsl(0, 100%, 40%);">- MCHBAR8(0x2c3) = MCHBAR8(0x2c3) | 0x40;</span><br><span style="color: hsl(0, 100%, 40%);">- MCHBAR8(0x2c4) = MCHBAR8(0x2c4) | 0x4;</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR8_OR(0x2c4, 0x8);</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR8_OR(0x2c3, 0x40);</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR8_OR(0x2c4, 0x4);</span><br><span> </span><br><span> printk(BIOS_DEBUG, "Done post-jedec\n");</span><br><span> </span><br><span> // Set DDR init complete</span><br><span> FOR_EACH_POPULATED_CHANNEL(s->dimms, ch) {</span><br><span style="color: hsl(0, 100%, 40%);">- MCHBAR32(0x400*ch + 0x268) = (MCHBAR32(0x400*ch + 0x268) & ~0xc0000000) | 0xc0000000;</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32_OR(0x400*ch + 0x268, 0xc0000000);</span><br><span> }</span><br><span> </span><br><span> // Receive enable</span><br><span>@@ -2205,14 +2207,14 @@</span><br><span> </span><br><span> // Finish rcven</span><br><span> FOR_EACH_CHANNEL(ch) {</span><br><span style="color: hsl(0, 100%, 40%);">- MCHBAR8(0x400*ch + 0x5d8) = MCHBAR8(0x400*ch + 0x5d8) & ~0xe;</span><br><span style="color: hsl(0, 100%, 40%);">- MCHBAR8(0x400*ch + 0x5d8) = MCHBAR8(0x400*ch + 0x5d8) | 0x2;</span><br><span style="color: hsl(0, 100%, 40%);">- MCHBAR8(0x400*ch + 0x5d8) = MCHBAR8(0x400*ch + 0x5d8) | 0x4;</span><br><span style="color: hsl(0, 100%, 40%);">- MCHBAR8(0x400*ch + 0x5d8) = MCHBAR8(0x400*ch + 0x5d8) | 0x8;</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR8_AND(0x400*ch + 0x5d8, ~0xe);</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR8_OR(0x400*ch + 0x5d8, 0x2);</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR8_OR(0x400*ch + 0x5d8, 0x4);</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR8_OR(0x400*ch + 0x5d8, 0x8);</span><br><span> }</span><br><span style="color: hsl(0, 100%, 40%);">- MCHBAR8(0x5dc) = MCHBAR8(0x5dc) | 0x80;</span><br><span style="color: hsl(0, 100%, 40%);">- MCHBAR8(0x5dc) = MCHBAR8(0x5dc) & ~0x80;</span><br><span style="color: hsl(0, 100%, 40%);">- MCHBAR8(0x5dc) = MCHBAR8(0x5dc) | 0x80;</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR8_OR(0x5dc, 0x80);</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR8_AND(0x5dc, ~0x80);</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR8_OR(0x5dc, 0x80);</span><br><span> </span><br><span> // Dummy writes / reads</span><br><span> if (s->boot_path == BOOT_PATH_NORMAL) {</span><br><span>@@ -2260,9 +2262,9 @@</span><br><span> printk(BIOS_DEBUG, "Done enhanced mode\n");</span><br><span> </span><br><span> // Periodic RCOMP</span><br><span style="color: hsl(0, 100%, 40%);">- MCHBAR16(0x160) = (MCHBAR16(0x160) & ~0xfff) | 0x999;</span><br><span style="color: hsl(0, 100%, 40%);">- MCHBAR16(0x1b4) = MCHBAR16(0x1b4) | 0x3000;</span><br><span style="color: hsl(0, 100%, 40%);">- MCHBAR8(0x130) = MCHBAR8(0x130) | 0x82;</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR16_AND_OR(0x160, ~0xfff, 0x999);</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR16_OR(0x1b4, 0x3000);</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR8_OR(0x130, 0x82);</span><br><span> printk(BIOS_DEBUG, "Done PRCOMP\n");</span><br><span> </span><br><span> // Power settings</span><br><span>@@ -2277,11 +2279,11 @@</span><br><span> if (ME_UMA_SIZEMB != 0) {</span><br><span> if (RANK_IS_POPULATED(s->dimms, 0, 0)</span><br><span> || RANK_IS_POPULATED(s->dimms, 1, 0))</span><br><span style="color: hsl(0, 100%, 40%);">- MCHBAR8(0xa2f) = MCHBAR8(0xa2f) | (1 << 0);</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR8_OR(0xa2f, 1 << 0);</span><br><span> if (RANK_IS_POPULATED(s->dimms, 0, 1)</span><br><span> || RANK_IS_POPULATED(s->dimms, 1, 1))</span><br><span style="color: hsl(0, 100%, 40%);">- MCHBAR8(0xa2f) = MCHBAR8(0xa2f) | (1 << 1);</span><br><span style="color: hsl(0, 100%, 40%);">- MCHBAR32(0xa30) = MCHBAR32(0xa30) | (1 << 26);</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR8_OR(0xa2f, 1 << 1);</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32_OR(0xa30, 1 << 26);</span><br><span> }</span><br><span> </span><br><span> printk(BIOS_DEBUG, "Done raminit\n");</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/27717">change 27717</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/27717"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I057abe314622e92000c7e4ff2faa4595edb5244b </div>
<div style="display:none"> Gerrit-Change-Number: 27717 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Felix Held <felix-coreboot@felixheld.de> </div>