<p>Felix Held has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/27706">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">nehalem/raminit: remove REAL define and most dead code<br><br>The code only compiled when REAL was set to 1; the other case included an<br>unpublished include.<br><br>Change-Id: I7f31e9cd02f45492d6c9e88ec6164a537ca5e3c2<br>Signed-off-by: Felix Held <felix-coreboot@felixheld.de><br>---<br>M src/northbridge/intel/nehalem/raminit.c<br>1 file changed, 7 insertions(+), 79 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/27706/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/northbridge/intel/nehalem/raminit.c b/src/northbridge/intel/nehalem/raminit.c</span><br><span>index dcf9b7b..8c4d50e 100644</span><br><span>--- a/src/northbridge/intel/nehalem/raminit.c</span><br><span>+++ b/src/northbridge/intel/nehalem/raminit.c</span><br><span>@@ -14,13 +14,6 @@</span><br><span> * GNU General Public License for more details.</span><br><span> */</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-/* Please don't remove this. It's needed for debugging and reverse</span><br><span style="color: hsl(0, 100%, 40%);">- * engineering more nehalem variants in the future. */</span><br><span style="color: hsl(0, 100%, 40%);">-#ifndef REAL</span><br><span style="color: hsl(0, 100%, 40%);">-#define REAL 1</span><br><span style="color: hsl(0, 100%, 40%);">-#endif</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#if REAL</span><br><span> #include <stdlib.h></span><br><span> #include <compiler.h></span><br><span> #include <console/console.h></span><br><span>@@ -45,22 +38,11 @@</span><br><span> #include <cpu/intel/turbo.h></span><br><span> #include <mrc_cache.h></span><br><span> #include <arch/early_variables.h></span><br><span style="color: hsl(0, 100%, 40%);">-#endif</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#if !REAL</span><br><span style="color: hsl(0, 100%, 40%);">-typedef unsigned char u8;</span><br><span style="color: hsl(0, 100%, 40%);">-typedef unsigned short u16;</span><br><span style="color: hsl(0, 100%, 40%);">-typedef unsigned int u32;</span><br><span style="color: hsl(0, 100%, 40%);">-typedef u32 device_t;</span><br><span style="color: hsl(0, 100%, 40%);">-#endif</span><br><span> </span><br><span> #include "nehalem.h"</span><br><span> </span><br><span> #include <southbridge/intel/ibexpeak/me.h></span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#if REAL</span><br><span> #include <delay.h></span><br><span style="color: hsl(0, 100%, 40%);">-#endif</span><br><span> </span><br><span> #define NORTHBRIDGE PCI_DEV(0, 0, 0)</span><br><span> #define SOUTHBRIDGE PCI_DEV(0, 0x1f, 0)</span><br><span>@@ -112,10 +94,6 @@</span><br><span> u32 reg_6e8;</span><br><span> };</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-#if !REAL</span><br><span style="color: hsl(0, 100%, 40%);">-#include "raminit_fake.c"</span><br><span style="color: hsl(0, 100%, 40%);">-#else</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span> #include <lib.h> /* Prototypes */</span><br><span> </span><br><span> static inline void write_mchbar32(u32 addr, u32 val)</span><br><span>@@ -171,8 +149,6 @@</span><br><span> out[1] = ret.hi;</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-#endif</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span> /* OK */</span><br><span> static void write_1d0(u32 val, u16 addr, int bits, int flag)</span><br><span> {</span><br><span>@@ -215,9 +191,7 @@</span><br><span> </span><br><span> static void sfence(void)</span><br><span> {</span><br><span style="color: hsl(0, 100%, 40%);">-#if REAL</span><br><span> asm volatile ("sfence");</span><br><span style="color: hsl(0, 100%, 40%);">-#endif</span><br><span> }</span><br><span> </span><br><span> static inline u16 get_lane_offset(int slot, int rank, int lane)</span><br><span>@@ -232,7 +206,6 @@</span><br><span> return get_lane_offset(slot, rank, lane) + offs[(tm + 3) % 4];</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-#if REAL</span><br><span> static u32 gav_real(int line, u32 in)</span><br><span> {</span><br><span> // printk (BIOS_DEBUG, "%d: GAV: %x\n", line, in);</span><br><span>@@ -240,7 +213,7 @@</span><br><span> }</span><br><span> </span><br><span> #define gav(x) gav_real (__LINE__, (x))</span><br><span style="color: hsl(0, 100%, 40%);">-#endif</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> struct raminfo {</span><br><span> u16 clock_speed_index; /* clock_speed (REAL, not DDR) / 133.(3) - 3 */</span><br><span> u16 fsb_frequency; /* in 1.(1)/2 MHz. */</span><br><span>@@ -1497,7 +1470,6 @@</span><br><span> </span><br><span> memset(memory_map, 0, sizeof(memory_map));</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-#if REAL</span><br><span> if (info->uma_enabled) {</span><br><span> u16 t = pci_read_config16(NORTHBRIDGE, D0F0_GGC);</span><br><span> gav(t);</span><br><span>@@ -1512,7 +1484,6 @@</span><br><span> uma_size_igd = uma_sizes_igd[(t >> 4) & 0xF];</span><br><span> uma_size_gtt = uma_sizes_gtt[(t >> 8) & 0xF];</span><br><span> }</span><br><span style="color: hsl(0, 100%, 40%);">-#endif</span><br><span> </span><br><span> mmio_size = get_mmio_size();</span><br><span> </span><br><span>@@ -1543,7 +1514,7 @@</span><br><span> if (memory_remap)</span><br><span> TOUUD -= quickpath_reserved;</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-#if !REAL</span><br><span style="color: hsl(120, 100%, 40%);">+#if 0</span><br><span> if (info->uma_enabled) {</span><br><span> u16 t = pci_read_config16(NORTHBRIDGE, D0F0_GGC);</span><br><span> gav(t);</span><br><span>@@ -1685,7 +1656,6 @@</span><br><span> </span><br><span> static void dump_timings(struct raminfo *info)</span><br><span> {</span><br><span style="color: hsl(0, 100%, 40%);">-#if REAL</span><br><span> int channel, slot, rank, lane, i;</span><br><span> printk(BIOS_DEBUG, "Timings:\n");</span><br><span> FOR_POPULATED_RANKS {</span><br><span>@@ -1710,7 +1680,6 @@</span><br><span> info->training.reg_178);</span><br><span> printk(BIOS_DEBUG, "[10b] = %x (%x)\n", read_1d0(0x10b, 6),</span><br><span> info->training.reg_10b);</span><br><span style="color: hsl(0, 100%, 40%);">-#endif</span><br><span> }</span><br><span> </span><br><span> /* Read timings and other registers that need to be restored verbatim and</span><br><span>@@ -1750,7 +1719,6 @@</span><br><span> &train, sizeof(train));</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-#if REAL</span><br><span> static const struct ram_training *get_cached_training(void)</span><br><span> {</span><br><span> struct region_device rdev;</span><br><span>@@ -1759,7 +1727,6 @@</span><br><span> return 0;</span><br><span> return (void *)rdev_mmap_full(&rdev);</span><br><span> }</span><br><span style="color: hsl(0, 100%, 40%);">-#endif</span><br><span> </span><br><span> /* FIXME: add timeout. */</span><br><span> static void wait_heci_ready(void)</span><br><span>@@ -1842,10 +1809,6 @@</span><br><span> write32(DEFAULT_HECIBAR + 0x4, read32(DEFAULT_HECIBAR + 0x4) | 2);</span><br><span> do {</span><br><span> csr.raw = read32(DEFAULT_HECIBAR + 0xc);</span><br><span style="color: hsl(0, 100%, 40%);">-#if !REAL</span><br><span style="color: hsl(0, 100%, 40%);">- if (i++ > 346)</span><br><span style="color: hsl(0, 100%, 40%);">- return -1;</span><br><span style="color: hsl(0, 100%, 40%);">-#endif</span><br><span> }</span><br><span> while (csr.csr.buffer_write_ptr == csr.csr.buffer_read_ptr);</span><br><span> *(u32 *) head = read32(DEFAULT_HECIBAR + 0x8);</span><br><span>@@ -3789,7 +3752,6 @@</span><br><span> write_mchbar8(0x2ca9, read_mchbar8(0x2ca9) & ~1);</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-#if REAL</span><br><span> static void dmi_setup(void)</span><br><span> {</span><br><span> gav(read8(DEFAULT_DMIBAR + 0x254));</span><br><span>@@ -3804,7 +3766,6 @@</span><br><span> DEFAULT_GPIOBASE | 0x38);</span><br><span> gav(inb(DEFAULT_GPIOBASE | 0xe)); // = 0xfdcaff6e</span><br><span> }</span><br><span style="color: hsl(0, 100%, 40%);">-#endif</span><br><span> </span><br><span> void chipset_init(const int s3resume)</span><br><span> {</span><br><span>@@ -3817,14 +3778,9 @@</span><br><span> printk(BIOS_DEBUG, "soft reset detected, rebooting properly\n");</span><br><span> write_mchbar8(0x2ca8, 0);</span><br><span> outb(0x6, 0xcf9);</span><br><span style="color: hsl(0, 100%, 40%);">-#if REAL</span><br><span> halt();</span><br><span style="color: hsl(0, 100%, 40%);">-#else</span><br><span style="color: hsl(0, 100%, 40%);">- printf("CP5\n");</span><br><span style="color: hsl(0, 100%, 40%);">- exit(0);</span><br><span style="color: hsl(0, 100%, 40%);">-#endif</span><br><span> }</span><br><span style="color: hsl(0, 100%, 40%);">-#if !REAL</span><br><span style="color: hsl(120, 100%, 40%);">+#if 0</span><br><span> if (!s3resume) {</span><br><span> pre_raminit_3(x2ca8);</span><br><span> }</span><br><span>@@ -3911,15 +3867,13 @@</span><br><span> /* before SPD */</span><br><span> timestamp_add_now(101);</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- if (!s3resume || REAL) {</span><br><span style="color: hsl(120, 100%, 40%);">+ if (!s3resume || 1) { // possible error</span><br><span> pci_read_config8(SOUTHBRIDGE, GEN_PMCON_2); // = 0x80</span><br><span> </span><br><span> collect_system_info(&info);</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-#if REAL</span><br><span> /* Enable SMBUS. */</span><br><span> enable_smbus();</span><br><span style="color: hsl(0, 100%, 40%);">-#endif</span><br><span> </span><br><span> memset(&info.populated_ranks, 0, sizeof(info.populated_ranks));</span><br><span> </span><br><span>@@ -4024,14 +3978,11 @@</span><br><span> timestamp_add_now(102);</span><br><span> </span><br><span> write_mchbar8(0x2ca8, read_mchbar8(0x2ca8) & 0xfc);</span><br><span style="color: hsl(0, 100%, 40%);">-#if !REAL</span><br><span style="color: hsl(0, 100%, 40%);">- rdmsr (MTRR_PHYS_MASK (3));</span><br><span style="color: hsl(0, 100%, 40%);">-#endif</span><br><span> </span><br><span> collect_system_info(&info);</span><br><span> calculate_timings(&info);</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-#if !REAL</span><br><span style="color: hsl(120, 100%, 40%);">+#if 0</span><br><span> pci_write_config8(NORTHBRIDGE, 0xdf, 0x82);</span><br><span> #endif</span><br><span> </span><br><span>@@ -4051,14 +4002,9 @@</span><br><span> printk(BIOS_INFO,</span><br><span> "Interrupted RAM init, reset required.\n");</span><br><span> outb(0x6, 0xcf9);</span><br><span style="color: hsl(0, 100%, 40%);">-#if REAL</span><br><span> halt();</span><br><span style="color: hsl(0, 100%, 40%);">-#endif</span><br><span> }</span><br><span> }</span><br><span style="color: hsl(0, 100%, 40%);">-#if !REAL</span><br><span style="color: hsl(0, 100%, 40%);">- gav(read_mchbar8(0x2ca8)); ///!!!!</span><br><span style="color: hsl(0, 100%, 40%);">-#endif</span><br><span> </span><br><span> if (!s3resume && x2ca8 == 0)</span><br><span> pci_write_config8(SOUTHBRIDGE, GEN_PMCON_2,</span><br><span>@@ -4415,12 +4361,7 @@</span><br><span> write_mchbar8(0x2ca8, read_mchbar8(0x2ca8) & ~3);</span><br><span> write_mchbar8(0x2ca8, read_mchbar8(0x2ca8) + 4);</span><br><span> write_mchbar32(0x1af0, read_mchbar32(0x1af0) | 0x10);</span><br><span style="color: hsl(0, 100%, 40%);">-#if REAL</span><br><span> halt();</span><br><span style="color: hsl(0, 100%, 40%);">-#else</span><br><span style="color: hsl(0, 100%, 40%);">- printf("CP5\n");</span><br><span style="color: hsl(0, 100%, 40%);">- exit(0);</span><br><span style="color: hsl(0, 100%, 40%);">-#endif</span><br><span> }</span><br><span> </span><br><span> write_mchbar8(0x2ca8, read_mchbar8(0x2ca8));</span><br><span>@@ -4515,13 +4456,7 @@</span><br><span> reg32 = inl(DEFAULT_PMBASE + 0x04);</span><br><span> outl(reg32 & ~(7 << 10), DEFAULT_PMBASE + 0x04);</span><br><span> outb(0xe, 0xcf9);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#if REAL</span><br><span> halt();</span><br><span style="color: hsl(0, 100%, 40%);">-#else</span><br><span style="color: hsl(0, 100%, 40%);">- printf("CP5\n");</span><br><span style="color: hsl(0, 100%, 40%);">- exit(0);</span><br><span style="color: hsl(0, 100%, 40%);">-#endif</span><br><span> }</span><br><span> int tm;</span><br><span> info.training = *info.cached_training;</span><br><span>@@ -4781,10 +4716,6 @@</span><br><span> write_mchbar32(0xfa4, read_mchbar32(0xfa4) & ~0x01000002);</span><br><span> write_mchbar32(0xfb0, 0x2000e019);</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-#if !REAL</span><br><span style="color: hsl(0, 100%, 40%);">- printf("CP16\n");</span><br><span style="color: hsl(0, 100%, 40%);">-#endif</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span> /* Before training. */</span><br><span> timestamp_add_now(103);</span><br><span> </span><br><span>@@ -4823,10 +4754,10 @@</span><br><span> write_mchbar8(0xff4, read_mchbar8(0xff4) | 0x2); // OK</span><br><span> write_mchbar32(0xff8, (read_mchbar32(0xff8) & ~0xe008) | 0x1020); // OK</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-#if REAL</span><br><span> write_mchbar32(0xd00, IOMMU_BASE2 | 1);</span><br><span> write_mchbar32(0xd40, IOMMU_BASE1 | 1);</span><br><span> write_mchbar32(0xdc0, IOMMU_BASE4 | 1);</span><br><span style="color: hsl(120, 100%, 40%);">+#if 1</span><br><span> </span><br><span> write32p(IOMMU_BASE1 | 0xffc, 0x80000000);</span><br><span> write32p(IOMMU_BASE2 | 0xffc, 0xc0000000);</span><br><span>@@ -4963,9 +4894,8 @@</span><br><span> ax = read_mchbar16(0x1190) & 0xf00; // = 0x480a // OK</span><br><span> write_mchbar16(0x1170, ax | (read_mchbar16(0x1170) & 0x107f) | 0x4080); // OK</span><br><span> write_mchbar16(0x1170, read_mchbar16(0x1170) | 0x1000); // OK</span><br><span style="color: hsl(0, 100%, 40%);">-#if REAL</span><br><span> udelay(1000);</span><br><span style="color: hsl(0, 100%, 40%);">-#endif</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> u16 ecx;</span><br><span> for (ecx = 0xffff; ecx && (read_mchbar16(0x1170) & 0x1000); ecx--); // OK</span><br><span> write_mchbar16(0x1190, read_mchbar16(0x1190) & ~0x4000); // OK</span><br><span>@@ -4976,7 +4906,6 @@</span><br><span> udelay(10000);</span><br><span> write_mchbar16(0x2ca8, 0x8);</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-#if REAL</span><br><span> udelay(1000);</span><br><span> dump_timings(&info);</span><br><span> cbmem_wasnot_inited = cbmem_recovery(s3resume);</span><br><span>@@ -4996,5 +4925,4 @@</span><br><span> outb(0xe, 0xcf9);</span><br><span> halt();</span><br><span> }</span><br><span style="color: hsl(0, 100%, 40%);">-#endif</span><br><span> }</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/27706">change 27706</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/27706"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I7f31e9cd02f45492d6c9e88ec6164a537ca5e3c2 </div>
<div style="display:none"> Gerrit-Change-Number: 27706 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Felix Held <felix-coreboot@felixheld.de> </div>