<p>Felix Held has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/27713">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">northbridge/nehalem: clean up header file<br><br>* remove duplicate macro definitions<br>* add brackets to macros<br><br>Change-Id: I1f758203afdcb1b18f3c0d786698f9fbf2246e0e<br>Signed-off-by: Felix Held <felix-coreboot@felixheld.de><br>---<br>M src/northbridge/intel/nehalem/nehalem.h<br>1 file changed, 11 insertions(+), 38 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/27713/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/northbridge/intel/nehalem/nehalem.h b/src/northbridge/intel/nehalem/nehalem.h</span><br><span>index 20c0bbc..afb3c7d 100644</span><br><span>--- a/src/northbridge/intel/nehalem/nehalem.h</span><br><span>+++ b/src/northbridge/intel/nehalem/nehalem.h</span><br><span>@@ -102,33 +102,6 @@</span><br><span> #define D1F0_VCCAP 0x104</span><br><span> #define D1F0_VC0RCTL 0x114</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-/*</span><br><span style="color: hsl(0, 100%, 40%);">- * MCHBAR</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#define MCHBAR8(x) *((volatile u8 *)(DEFAULT_MCHBAR + x))</span><br><span style="color: hsl(0, 100%, 40%);">-#define MCHBAR16(x) *((volatile u16 *)(DEFAULT_MCHBAR + x))</span><br><span style="color: hsl(0, 100%, 40%);">-#define MCHBAR32(x) *((volatile u32 *)(DEFAULT_MCHBAR + x))</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/*</span><br><span style="color: hsl(0, 100%, 40%);">- * DMIBAR</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#define DMIBAR8(x) *((volatile u8 *)(DEFAULT_DMIBAR + x))</span><br><span style="color: hsl(0, 100%, 40%);">-#define DMIBAR16(x) *((volatile u16 *)(DEFAULT_DMIBAR + x))</span><br><span style="color: hsl(0, 100%, 40%);">-#define DMIBAR32(x) *((volatile u32 *)(DEFAULT_DMIBAR + x))</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#define DMIVC0RCTL 0x14</span><br><span style="color: hsl(0, 100%, 40%);">-#define DMIESD 0x44</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/*</span><br><span style="color: hsl(0, 100%, 40%);">- * EPBAR</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#define EPBAR8(x) *((volatile u8 *)(DEFAULT_EPBAR + x))</span><br><span style="color: hsl(0, 100%, 40%);">-#define EPBAR16(x) *((volatile u16 *)(DEFAULT_EPBAR + x))</span><br><span style="color: hsl(0, 100%, 40%);">-#define EPBAR32(x) *((volatile u32 *)(DEFAULT_EPBAR + x))</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span> /* Chipset types */</span><br><span> #define NEHALEM_MOBILE 0</span><br><span> #define NEHALEM_DESKTOP 1</span><br><span>@@ -199,10 +172,10 @@</span><br><span> * MCHBAR</span><br><span> */</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-#define MCHBAR8(x) *((volatile u8 *)(DEFAULT_MCHBAR + x))</span><br><span style="color: hsl(0, 100%, 40%);">-#define MCHBAR16(x) *((volatile u16 *)(DEFAULT_MCHBAR + x))</span><br><span style="color: hsl(0, 100%, 40%);">-#define MCHBAR32(x) *((volatile u32 *)(DEFAULT_MCHBAR + x))</span><br><span style="color: hsl(0, 100%, 40%);">-#define MCHBAR32_OR(x, or) MCHBAR32(x) = (MCHBAR32(x) | (or))</span><br><span style="color: hsl(120, 100%, 40%);">+#define MCHBAR8(x) (*((volatile u8 *)(DEFAULT_MCHBAR + (x))))</span><br><span style="color: hsl(120, 100%, 40%);">+#define MCHBAR16(x) (*((volatile u16 *)(DEFAULT_MCHBAR + (x))))</span><br><span style="color: hsl(120, 100%, 40%);">+#define MCHBAR32(x) (*((volatile u32 *)(DEFAULT_MCHBAR + (x))))</span><br><span style="color: hsl(120, 100%, 40%);">+#define MCHBAR32_OR(x, or) (MCHBAR32(x) = (MCHBAR32(x) | (or)))</span><br><span> </span><br><span> #define BIOS_RESET_CPL 0x5da8 /* 8bit */</span><br><span> </span><br><span>@@ -210,9 +183,9 @@</span><br><span> * EPBAR - Egress Port Root Complex Register Block</span><br><span> */</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-#define EPBAR8(x) *((volatile u8 *)(DEFAULT_EPBAR + x))</span><br><span style="color: hsl(0, 100%, 40%);">-#define EPBAR16(x) *((volatile u16 *)(DEFAULT_EPBAR + x))</span><br><span style="color: hsl(0, 100%, 40%);">-#define EPBAR32(x) *((volatile u32 *)(DEFAULT_EPBAR + x))</span><br><span style="color: hsl(120, 100%, 40%);">+#define EPBAR8(x) (*((volatile u8 *)(DEFAULT_EPBAR + (x))))</span><br><span style="color: hsl(120, 100%, 40%);">+#define EPBAR16(x) (*((volatile u16 *)(DEFAULT_EPBAR + (x))))</span><br><span style="color: hsl(120, 100%, 40%);">+#define EPBAR32(x) (*((volatile u32 *)(DEFAULT_EPBAR + (x))))</span><br><span> </span><br><span> #define EPPVCCAP1 0x004 /* 32bit */</span><br><span> #define EPPVCCAP2 0x008 /* 32bit */</span><br><span>@@ -241,9 +214,9 @@</span><br><span> * DMIBAR</span><br><span> */</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-#define DMIBAR8(x) *((volatile u8 *)(DEFAULT_DMIBAR + x))</span><br><span style="color: hsl(0, 100%, 40%);">-#define DMIBAR16(x) *((volatile u16 *)(DEFAULT_DMIBAR + x))</span><br><span style="color: hsl(0, 100%, 40%);">-#define DMIBAR32(x) *((volatile u32 *)(DEFAULT_DMIBAR + x))</span><br><span style="color: hsl(120, 100%, 40%);">+#define DMIBAR8(x) (*((volatile u8 *)(DEFAULT_DMIBAR + (x))))</span><br><span style="color: hsl(120, 100%, 40%);">+#define DMIBAR16(x) (*((volatile u16 *)(DEFAULT_DMIBAR + (x))))</span><br><span style="color: hsl(120, 100%, 40%);">+#define DMIBAR32(x) (*((volatile u32 *)(DEFAULT_DMIBAR + (x))))</span><br><span> </span><br><span> #define DMIVCECH 0x000 /* 32bit */</span><br><span> #define DMIPVCCAP1 0x004 /* 32bit */</span><br><span>@@ -252,7 +225,7 @@</span><br><span> #define DMIPVCCCTL 0x00c /* 16bit */</span><br><span> </span><br><span> #define DMIVC0RCAP 0x010 /* 32bit */</span><br><span style="color: hsl(0, 100%, 40%);">-#define DMIVC0RCTL0 0x014 /* 32bit */</span><br><span style="color: hsl(120, 100%, 40%);">+#define DMIVC0RCTL 0x014 /* 32bit */</span><br><span> #define DMIVC0RSTS 0x01a /* 16bit */</span><br><span> </span><br><span> #define DMIVC1RCAP 0x01c /* 32bit */</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/27713">change 27713</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/27713"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I1f758203afdcb1b18f3c0d786698f9fbf2246e0e </div>
<div style="display:none"> Gerrit-Change-Number: 27713 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Felix Held <felix-coreboot@felixheld.de> </div>