<p>Felix Held <strong>merged</strong> this change.</p><p><a href="https://review.coreboot.org/27667">View Change</a></p><div style="white-space:pre-wrap">Approvals:
build bot (Jenkins): Verified
Felix Held: Looks good to me, approved
</div><pre style="font-family: monospace,monospace; white-space: pre-wrap;">nb/intel/sandybridge/report_platform: Move remaining code to sb folder<br><br>Change-Id: I2ced3f2bb9d1d150341a57ff333ca14c897c4fa3<br>Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com><br>Reviewed-on: https://review.coreboot.org/27667<br>Tested-by: build bot (Jenkins) <no-reply@coreboot.org><br>Reviewed-by: Felix Held <felix-coreboot@felixheld.de><br>---<br>M src/northbridge/intel/sandybridge/Makefile.inc<br>M src/northbridge/intel/sandybridge/raminit.c<br>D src/northbridge/intel/sandybridge/report_platform.c<br>M src/northbridge/intel/sandybridge/sandybridge.h<br>M src/southbridge/intel/bd82x6x/lpc.c<br>5 files changed, 71 insertions(+), 95 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/northbridge/intel/sandybridge/Makefile.inc b/src/northbridge/intel/sandybridge/Makefile.inc</span><br><span>index 9673cd1..304ea30 100644</span><br><span>--- a/src/northbridge/intel/sandybridge/Makefile.inc</span><br><span>+++ b/src/northbridge/intel/sandybridge/Makefile.inc</span><br><span>@@ -46,7 +46,6 @@</span><br><span> romstage-y += romstage.c</span><br><span> romstage-y += iommu.c</span><br><span> romstage-y += early_init.c</span><br><span style="color: hsl(0, 100%, 40%);">-romstage-y += report_platform.c</span><br><span> romstage-y += ../../../arch/x86/walkcbfs.S</span><br><span> </span><br><span> smm-$(CONFIG_HAVE_SMI_HANDLER) += finalize.c</span><br><span>diff --git a/src/northbridge/intel/sandybridge/raminit.c b/src/northbridge/intel/sandybridge/raminit.c</span><br><span>index c0f9c6f..47474ee 100644</span><br><span>--- a/src/northbridge/intel/sandybridge/raminit.c</span><br><span>+++ b/src/northbridge/intel/sandybridge/raminit.c</span><br><span>@@ -323,8 +323,6 @@</span><br><span> </span><br><span> MCHBAR32(0x5f00) |= 1;</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- report_platform_info();</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span> /* Wait for ME to be ready */</span><br><span> intel_early_me_init();</span><br><span> me_uma_size = intel_early_me_uma_size();</span><br><span>diff --git a/src/northbridge/intel/sandybridge/report_platform.c b/src/northbridge/intel/sandybridge/report_platform.c</span><br><span>deleted file mode 100644</span><br><span>index 7e647d8..0000000</span><br><span>--- a/src/northbridge/intel/sandybridge/report_platform.c</span><br><span>+++ /dev/null</span><br><span>@@ -1,91 +0,0 @@</span><br><span style="color: hsl(0, 100%, 40%);">-/*</span><br><span style="color: hsl(0, 100%, 40%);">- * This file is part of the coreboot project.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * Copyright (C) 2012 Google Inc.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(0, 100%, 40%);">- * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(0, 100%, 40%);">- * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(0, 100%, 40%);">- * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(0, 100%, 40%);">- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(0, 100%, 40%);">- * GNU General Public License for more details.</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#include <console/console.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <southbridge/intel/bd82x6x/pch.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include "sandybridge.h"</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-static struct {</span><br><span style="color: hsl(0, 100%, 40%);">- u16 dev_id;</span><br><span style="color: hsl(0, 100%, 40%);">- const char *dev_name;</span><br><span style="color: hsl(0, 100%, 40%);">-} pch_table [] = {</span><br><span style="color: hsl(0, 100%, 40%);">- /* 6-series PCI ids from</span><br><span style="color: hsl(0, 100%, 40%);">- * Intel® 6 Series Chipset and</span><br><span style="color: hsl(0, 100%, 40%);">- * Intel® C200 Series Chipset</span><br><span style="color: hsl(0, 100%, 40%);">- * Specification Update - NDA</span><br><span style="color: hsl(0, 100%, 40%);">- * October 2013</span><br><span style="color: hsl(0, 100%, 40%);">- * CDI / IBP#: 440377</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">- {0x1C41, "SFF Sample"},</span><br><span style="color: hsl(0, 100%, 40%);">- {0x1C42, "Desktop Sample"},</span><br><span style="color: hsl(0, 100%, 40%);">- {0x1C43, "Mobile Sample"},</span><br><span style="color: hsl(0, 100%, 40%);">- {0x1C44, "Z68"},</span><br><span style="color: hsl(0, 100%, 40%);">- {0x1C46, "P67"},</span><br><span style="color: hsl(0, 100%, 40%);">- {0x1C47, "UM67"},</span><br><span style="color: hsl(0, 100%, 40%);">- {0x1C49, "HM65"},</span><br><span style="color: hsl(0, 100%, 40%);">- {0x1C4A, "H67"},</span><br><span style="color: hsl(0, 100%, 40%);">- {0x1C4B, "HM67"},</span><br><span style="color: hsl(0, 100%, 40%);">- {0x1C4C, "Q65"},</span><br><span style="color: hsl(0, 100%, 40%);">- {0x1C4D, "QS67"},</span><br><span style="color: hsl(0, 100%, 40%);">- {0x1C4E, "Q67"},</span><br><span style="color: hsl(0, 100%, 40%);">- {0x1C4F, "QM67"},</span><br><span style="color: hsl(0, 100%, 40%);">- {0x1C50, "B65"},</span><br><span style="color: hsl(0, 100%, 40%);">- {0x1C52, "C202"},</span><br><span style="color: hsl(0, 100%, 40%);">- {0x1C54, "C204"},</span><br><span style="color: hsl(0, 100%, 40%);">- {0x1C56, "C206"},</span><br><span style="color: hsl(0, 100%, 40%);">- {0x1C5C, "H61"},</span><br><span style="color: hsl(0, 100%, 40%);">- /* 7-series PCI ids from Intel document 472178 */</span><br><span style="color: hsl(0, 100%, 40%);">- {0x1E41, "Desktop Sample"},</span><br><span style="color: hsl(0, 100%, 40%);">- {0x1E42, "Mobile Sample"},</span><br><span style="color: hsl(0, 100%, 40%);">- {0x1E43, "SFF Sample"},</span><br><span style="color: hsl(0, 100%, 40%);">- {0x1E44, "Z77"},</span><br><span style="color: hsl(0, 100%, 40%);">- {0x1E45, "H71"},</span><br><span style="color: hsl(0, 100%, 40%);">- {0x1E46, "Z75"},</span><br><span style="color: hsl(0, 100%, 40%);">- {0x1E47, "Q77"},</span><br><span style="color: hsl(0, 100%, 40%);">- {0x1E48, "Q75"},</span><br><span style="color: hsl(0, 100%, 40%);">- {0x1E49, "B75"},</span><br><span style="color: hsl(0, 100%, 40%);">- {0x1E4A, "H77"},</span><br><span style="color: hsl(0, 100%, 40%);">- {0x1E53, "C216"},</span><br><span style="color: hsl(0, 100%, 40%);">- {0x1E55, "QM77"},</span><br><span style="color: hsl(0, 100%, 40%);">- {0x1E56, "QS77"},</span><br><span style="color: hsl(0, 100%, 40%);">- {0x1E58, "UM77"},</span><br><span style="color: hsl(0, 100%, 40%);">- {0x1E57, "HM77"},</span><br><span style="color: hsl(0, 100%, 40%);">- {0x1E59, "HM76"},</span><br><span style="color: hsl(0, 100%, 40%);">- {0x1E5D, "HM75"},</span><br><span style="color: hsl(0, 100%, 40%);">- {0x1E5E, "HM70"},</span><br><span style="color: hsl(0, 100%, 40%);">- {0x1E5F, "NM70"},</span><br><span style="color: hsl(0, 100%, 40%);">-};</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-static void report_pch_info(void)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- int i;</span><br><span style="color: hsl(0, 100%, 40%);">- u16 dev_id = pci_read_config16(PCH_LPC_DEV, 2);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- const char *pch_type = "Unknown";</span><br><span style="color: hsl(0, 100%, 40%);">- for (i = 0; i < ARRAY_SIZE(pch_table); i++) {</span><br><span style="color: hsl(0, 100%, 40%);">- if (pch_table[i].dev_id == dev_id) {</span><br><span style="color: hsl(0, 100%, 40%);">- pch_type = pch_table[i].dev_name;</span><br><span style="color: hsl(0, 100%, 40%);">- break;</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">- printk (BIOS_DEBUG, "PCH type: %s, device id: %x, rev id %x\n",</span><br><span style="color: hsl(0, 100%, 40%);">- pch_type, dev_id, pci_read_config8(PCH_LPC_DEV, 8));</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-void report_platform_info(void)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- report_pch_info();</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span>diff --git a/src/northbridge/intel/sandybridge/sandybridge.h b/src/northbridge/intel/sandybridge/sandybridge.h</span><br><span>index 3269605..693bfb7 100644</span><br><span>--- a/src/northbridge/intel/sandybridge/sandybridge.h</span><br><span>+++ b/src/northbridge/intel/sandybridge/sandybridge.h</span><br><span>@@ -217,7 +217,6 @@</span><br><span> void dump_pci_devices(void);</span><br><span> void dump_spd_registers(void);</span><br><span> void dump_mem(unsigned start, unsigned end);</span><br><span style="color: hsl(0, 100%, 40%);">-void report_platform_info(void);</span><br><span> </span><br><span> #endif /* !__SMM__ */</span><br><span> </span><br><span>diff --git a/src/southbridge/intel/bd82x6x/lpc.c b/src/southbridge/intel/bd82x6x/lpc.c</span><br><span>index 611b08f..d9e72b4 100644</span><br><span>--- a/src/southbridge/intel/bd82x6x/lpc.c</span><br><span>+++ b/src/southbridge/intel/bd82x6x/lpc.c</span><br><span>@@ -19,6 +19,7 @@</span><br><span> #include <device/pci.h></span><br><span> #include <device/pci_ids.h></span><br><span> #include <device/pci_ops.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <device/pci_def.h></span><br><span> #include <pc80/mc146818rtc.h></span><br><span> #include <pc80/isa-dma.h></span><br><span> #include <pc80/i8259.h></span><br><span>@@ -500,10 +501,80 @@</span><br><span> RCBA32_OR(0x3800 + 0xc4, 1 << 23); /* lock both UVSCC + LVSCC */</span><br><span> }</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+static const struct {</span><br><span style="color: hsl(120, 100%, 40%);">+ u16 dev_id;</span><br><span style="color: hsl(120, 100%, 40%);">+ const char *dev_name;</span><br><span style="color: hsl(120, 100%, 40%);">+} pch_table[] = {</span><br><span style="color: hsl(120, 100%, 40%);">+ /* 6-series PCI ids from</span><br><span style="color: hsl(120, 100%, 40%);">+ * Intel® 6 Series Chipset and</span><br><span style="color: hsl(120, 100%, 40%);">+ * Intel® C200 Series Chipset</span><br><span style="color: hsl(120, 100%, 40%);">+ * Specification Update - NDA</span><br><span style="color: hsl(120, 100%, 40%);">+ * October 2013</span><br><span style="color: hsl(120, 100%, 40%);">+ * CDI / IBP#: 440377</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+ {0x1C41, "SFF Sample"},</span><br><span style="color: hsl(120, 100%, 40%);">+ {0x1C42, "Desktop Sample"},</span><br><span style="color: hsl(120, 100%, 40%);">+ {0x1C43, "Mobile Sample"},</span><br><span style="color: hsl(120, 100%, 40%);">+ {0x1C44, "Z68"},</span><br><span style="color: hsl(120, 100%, 40%);">+ {0x1C46, "P67"},</span><br><span style="color: hsl(120, 100%, 40%);">+ {0x1C47, "UM67"},</span><br><span style="color: hsl(120, 100%, 40%);">+ {0x1C49, "HM65"},</span><br><span style="color: hsl(120, 100%, 40%);">+ {0x1C4A, "H67"},</span><br><span style="color: hsl(120, 100%, 40%);">+ {0x1C4B, "HM67"},</span><br><span style="color: hsl(120, 100%, 40%);">+ {0x1C4C, "Q65"},</span><br><span style="color: hsl(120, 100%, 40%);">+ {0x1C4D, "QS67"},</span><br><span style="color: hsl(120, 100%, 40%);">+ {0x1C4E, "Q67"},</span><br><span style="color: hsl(120, 100%, 40%);">+ {0x1C4F, "QM67"},</span><br><span style="color: hsl(120, 100%, 40%);">+ {0x1C50, "B65"},</span><br><span style="color: hsl(120, 100%, 40%);">+ {0x1C52, "C202"},</span><br><span style="color: hsl(120, 100%, 40%);">+ {0x1C54, "C204"},</span><br><span style="color: hsl(120, 100%, 40%);">+ {0x1C56, "C206"},</span><br><span style="color: hsl(120, 100%, 40%);">+ {0x1C5C, "H61"},</span><br><span style="color: hsl(120, 100%, 40%);">+ /* 7-series PCI ids from Intel document 472178 */</span><br><span style="color: hsl(120, 100%, 40%);">+ {0x1E41, "Desktop Sample"},</span><br><span style="color: hsl(120, 100%, 40%);">+ {0x1E42, "Mobile Sample"},</span><br><span style="color: hsl(120, 100%, 40%);">+ {0x1E43, "SFF Sample"},</span><br><span style="color: hsl(120, 100%, 40%);">+ {0x1E44, "Z77"},</span><br><span style="color: hsl(120, 100%, 40%);">+ {0x1E45, "H71"},</span><br><span style="color: hsl(120, 100%, 40%);">+ {0x1E46, "Z75"},</span><br><span style="color: hsl(120, 100%, 40%);">+ {0x1E47, "Q77"},</span><br><span style="color: hsl(120, 100%, 40%);">+ {0x1E48, "Q75"},</span><br><span style="color: hsl(120, 100%, 40%);">+ {0x1E49, "B75"},</span><br><span style="color: hsl(120, 100%, 40%);">+ {0x1E4A, "H77"},</span><br><span style="color: hsl(120, 100%, 40%);">+ {0x1E53, "C216"},</span><br><span style="color: hsl(120, 100%, 40%);">+ {0x1E55, "QM77"},</span><br><span style="color: hsl(120, 100%, 40%);">+ {0x1E56, "QS77"},</span><br><span style="color: hsl(120, 100%, 40%);">+ {0x1E58, "UM77"},</span><br><span style="color: hsl(120, 100%, 40%);">+ {0x1E57, "HM77"},</span><br><span style="color: hsl(120, 100%, 40%);">+ {0x1E59, "HM76"},</span><br><span style="color: hsl(120, 100%, 40%);">+ {0x1E5D, "HM75"},</span><br><span style="color: hsl(120, 100%, 40%);">+ {0x1E5E, "HM70"},</span><br><span style="color: hsl(120, 100%, 40%);">+ {0x1E5F, "NM70"},</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static void report_pch_info(struct device *dev)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ const u16 dev_id = pci_read_config16(dev, PCI_DEVICE_ID);</span><br><span style="color: hsl(120, 100%, 40%);">+ int i;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ const char *pch_type = "Unknown";</span><br><span style="color: hsl(120, 100%, 40%);">+ for (i = 0; i < ARRAY_SIZE(pch_table); i++) {</span><br><span style="color: hsl(120, 100%, 40%);">+ if (pch_table[i].dev_id == dev_id) {</span><br><span style="color: hsl(120, 100%, 40%);">+ pch_type = pch_table[i].dev_name;</span><br><span style="color: hsl(120, 100%, 40%);">+ break;</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ printk(BIOS_INFO, "PCH: detected %s, device id: 0x%x, rev id 0x%x\n",</span><br><span style="color: hsl(120, 100%, 40%);">+ pch_type, dev_id, pci_read_config8(dev, PCI_CLASS_REVISION));</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> static void lpc_init(struct device *dev)</span><br><span> {</span><br><span> printk(BIOS_DEBUG, "pch: lpc_init\n");</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+ /* Print detected platform */</span><br><span style="color: hsl(120, 100%, 40%);">+ report_pch_info(dev);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> /* Set the value for PCI command register. */</span><br><span> pci_write_config16(dev, PCI_COMMAND, 0x000f);</span><br><span> </span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/27667">change 27667</a>. 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<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: merged </div>
<div style="display:none"> Gerrit-Change-Id: I2ced3f2bb9d1d150341a57ff333ca14c897c4fa3 </div>
<div style="display:none"> Gerrit-Change-Number: 27667 </div>
<div style="display:none"> Gerrit-PatchSet: 2 </div>
<div style="display:none"> Gerrit-Owner: Patrick Rudolph <patrick.rudolph@9elements.com> </div>
<div style="display:none"> Gerrit-Reviewer: Felix Held <felix-coreboot@felixheld.de> </div>
<div style="display:none"> Gerrit-Reviewer: build bot (Jenkins) <no-reply@coreboot.org> </div>