<p>Patrick Rudolph has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/27678">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">sb/intel/common: Improve TCO code<br><br>* Use register access like on soc/intel<br>* Fix comment spelling<br>* Report unhandled TCO bits in SMM (was dead code)<br><br>Change-Id: I5f0b439325227f3fb9f409a56f66256b5a9587d0<br>Signed-off-by: Patrick Rudolph <siro@das-labor.org><br>---<br>M src/southbridge/intel/common/pmutil.c<br>M src/southbridge/intel/common/pmutil.h<br>M src/southbridge/intel/common/smihandler.c<br>3 files changed, 14 insertions(+), 11 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/78/27678/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/southbridge/intel/common/pmutil.c b/src/southbridge/intel/common/pmutil.c</span><br><span>index ac72eba..06659fa 100644</span><br><span>--- a/src/southbridge/intel/common/pmutil.c</span><br><span>+++ b/src/southbridge/intel/common/pmutil.c</span><br><span>@@ -163,18 +163,22 @@</span><br><span> */</span><br><span> u32 reset_tco_status(void)</span><br><span> {</span><br><span style="color: hsl(0, 100%, 40%);">- u32 reg32;</span><br><span style="color: hsl(120, 100%, 40%);">+ u16 tco1_sts;</span><br><span style="color: hsl(120, 100%, 40%);">+ u16 tco2_sts;</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- reg32 = read_pmbase32(TCO1_STS);</span><br><span style="color: hsl(120, 100%, 40%);">+ tco1_sts = read_pmbase16(TCO1_STS);</span><br><span style="color: hsl(120, 100%, 40%);">+ write_pmbas16(TCO1_STS, tco1_sts);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> /*</span><br><span style="color: hsl(0, 100%, 40%);">- * set status bits are cleared by writing 1 to them, but don't</span><br><span style="color: hsl(120, 100%, 40%);">+ * Status bits are cleared by writing 1 to them, but don't</span><br><span> * clear BOOT_STS before SECOND_TO_STS.</span><br><span> */</span><br><span style="color: hsl(0, 100%, 40%);">- write_pmbase32(TCO1_STS, reg32 & ~BOOT_STS);</span><br><span style="color: hsl(0, 100%, 40%);">- if (reg32 & BOOT_STS)</span><br><span style="color: hsl(0, 100%, 40%);">- write_pmbase32(TCO1_STS, BOOT_STS);</span><br><span style="color: hsl(120, 100%, 40%);">+ tco2_sts = read_pmbase16(TCO2_STS);</span><br><span style="color: hsl(120, 100%, 40%);">+ write_pmbas16(TCO2_STS, tco2_sts & ~BOOT_STS);</span><br><span style="color: hsl(120, 100%, 40%);">+ if (tco2_sts & BOOT_STS)</span><br><span style="color: hsl(120, 100%, 40%);">+ write_pmbas16(TCO2_STS, BOOT_STS);</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- return reg32;</span><br><span style="color: hsl(120, 100%, 40%);">+ return (tco2_sts << 16) | tco1_sts;</span><br><span> }</span><br><span> </span><br><span> </span><br><span>diff --git a/src/southbridge/intel/common/pmutil.h b/src/southbridge/intel/common/pmutil.h</span><br><span>index 273e0f8..47fa103 100644</span><br><span>--- a/src/southbridge/intel/common/pmutil.h</span><br><span>+++ b/src/southbridge/intel/common/pmutil.h</span><br><span>@@ -96,8 +96,8 @@</span><br><span> #define C3_RES 0x54</span><br><span> #define TCO1_STS 0x64</span><br><span> #define DMISCI_STS (1 << 9)</span><br><span style="color: hsl(0, 100%, 40%);">-#define BOOT_STS (1 << 18)</span><br><span> #define TCO2_STS 0x66</span><br><span style="color: hsl(120, 100%, 40%);">+#define BOOT_STS (1 << 2)</span><br><span> #define TCO1_CNT 0x68</span><br><span> #define TCO_LOCK (1 << 12)</span><br><span> #define TCO2_CNT 0x6a</span><br><span>diff --git a/src/southbridge/intel/common/smihandler.c b/src/southbridge/intel/common/smihandler.c</span><br><span>index fb2fe59..9dfbaa9 100644</span><br><span>--- a/src/southbridge/intel/common/smihandler.c</span><br><span>+++ b/src/southbridge/intel/common/smihandler.c</span><br><span>@@ -417,16 +417,15 @@</span><br><span> * resolute answer would be to power down the</span><br><span> * box.</span><br><span> */</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, "Switching back to RO\n");</span><br><span style="color: hsl(120, 100%, 40%);">+ printk(BIOS_DEBUG, "Switching BIOS_CNTL back to RO\n");</span><br><span> pci_write_config32(PCI_DEV(0, 0x1f, 0), 0xdc,</span><br><span> (bios_cntl & ~1));</span><br><span> } /* No else for now? */</span><br><span> } else if (tco_sts & (1 << 3)) { /* TIMEOUT */</span><br><span> /* Handle TCO timeout */</span><br><span> printk(BIOS_DEBUG, "TCO Timeout.\n");</span><br><span style="color: hsl(0, 100%, 40%);">- } else if (!tco_sts) {</span><br><span style="color: hsl(120, 100%, 40%);">+ } else</span><br><span> dump_tco_status(tco_sts);</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span> }</span><br><span> </span><br><span> static void southbridge_smi_periodic(void)</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/27678">change 27678</a>. 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<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I5f0b439325227f3fb9f409a56f66256b5a9587d0 </div>
<div style="display:none"> Gerrit-Change-Number: 27678 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Patrick Rudolph <siro@das-labor.org> </div>