<p>Patrick Rudolph has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/27664">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">sb/intel/gpio: Cache gpiobase in ramstage and romstage<br><br>Implement caching like it's done with pmbase.<br><br>Change-Id: I26d56a9ff1a8d6e64c164f36e23b846b8b459380<br>Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com><br>---<br>M src/southbridge/intel/common/gpio.c<br>M src/southbridge/intel/common/gpio.h<br>2 files changed, 21 insertions(+), 8 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/27664/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/southbridge/intel/common/gpio.c b/src/southbridge/intel/common/gpio.c</span><br><span>index caf24f4..9eb2fe4 100644</span><br><span>--- a/src/southbridge/intel/common/gpio.c</span><br><span>+++ b/src/southbridge/intel/common/gpio.c</span><br><span>@@ -18,18 +18,36 @@</span><br><span> #include <arch/io.h></span><br><span> #include <device/device.h></span><br><span> #include <device/pci.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <arch/early_variables.h></span><br><span> </span><br><span> #include "gpio.h"</span><br><span> </span><br><span> #define MAX_GPIO_NUMBER 75 /* zero based */</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+/* LPC GPIO Base Address Register */</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_BASE   0x48</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* PCI Configuration Space (D31:F0): LPC */</span><br><span style="color: hsl(120, 100%, 40%);">+#if defined(__SIMPLE_DEVICE__)</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCH_LPC_DEV        PCI_DEV(0, 0x1f, 0)</span><br><span style="color: hsl(120, 100%, 40%);">+#else</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCH_LPC_DEV dev_find_slot(0, PCI_DEVFN(0x1f, 0))</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> static u16 get_gpio_base(void)</span><br><span> {</span><br><span style="color: hsl(0, 100%, 40%);">-#if defined(__PRE_RAM__) || defined(__SMM__)</span><br><span style="color: hsl(120, 100%, 40%);">+#if defined(__SMM__)</span><br><span style="color: hsl(120, 100%, 40%);">+       /* Don't assume GPIO_BASE is still the same */</span><br><span>   return pci_read_config16(PCH_LPC_DEV, GPIO_BASE) & 0xfffc;</span><br><span> #else</span><br><span style="color: hsl(0, 100%, 40%);">- return pci_read_config16(dev_find_slot(0, PCI_DEVFN(0x1f, 0)),</span><br><span style="color: hsl(0, 100%, 40%);">-                           GPIO_BASE) & 0xfffc;</span><br><span style="color: hsl(120, 100%, 40%);">+     static u16 gpiobase CAR_GLOBAL;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+     if (gpiobase)</span><br><span style="color: hsl(120, 100%, 40%);">+         return gpiobase;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+    gpiobase = pci_read_config16(PCH_LPC_DEV, GPIO_BASE) & 0xfffc;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+  return gpiobase;</span><br><span> #endif</span><br><span> }</span><br><span> </span><br><span>diff --git a/src/southbridge/intel/common/gpio.h b/src/southbridge/intel/common/gpio.h</span><br><span>index 8bd3b96..97b7783 100644</span><br><span>--- a/src/southbridge/intel/common/gpio.h</span><br><span>+++ b/src/southbridge/intel/common/gpio.h</span><br><span>@@ -19,11 +19,6 @@</span><br><span> #include <stdint.h></span><br><span> #include <compiler.h></span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-/* LPC GPIO Base Address Register */</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPIO_BASE          0x48</span><br><span style="color: hsl(0, 100%, 40%);">-/* PCI Configuration Space (D31:F0): LPC */</span><br><span style="color: hsl(0, 100%, 40%);">-#define PCH_LPC_DEV              PCI_DEV(0, 0x1f, 0)</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span> /* ICH7 GPIOBASE */</span><br><span> #define GPIO_USE_SEL      0x00</span><br><span> #define GP_IO_SEL       0x04</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/27664">change 27664</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/27664"/><meta itemprop="name" content="View Change"/></div></div>

<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I26d56a9ff1a8d6e64c164f36e23b846b8b459380 </div>
<div style="display:none"> Gerrit-Change-Number: 27664 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Patrick Rudolph <patrick.rudolph@9elements.com> </div>