<p>Matt Delco has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/27673">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">soc/intel/skylake: add CPPC support<br><br>ACPI defines a method _CPC for "Continuous Performance Control" (CPPC).<br>Linux has a driver that enables features like speed shift without<br>consulting ACPI. Other OSes instead rely on this information and need a<br>_CPC present. Prior to this change performance in Win10 never exceeds<br>80% and MSR 0x770 is 0, while with this change higher speeds can be achieved<br>and the MSR value is now 1.<br><br>Rather than add a large package to each processor I have the code add one<br>global instance and each processor has a method that references that instance.<br>I'm open to suggestions on a different place to place the package.<br><br>Change-Id: Ib7e0ae13f4b664b51e42f963e53c71f8832be062<br>Signed-off-by: Matt Delco <delco@chromium.org><br>---<br>M src/soc/intel/skylake/acpi.c<br>1 file changed, 152 insertions(+), 2 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/27673/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/soc/intel/skylake/acpi.c b/src/soc/intel/skylake/acpi.c</span><br><span>index 5bed118..d2d41c9 100644</span><br><span>--- a/src/soc/intel/skylake/acpi.c</span><br><span>+++ b/src/soc/intel/skylake/acpi.c</span><br><span>@@ -501,6 +501,151 @@</span><br><span> acpigen_pop_len();</span><br><span> }</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+#define CPPC_PACKAGE_NAME "\\GCPC"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static void generate_CPPC_method(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ acpigen_write_method("_CPC", 0);</span><br><span style="color: hsl(120, 100%, 40%);">+ acpigen_emit_byte(RETURN_OP);</span><br><span style="color: hsl(120, 100%, 40%);">+ acpigen_emit_namestring(CPPC_PACKAGE_NAME);</span><br><span style="color: hsl(120, 100%, 40%);">+ acpigen_pop_len();</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static void generate_CPPC_package(bool version2)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ acpi_addr_t msr = {</span><br><span style="color: hsl(120, 100%, 40%);">+ .space_id = ACPI_ADDRESS_SPACE_FIXED,</span><br><span style="color: hsl(120, 100%, 40%);">+ .bit_width = 8,</span><br><span style="color: hsl(120, 100%, 40%);">+ .bit_offset = 0,</span><br><span style="color: hsl(120, 100%, 40%);">+ {</span><br><span style="color: hsl(120, 100%, 40%);">+ .access_size = 4</span><br><span style="color: hsl(120, 100%, 40%);">+ },</span><br><span style="color: hsl(120, 100%, 40%);">+ .addrl = 0,</span><br><span style="color: hsl(120, 100%, 40%);">+ .addrh = 0,</span><br><span style="color: hsl(120, 100%, 40%);">+ };</span><br><span style="color: hsl(120, 100%, 40%);">+ static const acpi_addr_t unsupported = {</span><br><span style="color: hsl(120, 100%, 40%);">+ .space_id = ACPI_ADDRESS_SPACE_MEMORY,</span><br><span style="color: hsl(120, 100%, 40%);">+ .bit_width = 0,</span><br><span style="color: hsl(120, 100%, 40%);">+ .bit_offset = 0,</span><br><span style="color: hsl(120, 100%, 40%);">+ {</span><br><span style="color: hsl(120, 100%, 40%);">+ .resv = 0</span><br><span style="color: hsl(120, 100%, 40%);">+ },</span><br><span style="color: hsl(120, 100%, 40%);">+ .addrl = 0,</span><br><span style="color: hsl(120, 100%, 40%);">+ .addrh = 0,</span><br><span style="color: hsl(120, 100%, 40%);">+ };</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ acpigen_write_name(CPPC_PACKAGE_NAME);</span><br><span style="color: hsl(120, 100%, 40%);">+ acpigen_write_package(version2 ? 21 : 17);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ acpigen_write_dword(version2 ? 21 : 17);</span><br><span style="color: hsl(120, 100%, 40%);">+ acpigen_write_byte(version2 ? 2 : 1);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ // 0x771 is IA32_HWP_CAPABILITIES (RO)</span><br><span style="color: hsl(120, 100%, 40%);">+ msr.addrl = 0x771;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ // Highest Performance:</span><br><span style="color: hsl(120, 100%, 40%);">+ // ResourceTemplate(){Register(FFixedHW, 0x08, 0x00, 0x771, 0x04,)},</span><br><span style="color: hsl(120, 100%, 40%);">+ acpigen_write_register_resource(&msr);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ // Nominal Performance -> Guaranteed Performance:</span><br><span style="color: hsl(120, 100%, 40%);">+ // ResourceTemplate(){Register(FFixedHW, 0x08, 0x08, 0x771, 0x04,)},</span><br><span style="color: hsl(120, 100%, 40%);">+ msr.bit_offset = 8;</span><br><span style="color: hsl(120, 100%, 40%);">+ acpigen_write_register_resource(&msr);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ // Lowest Nonlinear Performance -> Most Efficient Performance:</span><br><span style="color: hsl(120, 100%, 40%);">+ // ResourceTemplate(){Register(FFixedHW, 0x08, 0x10, 0x771, 0x04,)},</span><br><span style="color: hsl(120, 100%, 40%);">+ msr.bit_offset = 16;</span><br><span style="color: hsl(120, 100%, 40%);">+ acpigen_write_register_resource(&msr);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ // Lowest Performance:</span><br><span style="color: hsl(120, 100%, 40%);">+ // ResourceTemplate(){Register(FFixedHW, 0x08, 0x18, 0x771, 0x04,)},</span><br><span style="color: hsl(120, 100%, 40%);">+ msr.bit_offset = 24;</span><br><span style="color: hsl(120, 100%, 40%);">+ acpigen_write_register_resource(&msr);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ // Guaranteed Performance Register:</span><br><span style="color: hsl(120, 100%, 40%);">+ // ResourceTemplate(){Register(FFixedHW, 0x08, 0x08, 0x771, 0x04,)},</span><br><span style="color: hsl(120, 100%, 40%);">+ msr.bit_offset = 8;</span><br><span style="color: hsl(120, 100%, 40%);">+ acpigen_write_register_resource(&msr);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ // 0x774 is IA32_HWP_REQUEST (RW)</span><br><span style="color: hsl(120, 100%, 40%);">+ msr.addrl = 0x774;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ // Desired Performance Register:</span><br><span style="color: hsl(120, 100%, 40%);">+ // ResourceTemplate(){Register(FFixedHW, 0x08, 0x10, 0x774, 0x04,)},</span><br><span style="color: hsl(120, 100%, 40%);">+ msr.bit_offset = 16;</span><br><span style="color: hsl(120, 100%, 40%);">+ acpigen_write_register_resource(&msr);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ // Minimum Performance Register:</span><br><span style="color: hsl(120, 100%, 40%);">+ // ResourceTemplate(){Register(FFixedHW, 0x08, 0x00, 0x774, 0x04,)},</span><br><span style="color: hsl(120, 100%, 40%);">+ msr.bit_offset = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+ acpigen_write_register_resource(&msr);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ // Maximum Performance Register:</span><br><span style="color: hsl(120, 100%, 40%);">+ // ResourceTemplate(){Register(FFixedHW, 0x08, 0x08, 0x774, 0x04,)},</span><br><span style="color: hsl(120, 100%, 40%);">+ msr.bit_offset = 8;</span><br><span style="color: hsl(120, 100%, 40%);">+ acpigen_write_register_resource(&msr);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ // Performance Reduction Tolerance Register:</span><br><span style="color: hsl(120, 100%, 40%);">+ // ResourceTemplate(){Register(SystemMemory, 0x00, 0x00, 0x0,,)},</span><br><span style="color: hsl(120, 100%, 40%);">+ acpigen_write_register_resource(&unsupported);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ // Time Window Register:</span><br><span style="color: hsl(120, 100%, 40%);">+ // ResourceTemplate(){Register(SystemMemory, 0x00, 0x00, 0x0,,)},</span><br><span style="color: hsl(120, 100%, 40%);">+ acpigen_write_register_resource(&unsupported);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ // Counter Wraparound Time:</span><br><span style="color: hsl(120, 100%, 40%);">+ // ResourceTemplate(){Register(SystemMemory, 0x00, 0x00, 0x0,,)},</span><br><span style="color: hsl(120, 100%, 40%);">+ acpigen_write_register_resource(&unsupported);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ // 0xE7 is IA32_MPERF</span><br><span style="color: hsl(120, 100%, 40%);">+ msr.addrl = 0xe7;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ // Reference Performance Counter Register:</span><br><span style="color: hsl(120, 100%, 40%);">+ // ResourceTemplate(){Register(FFixedHW, 0x40, 0x00, 0x0E7, 0x04,)},</span><br><span style="color: hsl(120, 100%, 40%);">+ msr.bit_width = 64;</span><br><span style="color: hsl(120, 100%, 40%);">+ msr.bit_offset = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+ acpigen_write_register_resource(&msr);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ // 0xE8 is IA32_APERF</span><br><span style="color: hsl(120, 100%, 40%);">+ msr.addrl = 0xe8;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ // Delivered Performance Counter Register:</span><br><span style="color: hsl(120, 100%, 40%);">+ // ResourceTemplate(){Register(FFixedHW, 0x40, 0x00, 0x0E8, 0x04,)},</span><br><span style="color: hsl(120, 100%, 40%);">+ acpigen_write_register_resource(&msr);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ // 0x777 is IA32_HWP_STATUS</span><br><span style="color: hsl(120, 100%, 40%);">+ msr.addrl = 0x777;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ // Performance Limited Register:</span><br><span style="color: hsl(120, 100%, 40%);">+ // ResourceTemplate(){Register(FFixedHW, 0x01, 0x02, 0x777, 0x04,)},</span><br><span style="color: hsl(120, 100%, 40%);">+ msr.bit_width = 1;</span><br><span style="color: hsl(120, 100%, 40%);">+ msr.bit_offset = 2;</span><br><span style="color: hsl(120, 100%, 40%);">+ acpigen_write_register_resource(&msr);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ // 0x770 is IA32_PM_ENABLE</span><br><span style="color: hsl(120, 100%, 40%);">+ msr.addrl = 0x770;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ // CPPC Enable Register:</span><br><span style="color: hsl(120, 100%, 40%);">+ // ResourceTemplate(){Register(FFixedHW, 0x01, 0x00, 0x770, 0x04,)},</span><br><span style="color: hsl(120, 100%, 40%);">+ msr.bit_offset = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+ acpigen_write_register_resource(&msr);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ if (version2) {</span><br><span style="color: hsl(120, 100%, 40%);">+ // Autonomous Selection Enable = 1</span><br><span style="color: hsl(120, 100%, 40%);">+ acpigen_write_dword(1);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ // Autonomous Activity Window Register</span><br><span style="color: hsl(120, 100%, 40%);">+ acpigen_write_register_resource(&unsupported);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ // Energy Performance Preference Register</span><br><span style="color: hsl(120, 100%, 40%);">+ acpigen_write_register_resource(&unsupported);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ // Reference Performance</span><br><span style="color: hsl(120, 100%, 40%);">+ acpigen_write_register_resource(&unsupported);</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ acpigen_pop_len();</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> void generate_cpu_entries(struct device *device)</span><br><span> {</span><br><span> int core_id, cpu_id, pcontrol_blk = ACPI_BASE_ADDRESS, plen = 6;</span><br><span>@@ -520,6 +665,9 @@</span><br><span> printk(BIOS_DEBUG, "Found %d CPU(s) with %d core(s) each.\n",</span><br><span> numcpus, cores_per_package);</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+ if (config->eist_enable && config->speed_shift_enable)</span><br><span style="color: hsl(120, 100%, 40%);">+ generate_CPPC_package(TRUE);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> for (cpu_id = 0; cpu_id < numcpus; cpu_id++) {</span><br><span> for (core_id = 0; core_id < cores_per_package; core_id++) {</span><br><span> if (core_id > 0) {</span><br><span>@@ -535,11 +683,13 @@</span><br><span> generate_c_state_entries(is_s0ix_enable,</span><br><span> max_c_state);</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- if (config->eist_enable)</span><br><span style="color: hsl(120, 100%, 40%);">+ if (config->eist_enable) {</span><br><span> /* Generate P-state tables */</span><br><span> generate_p_state_entries(core_id,</span><br><span> cores_per_package);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(120, 100%, 40%);">+ if (config->speed_shift_enable)</span><br><span style="color: hsl(120, 100%, 40%);">+ generate_CPPC_method();</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span> acpigen_pop_len();</span><br><span> }</span><br><span> }</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/27673">change 27673</a>. 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<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: Ib7e0ae13f4b664b51e42f963e53c71f8832be062 </div>
<div style="display:none"> Gerrit-Change-Number: 27673 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Matt Delco <delco@chromium.org> </div>