<p>Felix Held has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/27674">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">andybridge/raminit_common: use MCHBAR32 macro consistently<br><br>Change-Id: I22f1c7dbdaf42722115d9e5913d47aa2c9dc7e9a<br>Signed-off-by: Felix Held <felix-coreboot@felixheld.de><br>---<br>M src/northbridge/intel/sandybridge/raminit_common.c<br>1 file changed, 542 insertions(+), 662 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/27674/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c</span><br><span>index 44f7f6d..2a5f09c 100644</span><br><span>--- a/src/northbridge/intel/sandybridge/raminit_common.c</span><br><span>+++ b/src/northbridge/intel/sandybridge/raminit_common.c</span><br><span>@@ -72,10 +72,10 @@</span><br><span> </span><br><span> static void toggle_io_reset(void) {</span><br><span> /* toggle IO reset bit */</span><br><span style="color: hsl(0, 100%, 40%);">- u32 r32 = read32(DEFAULT_MCHBAR + 0x5030);</span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x5030, r32 | 0x20);</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 r32 = MCHBAR32(0x5030);</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x5030) = r32 | 0x20;</span><br><span> udelay(1);</span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x5030, r32 & ~0x20);</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x5030) = r32 & ~0x20;</span><br><span> udelay(1);</span><br><span> }</span><br><span> </span><br><span>@@ -623,7 +623,7 @@</span><br><span> static void wait_428c(int channel)</span><br><span> {</span><br><span> while (1) {</span><br><span style="color: hsl(0, 100%, 40%);">- if (read32(DEFAULT_MCHBAR + 0x428c + (channel << 10)) & 0x50)</span><br><span style="color: hsl(120, 100%, 40%);">+ if (MCHBAR32(0x428c + (channel << 10)) & 0x50)</span><br><span> return;</span><br><span> }</span><br><span> }</span><br><span>@@ -641,15 +641,14 @@</span><br><span> slotrank = (ctrl->rankmap[channel] & 1) ? 0 : 2;</span><br><span> </span><br><span> /* DRAM command ZQCS */</span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x4220 + 0x400 * channel, 0x0f003);</span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x4230 + 0x400 * channel, 0x80c01);</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x4220 + 0x400 * channel) = 0x0f003;</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x4230 + 0x400 * channel) = 0x80c01;</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x4200 + 0x400 * channel,</span><br><span style="color: hsl(0, 100%, 40%);">- (slotrank << 24) | 0x60000);</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x4200 + 0x400 * channel) = (slotrank << 24) | 0x60000);</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x4210 + 0x400 * channel, 0);</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x4210 + 0x400 * channel) = 0;</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x4284 + 0x400 * channel, 0x400001);</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x4284 + 0x400 * channel) = 0x400001;</span><br><span> wait_428c(channel);</span><br><span> }</span><br><span> </span><br><span>@@ -736,27 +735,26 @@</span><br><span> }</span><br><span> </span><br><span> /* DRAM command MRS */</span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x4220 + 0x400 * channel, 0x0f000);</span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x4230 + 0x400 * channel, 0x41001);</span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x4200 + 0x400 * channel,</span><br><span style="color: hsl(0, 100%, 40%);">- (slotrank << 24) | (reg << 20) | val | 0x60000);</span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x4210 + 0x400 * channel, 0);</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x4220 + 0x400 * channel) = 0x0f000;</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x4230 + 0x400 * channel) = 0x41001;</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x4200 + 0x400 * channel) =</span><br><span style="color: hsl(120, 100%, 40%);">+ (slotrank << 24) | (reg << 20) | val | 0x60000;</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x4210 + 0x400 * channel) = 0;</span><br><span> </span><br><span> /* DRAM command MRS */</span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x4224 + 0x400 * channel, 0x1f000);</span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x4234 + 0x400 * channel, 0x41001);</span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x4204 + 0x400 * channel,</span><br><span style="color: hsl(0, 100%, 40%);">- (slotrank << 24) | (reg << 20) | val | 0x60000);</span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x4214 + 0x400 * channel, 0);</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x4224 + 0x400 * channel) = 0x1f000;</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x4234 + 0x400 * channel) = 0x41001;</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x4204 + 0x400 * channel) =</span><br><span style="color: hsl(120, 100%, 40%);">+ (slotrank << 24) | (reg << 20) | val | 0x60000;</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x4214 + 0x400 * channel) = 0;</span><br><span> </span><br><span> /* DRAM command MRS */</span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x4228 + 0x400 * channel, 0x0f000);</span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x4238 + 0x400 * channel,</span><br><span style="color: hsl(0, 100%, 40%);">- 0x1001 | (ctrl->tMOD << 16));</span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x4208 + 0x400 * channel,</span><br><span style="color: hsl(0, 100%, 40%);">- (slotrank << 24) | (reg << 20) | val | 0x60000);</span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x4218 + 0x400 * channel, 0);</span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x4284 + 0x400 * channel, 0x80001);</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x4228 + 0x400 * channel) = 0x0f000;</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x4238 + 0x400 * channel) = 0x1001 | (ctrl->tMOD << 16);</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x4208 + 0x400 * channel) =</span><br><span style="color: hsl(120, 100%, 40%);">+ (slotrank << 24) | (reg << 20) | val | 0x60000;</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x4218 + 0x400 * channel) = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x4284 + 0x400 * channel) = 0x80001;</span><br><span> }</span><br><span> </span><br><span> static u32 make_mr0(ramctr_timing * ctrl, u8 rank)</span><br><span>@@ -789,8 +787,7 @@</span><br><span> </span><br><span> static void dram_mr0(ramctr_timing *ctrl, u8 rank, int channel)</span><br><span> {</span><br><span style="color: hsl(0, 100%, 40%);">- write_mrreg(ctrl, channel, rank, 0,</span><br><span style="color: hsl(0, 100%, 40%);">- make_mr0(ctrl, rank));</span><br><span style="color: hsl(120, 100%, 40%);">+ write_mrreg(ctrl, channel, rank, 0, make_mr0(ctrl, rank));</span><br><span> }</span><br><span> </span><br><span> static u32 encode_odt(u32 odt)</span><br><span>@@ -880,19 +877,19 @@</span><br><span> }</span><br><span> </span><br><span> /* DRAM command NOP */</span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x4e20, 0x7);</span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x4e30, 0xf1001);</span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x4e00, 0x60002);</span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x4e10, 0);</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x4e20) = 0x7;</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x4e30) = 0xf1001;</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x4e00) = 0x60002;</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x4e10) = 0;</span><br><span> </span><br><span> /* DRAM command ZQCL */</span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x4e24, 0x1f003);</span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x4e34, 0x1901001);</span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x4e04, 0x60400);</span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x4e14, 0x288);</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x4e24) = 0x1f003;</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x4e34) = 0x1901001;</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x4e04) = 0x60400;</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x4e14) = 0x288;</span><br><span> </span><br><span> /* execute command queue on all channels ? */</span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x4e84, 0x40004);</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x4e84) = 0x40004;</span><br><span> </span><br><span> // Drain</span><br><span> FOR_ALL_CHANNELS {</span><br><span>@@ -917,12 +914,12 @@</span><br><span> wait_428c(channel);</span><br><span> </span><br><span> /* DRAM command ZQCS */</span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x4220 + 0x400 * channel, 0x0f003);</span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x4230 + 0x400 * channel, 0x659001);</span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x4200 + 0x400 * channel,</span><br><span style="color: hsl(0, 100%, 40%);">- (slotrank << 24) | 0x60000);</span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x4210 + 0x400 * channel, 0x3e0);</span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x4284 + 0x400 * channel, 0x1);</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x4220 + 0x400 * channel) = 0x0f003;</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x4230 + 0x400 * channel) = 0x659001;</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x4200 + 0x400 * channel) =</span><br><span style="color: hsl(120, 100%, 40%);">+ (slotrank << 24) | 0x60000;</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x4210 + 0x400 * channel) = 0x3e0;</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x4284 + 0x400 * channel) = 0x1;</span><br><span> </span><br><span> // Drain</span><br><span> wait_428c(channel);</span><br><span>@@ -967,8 +964,7 @@</span><br><span> case 3:</span><br><span> slot320c[slot] =</span><br><span> (ctrl->timings[channel][2 * slot].val_320c +</span><br><span style="color: hsl(0, 100%, 40%);">- ctrl->timings[channel][2 * slot +</span><br><span style="color: hsl(0, 100%, 40%);">- 1].val_320c) / 2 +</span><br><span style="color: hsl(120, 100%, 40%);">+ ctrl->timings[channel][2 * slot + 1].val_320c) / 2 +</span><br><span> full_shift;</span><br><span> break;</span><br><span> }</span><br><span>@@ -1088,37 +1084,31 @@</span><br><span> * write MR3 MPR enable</span><br><span> * in this mode only RD and RDA are allowed</span><br><span> * all reads return a predefined pattern */</span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x4220 + 0x400 * channel, 0x1f000);</span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x4230 + 0x400 * channel,</span><br><span style="color: hsl(0, 100%, 40%);">- (0xc01 | (ctrl->tMOD << 16)));</span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x4200 + 0x400 * channel,</span><br><span style="color: hsl(0, 100%, 40%);">- (slotrank << 24) | 0x360004);</span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x4210 + 0x400 * channel, 0);</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x4220 + 0x400 * channel) = 0x1f000;</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x4230 + 0x400 * channel) = (0xc01 | (ctrl->tMOD << 16));</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x4200 + 0x400 * channel) = (slotrank << 24) | 0x360004;</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x4210 + 0x400 * channel) = 0;</span><br><span> </span><br><span> /* DRAM command RD */</span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x4224 + 0x400 * channel, 0x1f105);</span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x4234 + 0x400 * channel, 0x4040c01);</span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x4204 + 0x400 * channel, (slotrank << 24));</span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x4214 + 0x400 * channel, 0);</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x4224 + 0x400 * channel) = 0x1f105;</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x4234 + 0x400 * channel) = 0x4040c01;</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x4204 + 0x400 * channel) = (slotrank << 24);</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x4214 + 0x400 * channel) = 0;</span><br><span> </span><br><span> /* DRAM command RD */</span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x4228 + 0x400 * channel, 0x1f105);</span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x4238 + 0x400 * channel,</span><br><span style="color: hsl(0, 100%, 40%);">- 0x100f | ((ctrl->CAS + 36) << 16));</span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x4208 + 0x400 * channel,</span><br><span style="color: hsl(0, 100%, 40%);">- (slotrank << 24) | 0x60000);</span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x4218 + 0x400 * channel, 0);</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x4228 + 0x400 * channel) = 0x1f105;</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x4238 + 0x400 * channel) = 0x100f | ((ctrl->CAS + 36) << 16);</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x4208 + 0x400 * channel) = (slotrank << 24) | 0x60000;</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x4218 + 0x400 * channel) = 0;</span><br><span> </span><br><span> /* DRAM command MRS</span><br><span> * write MR3 MPR disable */</span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x422c + 0x400 * channel, 0x1f000);</span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x423c + 0x400 * channel,</span><br><span style="color: hsl(0, 100%, 40%);">- (0xc01 | (ctrl->tMOD << 16)));</span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x420c + 0x400 * channel,</span><br><span style="color: hsl(0, 100%, 40%);">- (slotrank << 24) | 0x360000);</span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x421c + 0x400 * channel, 0);</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x422c + 0x400 * channel) = 0x1f000;</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x423c + 0x400 * channel) = 0xc01 | (ctrl->tMOD << 16);</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x420c + 0x400 * channel) = (slotrank << 24) | 0x360000;</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x421c + 0x400 * channel) = 0;</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x4284 + 0x400 * channel, 0xc0001);</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x4284 + 0x400 * channel) = 0xc0001;</span><br><span> </span><br><span> wait_428c(channel);</span><br><span> }</span><br><span>@@ -1127,8 +1117,7 @@</span><br><span> int lane)</span><br><span> {</span><br><span> u32 timA = ctrl->timings[channel][slotrank].lanes[lane].timA;</span><br><span style="color: hsl(0, 100%, 40%);">- return ((read32</span><br><span style="color: hsl(0, 100%, 40%);">- (DEFAULT_MCHBAR + lane_registers[lane] + channel * 0x100 + 4 +</span><br><span style="color: hsl(120, 100%, 40%);">+ return ((MCHBAR32(lane_registers[lane] + channel * 0x100 + 4 +</span><br><span> ((timA / 32) & 1) * 4)</span><br><span> >> (timA % 32)) & 1);</span><br><span> }</span><br><span>@@ -1200,7 +1189,7 @@</span><br><span> if (upperA[lane] < rn.middle)</span><br><span> upperA[lane] += 128;</span><br><span> printram("timA: %d, %d, %d: 0x%02x-0x%02x-0x%02x\n",</span><br><span style="color: hsl(0, 100%, 40%);">- channel, slotrank, lane, rn.start, rn.middle, rn.end);</span><br><span style="color: hsl(120, 100%, 40%);">+ channel, slotrank, lane, rn.start, rn.middle, rn.end);</span><br><span> }</span><br><span> }</span><br><span> </span><br><span>@@ -1222,8 +1211,8 @@</span><br><span> test_timA(ctrl, channel, slotrank);</span><br><span> FOR_ALL_LANES {</span><br><span> statistics[lane][timA_delta + 25] +=</span><br><span style="color: hsl(0, 100%, 40%);">- does_lane_work(ctrl, channel, slotrank,</span><br><span style="color: hsl(0, 100%, 40%);">- lane);</span><br><span style="color: hsl(120, 100%, 40%);">+ does_lane_work(ctrl, channel, slotrank,</span><br><span style="color: hsl(120, 100%, 40%);">+ lane);</span><br><span> }</span><br><span> }</span><br><span> }</span><br><span>@@ -1371,34 +1360,32 @@</span><br><span> int upperA[NUM_LANES];</span><br><span> struct timA_minmax mnmx;</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- wait_428c(channel);</span><br><span style="color: hsl(120, 100%, 40%);">+ wait_428c(channel);</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- /* DRAM command PREA */</span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x4220 + 0x400 * channel, 0x1f002);</span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x4230 + 0x400 * channel,</span><br><span style="color: hsl(0, 100%, 40%);">- 0xc01 | (ctrl->tRP << 16));</span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x4200 + 0x400 * channel,</span><br><span style="color: hsl(0, 100%, 40%);">- (slotrank << 24) | 0x60400);</span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x4210 + 0x400 * channel, 0);</span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x4284 + 0x400 * channel, 1);</span><br><span style="color: hsl(120, 100%, 40%);">+ /* DRAM command PREA */</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x4220 + 0x400 * channel) = 0x1f002;</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x4230 + 0x400 * channel) = 0xc01 | (ctrl->tRP << 16);</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x4200 + 0x400 * channel) = (slotrank << 24) | 0x60400;</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x4210 + 0x400 * channel) = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x4284 + 0x400 * channel) = 1;</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x3400, (slotrank << 2) | 0x8001);</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x3400) = (slotrank << 2) | 0x8001;</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- ctrl->timings[channel][slotrank].val_4028 = 4;</span><br><span style="color: hsl(0, 100%, 40%);">- ctrl->timings[channel][slotrank].val_4024 = 55;</span><br><span style="color: hsl(0, 100%, 40%);">- program_timings(ctrl, channel);</span><br><span style="color: hsl(120, 100%, 40%);">+ ctrl->timings[channel][slotrank].val_4028 = 4;</span><br><span style="color: hsl(120, 100%, 40%);">+ ctrl->timings[channel][slotrank].val_4024 = 55;</span><br><span style="color: hsl(120, 100%, 40%);">+ program_timings(ctrl, channel);</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- discover_timA_coarse(ctrl, channel, slotrank, upperA);</span><br><span style="color: hsl(120, 100%, 40%);">+ discover_timA_coarse(ctrl, channel, slotrank, upperA);</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- all_high = 1;</span><br><span style="color: hsl(0, 100%, 40%);">- some_high = 0;</span><br><span style="color: hsl(0, 100%, 40%);">- FOR_ALL_LANES {</span><br><span style="color: hsl(0, 100%, 40%);">- if (ctrl->timings[channel][slotrank].lanes[lane].</span><br><span style="color: hsl(0, 100%, 40%);">- timA >= 0x40)</span><br><span style="color: hsl(0, 100%, 40%);">- some_high = 1;</span><br><span style="color: hsl(0, 100%, 40%);">- else</span><br><span style="color: hsl(0, 100%, 40%);">- all_high = 0;</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(120, 100%, 40%);">+ all_high = 1;</span><br><span style="color: hsl(120, 100%, 40%);">+ some_high = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+ FOR_ALL_LANES {</span><br><span style="color: hsl(120, 100%, 40%);">+ if (ctrl->timings[channel][slotrank].lanes[lane].timA >=</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x40)</span><br><span style="color: hsl(120, 100%, 40%);">+ some_high = 1;</span><br><span style="color: hsl(120, 100%, 40%);">+ else</span><br><span style="color: hsl(120, 100%, 40%);">+ all_high = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span> </span><br><span> if (all_high) {</span><br><span> ctrl->timings[channel][slotrank].val_4028--;</span><br><span>@@ -1446,11 +1433,11 @@</span><br><span> </span><br><span> printram("final results:\n");</span><br><span> FOR_ALL_LANES</span><br><span style="color: hsl(0, 100%, 40%);">- printram("Aval: %d, %d, %d: %x\n", channel, slotrank,</span><br><span style="color: hsl(0, 100%, 40%);">- lane,</span><br><span style="color: hsl(0, 100%, 40%);">- ctrl->timings[channel][slotrank].lanes[lane].timA);</span><br><span style="color: hsl(120, 100%, 40%);">+ printram("Aval: %d, %d, %d: %x\n", channel, slotrank,</span><br><span style="color: hsl(120, 100%, 40%);">+ lane,</span><br><span style="color: hsl(120, 100%, 40%);">+ ctrl->timings[channel][slotrank].lanes[lane].timA);</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x3400, 0);</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x3400) = 0;</span><br><span> </span><br><span> toggle_io_reset();</span><br><span> }</span><br><span>@@ -1459,8 +1446,7 @@</span><br><span> program_timings(ctrl, channel);</span><br><span> }</span><br><span> FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS FOR_ALL_LANES {</span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x4080 + 0x400 * channel</span><br><span style="color: hsl(0, 100%, 40%);">- + 4 * lane, 0);</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x4080 + 0x400 * channel + 4 * lane) = 0;</span><br><span> }</span><br><span> return 0;</span><br><span> }</span><br><span>@@ -1470,82 +1456,75 @@</span><br><span> int lane;</span><br><span> </span><br><span> FOR_ALL_LANES {</span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x4340 + 0x400 * channel + 4 * lane, 0);</span><br><span style="color: hsl(0, 100%, 40%);">- read32(DEFAULT_MCHBAR + 0x4140 + 0x400 * channel + 4 * lane);</span><br><span style="color: hsl(120, 100%, 40%);">+ volatile u32 tmp;</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x4340 + 0x400 * channel + 4 * lane) = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+ tmp = MCHBAR32(0x4140 + 0x400 * channel + 4 * lane);</span><br><span> }</span><br><span> </span><br><span> wait_428c(channel);</span><br><span> </span><br><span> /* DRAM command ACT */</span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x4220 + 0x400 * channel, 0x1f006);</span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x4230 + 0x400 * channel,</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x4220 + 0x400 * channel) = 0x1f006;</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x4230 + 0x400 * channel) =</span><br><span> (max((ctrl->tFAW >> 2) + 1, ctrl->tRRD) << 10)</span><br><span style="color: hsl(0, 100%, 40%);">- | 4 | (ctrl->tRCD << 16));</span><br><span style="color: hsl(120, 100%, 40%);">+ | 4 | (ctrl->tRCD << 16);</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x4200 + 0x400 * channel,</span><br><span style="color: hsl(0, 100%, 40%);">- (slotrank << 24) | (6 << 16));</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x4200 + 0x400 * channel) = (slotrank << 24) | (6 << 16);</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x4210 + 0x400 * channel, 0x244);</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x4210 + 0x400 * channel) = 0x244;</span><br><span> </span><br><span> /* DRAM command NOP */</span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x4224 + 0x400 * channel, 0x1f207);</span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x4234 + 0x400 * channel, 0x8041001);</span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x4204 + 0x400 * channel,</span><br><span style="color: hsl(0, 100%, 40%);">- (slotrank << 24) | 8);</span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x4214 + 0x400 * channel, 0x3e0);</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x4224 + 0x400 * channel) = 0x1f207;</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x4234 + 0x400 * channel) = 0x8041001;</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x4204 + 0x400 * channel) = (slotrank << 24) | 8;</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x4214 + 0x400 * channel) = 0x3e0;</span><br><span> </span><br><span> /* DRAM command WR */</span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x4228 + 0x400 * channel, 0x1f201);</span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x4238 + 0x400 * channel, 0x80411f4);</span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x4208 + 0x400 * channel, (slotrank << 24));</span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x4218 + 0x400 * channel, 0x242);</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x4228 + 0x400 * channel) = 0x1f201;</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x4238 + 0x400 * channel) = 0x80411f4;</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x4208 + 0x400 * channel) = slotrank << 24;</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x4218 + 0x400 * channel) = 0x242;</span><br><span> </span><br><span> /* DRAM command NOP */</span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x422c + 0x400 * channel, 0x1f207);</span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x423c + 0x400 * channel,</span><br><span style="color: hsl(0, 100%, 40%);">- 0x8000c01 | ((ctrl->CWL + ctrl->tWTR + 5) << 16));</span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x420c + 0x400 * channel,</span><br><span style="color: hsl(0, 100%, 40%);">- (slotrank << 24) | 8);</span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x421c + 0x400 * channel, 0x3e0);</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x422c + 0x400 * channel) = 0x1f207;</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x423c + 0x400 * channel) =</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x8000c01 | ((ctrl->CWL + ctrl->tWTR + 5) << 16);</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x420c + 0x400 * channel) = (slotrank << 24) | 8;</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x421c + 0x400 * channel) = 0x3e0;</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x4284 + 0x400 * channel, 0xc0001);</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x4284 + 0x400 * channel) = 0xc0001;</span><br><span> </span><br><span> wait_428c(channel);</span><br><span> </span><br><span> /* DRAM command PREA */</span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x4220 + 0x400 * channel, 0x1f002);</span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x4230 + 0x400 * channel,</span><br><span style="color: hsl(0, 100%, 40%);">- 0xc01 | (ctrl->tRP << 16));</span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x4200 + 0x400 * channel,</span><br><span style="color: hsl(0, 100%, 40%);">- (slotrank << 24) | 0x60400);</span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x4210 + 0x400 * channel, 0x240);</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x4220 + 0x400 * channel) = 0x1f002;</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x4230 + 0x400 * channel) = 0xc01 | (ctrl->tRP << 16);</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x4200 + 0x400 * channel) = (slotrank << 24) | 0x60400;</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x4210 + 0x400 * channel) = 0x240;</span><br><span> </span><br><span> /* DRAM command ACT */</span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x4224 + 0x400 * channel, 0x1f006);</span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x4234 + 0x400 * channel,</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x4224 + 0x400 * channel) = 0x1f006;</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x4234 + 0x400 * channel) =</span><br><span> (max(ctrl->tRRD, (ctrl->tFAW >> 2) + 1) << 10)</span><br><span style="color: hsl(0, 100%, 40%);">- | 8 | (ctrl->CAS << 16));</span><br><span style="color: hsl(120, 100%, 40%);">+ | 8 | (ctrl->CAS << 16);</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x4204 + 0x400 * channel,</span><br><span style="color: hsl(0, 100%, 40%);">- (slotrank << 24) | 0x60000);</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x4204 + 0x400 * channel) = (slotrank << 24) | 0x60000;</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x4214 + 0x400 * channel, 0x244);</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x4214 + 0x400 * channel) = 0x244;</span><br><span> </span><br><span> /* DRAM command RD */</span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x4228 + 0x400 * channel, 0x1f105);</span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x4238 + 0x400 * channel,</span><br><span style="color: hsl(0, 100%, 40%);">- 0x40011f4 | (max(ctrl->tRTP, 8) << 16));</span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x4208 + 0x400 * channel, (slotrank << 24));</span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x4218 + 0x400 * channel, 0x242);</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x4228 + 0x400 * channel) = 0x1f105;</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x4238 + 0x400 * channel) =</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x40011f4 | (max(ctrl->tRTP, 8) << 16);</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x4208 + 0x400 * channel) = (slotrank << 24);</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x4218 + 0x400 * channel) = 0x242;</span><br><span> </span><br><span> /* DRAM command PREA */</span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x422c + 0x400 * channel, 0x1f002);</span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x423c + 0x400 * channel,</span><br><span style="color: hsl(0, 100%, 40%);">- 0xc01 | (ctrl->tRP << 16));</span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x420c + 0x400 * channel,</span><br><span style="color: hsl(0, 100%, 40%);">- (slotrank << 24) | 0x60400);</span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x421c + 0x400 * channel, 0x240);</span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x4284 + 0x400 * channel, 0xc0001);</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x422c + 0x400 * channel) = 0x1f002;</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x423c + 0x400 * channel) = 0xc01 | (ctrl->tRP << 16);</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x420c + 0x400 * channel) = (slotrank << 24) | 0x60400;</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x421c + 0x400 * channel) = 0x240;</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x4284 + 0x400 * channel) = 0xc0001;</span><br><span> wait_428c(channel);</span><br><span> }</span><br><span> </span><br><span>@@ -1558,13 +1537,11 @@</span><br><span> wait_428c(channel);</span><br><span> </span><br><span> /* DRAM command PREA */</span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x4220 + 0x400 * channel, 0x1f002);</span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x4230 + 0x400 * channel,</span><br><span style="color: hsl(0, 100%, 40%);">- 0xc01 | (ctrl->tRP << 16));</span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x4200 + 0x400 * channel,</span><br><span style="color: hsl(0, 100%, 40%);">- (slotrank << 24) | 0x60400);</span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x4210 + 0x400 * channel, 0x240);</span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x4284 + 0x400 * channel, 1);</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x4220 + 0x400 * channel) = 0x1f002;</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x4230 + 0x400 * channel) = 0xc01 | (ctrl->tRP << 16);</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x4200 + 0x400 * channel) = (slotrank << 24) | 0x60400;</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x4210 + 0x400 * channel) = 0x240;</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x4284 + 0x400 * channel) = 1;</span><br><span> </span><br><span> for (timC = 0; timC <= MAX_TIMC; timC++) {</span><br><span> FOR_ALL_LANES ctrl->timings[channel][slotrank].lanes[lane].</span><br><span>@@ -1575,8 +1552,7 @@</span><br><span> </span><br><span> FOR_ALL_LANES {</span><br><span> statistics[lane][timC] =</span><br><span style="color: hsl(0, 100%, 40%);">- read32(DEFAULT_MCHBAR + 0x4340 + 4 * lane +</span><br><span style="color: hsl(0, 100%, 40%);">- 0x400 * channel);</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x4340 + 4 * lane + 0x400 * channel);</span><br><span> }</span><br><span> }</span><br><span> FOR_ALL_LANES {</span><br><span>@@ -1589,7 +1565,7 @@</span><br><span> return MAKE_ERR;</span><br><span> }</span><br><span> printram("timC: %d, %d, %d: 0x%02x-0x%02x-0x%02x\n",</span><br><span style="color: hsl(0, 100%, 40%);">- channel, slotrank, lane, rn.start, rn.middle, rn.end);</span><br><span style="color: hsl(120, 100%, 40%);">+ channel, slotrank, lane, rn.start, rn.middle, rn.end);</span><br><span> }</span><br><span> return 0;</span><br><span> }</span><br><span>@@ -1654,43 +1630,37 @@</span><br><span> * write MR3 MPR enable</span><br><span> * in this mode only RD and RDA are allowed</span><br><span> * all reads return a predefined pattern */</span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x4220 + 0x400 * channel,</span><br><span style="color: hsl(0, 100%, 40%);">- 0x1f000);</span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x4230 + 0x400 * channel,</span><br><span style="color: hsl(0, 100%, 40%);">- 0xc01 | (ctrl->tMOD << 16));</span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x4200 + 0x400 * channel,</span><br><span style="color: hsl(0, 100%, 40%);">- (slotrank << 24) | 0x360004);</span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x4210 + 0x400 * channel, 0);</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x4220 + 0x400 * channel) = 0x1f000;</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x4230 + 0x400 * channel) =</span><br><span style="color: hsl(120, 100%, 40%);">+ 0xc01 | (ctrl->tMOD << 16);</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x4200 + 0x400 * channel) =</span><br><span style="color: hsl(120, 100%, 40%);">+ (slotrank << 24) | 0x360004;</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x4210 + 0x400 * channel) = 0;</span><br><span> </span><br><span> /* DRAM command RD */</span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x4224 + 0x400 * channel,</span><br><span style="color: hsl(0, 100%, 40%);">- 0x1f105);</span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x4234 + 0x400 * channel,</span><br><span style="color: hsl(0, 100%, 40%);">- 0x4041003);</span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x4204 + 0x400 * channel,</span><br><span style="color: hsl(0, 100%, 40%);">- (slotrank << 24) | 0);</span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x4214 + 0x400 * channel, 0);</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x4224 + 0x400 * channel) = 0x1f105;</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x4234 + 0x400 * channel) = 0x4041003;</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x4204 + 0x400 * channel) =</span><br><span style="color: hsl(120, 100%, 40%);">+ (slotrank << 24) | 0;</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x4214 + 0x400 * channel) = 0;</span><br><span> </span><br><span> /* DRAM command RD */</span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x4228 + 0x400 * channel,</span><br><span style="color: hsl(0, 100%, 40%);">- 0x1f105);</span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x4238 + 0x400 * channel,</span><br><span style="color: hsl(0, 100%, 40%);">- 0x1001 | ((ctrl->CAS + 8) << 16));</span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x4208 + 0x400 * channel,</span><br><span style="color: hsl(0, 100%, 40%);">- (slotrank << 24) | 0x60000);</span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x4218 + 0x400 * channel, 0);</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x4228 + 0x400 * channel) = 0x1f105;</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x4238 + 0x400 * channel) =</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x1001 | ((ctrl->CAS + 8) << 16);</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x4208 + 0x400 * channel) =</span><br><span style="color: hsl(120, 100%, 40%);">+ (slotrank << 24) | 0x60000;</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x4218 + 0x400 * channel) = 0;</span><br><span> </span><br><span> /* DRAM command MRS</span><br><span> * write MR3 MPR disable */</span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x422c + 0x400 * channel,</span><br><span style="color: hsl(0, 100%, 40%);">- 0x1f000);</span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x423c + 0x400 * channel,</span><br><span style="color: hsl(0, 100%, 40%);">- 0xc01 | (ctrl->tMOD << 16));</span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x420c + 0x400 * channel,</span><br><span style="color: hsl(0, 100%, 40%);">- (slotrank << 24) | 0x360000);</span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x421c + 0x400 * channel, 0);</span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x4284 + 0x400 * channel,</span><br><span style="color: hsl(0, 100%, 40%);">- 0xc0001);</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x422c + 0x400 * channel) = 0x1f000;</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x423c + 0x400 * channel) =</span><br><span style="color: hsl(120, 100%, 40%);">+ 0xc01 | (ctrl->tMOD << 16);</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x420c + 0x400 * channel) =</span><br><span style="color: hsl(120, 100%, 40%);">+ (slotrank << 24) | 0x360000;</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x421c + 0x400 * channel) = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x4284 + 0x400 * channel) = 0xc0001;</span><br><span> </span><br><span> wait_428c(channel);</span><br><span> }</span><br><span>@@ -1710,45 +1680,39 @@</span><br><span> * write MR3 MPR enable</span><br><span> * in this mode only RD and RDA are allowed</span><br><span> * all reads return a predefined pattern */</span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x4220 + 0x400 * channel,</span><br><span style="color: hsl(0, 100%, 40%);">- 0x1f000);</span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x4230 + 0x400 * channel,</span><br><span style="color: hsl(0, 100%, 40%);">- 0xc01 | (ctrl->tMOD << 16));</span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x4200 + 0x400 * channel,</span><br><span style="color: hsl(0, 100%, 40%);">- (slotrank << 24) | 0x360004);</span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x4210 + 0x400 * channel, 0);</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x4220 + 0x400 * channel) = 0x1f000;</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x4230 + 0x400 * channel) =</span><br><span style="color: hsl(120, 100%, 40%);">+ 0xc01 | (ctrl->tMOD << 16);</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x4200 + 0x400 * channel) =</span><br><span style="color: hsl(120, 100%, 40%);">+ (slotrank << 24) | 0x360004;</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x4210 + 0x400 * channel) = 0;</span><br><span> </span><br><span> /* DRAM command RD */</span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x4224 + 0x400 * channel,</span><br><span style="color: hsl(0, 100%, 40%);">- 0x1f105);</span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x4234 + 0x400 * channel,</span><br><span style="color: hsl(0, 100%, 40%);">- 0x4041003);</span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x4204 + 0x400 * channel,</span><br><span style="color: hsl(0, 100%, 40%);">- (slotrank << 24) | 0);</span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x4214 + 0x400 * channel, 0);</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x4224 + 0x400 * channel) = 0x1f105;</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x4234 + 0x400 * channel) = 0x4041003;</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x4204 + 0x400 * channel) =</span><br><span style="color: hsl(120, 100%, 40%);">+ (slotrank << 24) | 0;</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x4214 + 0x400 * channel) = 0;</span><br><span> </span><br><span> /* DRAM command RD */</span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x4228 + 0x400 * channel,</span><br><span style="color: hsl(0, 100%, 40%);">- 0x1f105);</span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x4238 + 0x400 * channel,</span><br><span style="color: hsl(0, 100%, 40%);">- 0x1001 | ((ctrl->CAS + 8) << 16));</span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x4208 + 0x400 * channel,</span><br><span style="color: hsl(0, 100%, 40%);">- (slotrank << 24) | 0x60000);</span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x4218 + 0x400 * channel, 0);</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x4228 + 0x400 * channel) = 0x1f105;</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x4238 + 0x400 * channel) =</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x1001 | ((ctrl->CAS + 8) << 16);</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x4208 + 0x400 * channel) =</span><br><span style="color: hsl(120, 100%, 40%);">+ (slotrank << 24) | 0x60000;</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x4218 + 0x400 * channel) = 0;</span><br><span> </span><br><span> /* DRAM command MRS</span><br><span> * write MR3 MPR disable */</span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x422c + 0x400 * channel,</span><br><span style="color: hsl(0, 100%, 40%);">- 0x1f000);</span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x423c + 0x400 * channel,</span><br><span style="color: hsl(0, 100%, 40%);">- 0xc01 | (ctrl->tMOD << 16));</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x422c + 0x400 * channel) = 0x1f000;</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x423c + 0x400 * channel) =</span><br><span style="color: hsl(120, 100%, 40%);">+ 0xc01 | (ctrl->tMOD << 16);</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x420c + 0x400 * channel,</span><br><span style="color: hsl(0, 100%, 40%);">- (slotrank << 24) | 0x360000);</span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x421c + 0x400 * channel, 0);</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x420c + 0x400 * channel) =</span><br><span style="color: hsl(120, 100%, 40%);">+ (slotrank << 24) | 0x360000;</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x421c + 0x400 * channel) = 0;</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x4284 + 0x400 * channel,</span><br><span style="color: hsl(0, 100%, 40%);">- 0xc0001);</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x4284 + 0x400 * channel) = 0xc0001;</span><br><span> wait_428c(channel);</span><br><span> }</span><br><span> }</span><br><span>@@ -1762,22 +1726,20 @@</span><br><span> </span><br><span> wait_428c(channel);</span><br><span> /* DRAM command NOP */</span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x4220 + 0x400 * channel, 0x1f207);</span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x4230 + 0x400 * channel,</span><br><span style="color: hsl(0, 100%, 40%);">- 0x8000c01 | ((ctrl->CWL + ctrl->tWLO) << 16));</span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x4200 + 0x400 * channel,</span><br><span style="color: hsl(0, 100%, 40%);">- 8 | (slotrank << 24));</span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x4210 + 0x400 * channel, 0);</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x4220 + 0x400 * channel) = 0x1f207;</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x4230 + 0x400 * channel) =</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x8000c01 | ((ctrl->CWL + ctrl->tWLO) << 16);</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x4200 + 0x400 * channel) = 8 | (slotrank << 24);</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x4210 + 0x400 * channel) = 0;</span><br><span> </span><br><span> /* DRAM command NOP */</span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x4224 + 0x400 * channel, 0x1f107);</span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x4234 + 0x400 * channel,</span><br><span style="color: hsl(0, 100%, 40%);">- 0x4000c01 | ((ctrl->CAS + 38) << 16));</span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x4204 + 0x400 * channel,</span><br><span style="color: hsl(0, 100%, 40%);">- (slotrank << 24) | 4);</span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x4214 + 0x400 * channel, 0);</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x4224 + 0x400 * channel) = 0x1f107;</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x4234 + 0x400 * channel) =</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x4000c01 | ((ctrl->CAS + 38) << 16);</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x4204 + 0x400 * channel) = (slotrank << 24) | 4;</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x4214 + 0x400 * channel) = 0;</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x400 * channel + 0x4284, 0x40001);</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x400 * channel + 0x4284) = 0x40001;</span><br><span> wait_428c(channel);</span><br><span> </span><br><span> /* disable DQs on this slotrank */</span><br><span>@@ -1791,7 +1753,7 @@</span><br><span> int statistics[NUM_LANES][128];</span><br><span> int lane;</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x3400, 0x108052 | (slotrank << 2));</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x3400) = 0x108052 | (slotrank << 2);</span><br><span> </span><br><span> for (timB = 0; timB < 128; timB++) {</span><br><span> FOR_ALL_LANES {</span><br><span>@@ -1803,8 +1765,7 @@</span><br><span> </span><br><span> FOR_ALL_LANES {</span><br><span> statistics[lane][timB] =</span><br><span style="color: hsl(0, 100%, 40%);">- !((read32</span><br><span style="color: hsl(0, 100%, 40%);">- (DEFAULT_MCHBAR + lane_registers[lane] +</span><br><span style="color: hsl(120, 100%, 40%);">+ !((MCHBAR32(lane_registers[lane] +</span><br><span> channel * 0x100 + 4 + ((timB / 32) & 1) * 4)</span><br><span> >> (timB % 32)) & 1);</span><br><span> }</span><br><span>@@ -1861,87 +1822,76 @@</span><br><span> static void adjust_high_timB(ramctr_timing * ctrl)</span><br><span> {</span><br><span> int channel, slotrank, lane, old;</span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x3400, 0x200);</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x3400) = 0x200;</span><br><span> FOR_ALL_POPULATED_CHANNELS {</span><br><span> fill_pattern1(ctrl, channel);</span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x4288 + (channel << 10), 1);</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x4288 + (channel << 10)) = 1;</span><br><span> }</span><br><span> FOR_ALL_POPULATED_CHANNELS FOR_ALL_POPULATED_RANKS {</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x4288 + 0x400 * channel, 0x10001);</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(x4288 + 0x400 * channel) = 0x10001;</span><br><span> </span><br><span> wait_428c(channel);</span><br><span> </span><br><span> /* DRAM command ACT */</span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x4220 + 0x400 * channel, 0x1f006);</span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x4230 + 0x400 * channel,</span><br><span style="color: hsl(0, 100%, 40%);">- 0xc01 | (ctrl->tRCD << 16));</span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x4200 + 0x400 * channel,</span><br><span style="color: hsl(0, 100%, 40%);">- (slotrank << 24) | 0x60000);</span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x4210 + 0x400 * channel, 0);</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x4220 + 0x400 * channel) = 0x1f006;</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x4230 + 0x400 * channel) = 0xc01 | (ctrl->tRCD << 16);</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x4200 + 0x400 * channel) = (slotrank << 24) | 0x60000;</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x4210 + 0x400 * channel) = 0;</span><br><span> </span><br><span> /* DRAM command NOP */</span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x4224 + 0x400 * channel, 0x1f207);</span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x4234 + 0x400 * channel, 0x8040c01);</span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x4204 + 0x400 * channel,</span><br><span style="color: hsl(0, 100%, 40%);">- (slotrank << 24) | 0x8);</span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x4214 + 0x400 * channel, 0x3e0);</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x4224 + 0x400 * channel) = 0x1f207;</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x4234 + 0x400 * channel) = 0x8040c01;</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x4204 + 0x400 * channel) = (slotrank << 24) | 0x8;</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x4214 + 0x400 * channel) = 0x3e0;</span><br><span> </span><br><span> /* DRAM command WR */</span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x4228 + 0x400 * channel, 0x1f201);</span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x4238 + 0x400 * channel, 0x8041003);</span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x4208 + 0x400 * channel,</span><br><span style="color: hsl(0, 100%, 40%);">- (slotrank << 24));</span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x4218 + 0x400 * channel, 0x3e2);</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x4228 + 0x400 * channel) = 0x1f201;</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x4238 + 0x400 * channel) = 0x8041003;</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x4208 + 0x400 * channel) = (slotrank << 24);</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x4218 + 0x400 * channel) = 0x3e2;</span><br><span> </span><br><span> /* DRAM command NOP */</span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x422c + 0x400 * channel, 0x1f207);</span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x423c + 0x400 * channel,</span><br><span style="color: hsl(0, 100%, 40%);">- 0x8000c01 | ((ctrl->CWL + ctrl->tWTR + 5) << 16));</span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x420c + 0x400 * channel,</span><br><span style="color: hsl(0, 100%, 40%);">- (slotrank << 24) | 0x8);</span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x421c + 0x400 * channel, 0x3e0);</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x422c + 0x400 * channel) = 0x1f207;</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x423c + 0x400 * channel) =</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x8000c01 | ((ctrl->CWL + ctrl->tWTR + 5) << 16);</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x420c + 0x400 * channel) = (slotrank << 24) | 0x8;</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x421c + 0x400 * channel) = 0x3e0;</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x4284 + 0x400 * channel, 0xc0001);</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x4284 + 0x400 * channel) = 0xc0001;</span><br><span> </span><br><span> wait_428c(channel);</span><br><span> </span><br><span> /* DRAM command PREA */</span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x4220 + 0x400 * channel, 0x1f002);</span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x4230 + 0x400 * channel,</span><br><span style="color: hsl(0, 100%, 40%);">- 0xc01 | ((ctrl->tRP) << 16));</span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x4200 + 0x400 * channel,</span><br><span style="color: hsl(0, 100%, 40%);">- (slotrank << 24) | 0x60400);</span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x4210 + 0x400 * channel, 0x240);</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x4220 + 0x400 * channel) = 0x1f002;</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x4230 + 0x400 * channel) =</span><br><span style="color: hsl(120, 100%, 40%);">+ 0xc01 | ((ctrl->tRP) << 16);</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x4200 + 0x400 * channel) =</span><br><span style="color: hsl(120, 100%, 40%);">+ (slotrank << 24) | 0x60400;</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x4210 + 0x400 * channel) = 0x240;</span><br><span> </span><br><span> /* DRAM command ACT */</span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x4224 + 0x400 * channel, 0x1f006);</span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x4234 + 0x400 * channel,</span><br><span style="color: hsl(0, 100%, 40%);">- 0xc01 | ((ctrl->tRCD) << 16));</span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x4204 + 0x400 * channel,</span><br><span style="color: hsl(0, 100%, 40%);">- (slotrank << 24) | 0x60000);</span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x4214 + 0x400 * channel, 0);</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x4224 + 0x400 * channel) = 0x1f006;</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x4234 + 0x400 * channel) =</span><br><span style="color: hsl(120, 100%, 40%);">+ 0xc01 | ((ctrl->tRCD) << 16);</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x4204 + 0x400 * channel) = (slotrank << 24) | 0x60000;</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x4214 + 0x400 * channel) = 0;</span><br><span> </span><br><span> /* DRAM command RD */</span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x4228 + 0x400 * channel, 0x3f105);</span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x4238 + 0x400 * channel,</span><br><span style="color: hsl(0, 100%, 40%);">- 0x4000c01 |</span><br><span style="color: hsl(0, 100%, 40%);">- ((ctrl->tRP +</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x4228 + 0x400 * channel) = 0x3f105;</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x4238 + 0x400 * channel) = 0x4000c01 | ((ctrl->tRP +</span><br><span> ctrl->timings[channel][slotrank].val_4024 +</span><br><span style="color: hsl(0, 100%, 40%);">- ctrl->timings[channel][slotrank].val_4028) << 16));</span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x4208 + 0x400 * channel,</span><br><span style="color: hsl(0, 100%, 40%);">- (slotrank << 24) | 0x60008);</span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x4218 + 0x400 * channel, 0);</span><br><span style="color: hsl(120, 100%, 40%);">+ ctrl->timings[channel][slotrank].val_4028) << 16);</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x4208 + 0x400 * channel) = (slotrank << 24) | 0x60008;</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x4218 + 0x400 * channel) = 0;</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x4284 + 0x400 * channel, 0x80001);</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x4284 + 0x400 * channel) = 0x80001;</span><br><span> wait_428c(channel);</span><br><span> FOR_ALL_LANES {</span><br><span style="color: hsl(0, 100%, 40%);">- u64 res =</span><br><span style="color: hsl(0, 100%, 40%);">- read32(DEFAULT_MCHBAR + lane_registers[lane] +</span><br><span style="color: hsl(0, 100%, 40%);">- 0x100 * channel + 4);</span><br><span style="color: hsl(0, 100%, 40%);">- res |=</span><br><span style="color: hsl(0, 100%, 40%);">- ((u64) read32(DEFAULT_MCHBAR + lane_registers[lane] +</span><br><span style="color: hsl(0, 100%, 40%);">- 0x100 * channel + 8)) << 32;</span><br><span style="color: hsl(120, 100%, 40%);">+ u64 res = MCHBAR32(lane_registers[lane] +</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x100 * channel + 4);</span><br><span style="color: hsl(120, 100%, 40%);">+ res |= ((u64) MCHBAR32(lane_registers[lane] +</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x100 * channel + 8)) << 32;</span><br><span> old = ctrl->timings[channel][slotrank].lanes[lane].timB;</span><br><span> ctrl->timings[channel][slotrank].lanes[lane].timB +=</span><br><span> get_timB_high_adjust(res) * 64;</span><br><span>@@ -1953,7 +1903,7 @@</span><br><span> timB);</span><br><span> }</span><br><span> }</span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x3400, 0);</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x3400) = 0;</span><br><span> }</span><br><span> </span><br><span> static void write_op(ramctr_timing * ctrl, int channel)</span><br><span>@@ -1966,15 +1916,14 @@</span><br><span> slotrank = !(ctrl->rankmap[channel] & 1) ? 2 : 0;</span><br><span> </span><br><span> /* DRAM command ACT */</span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x4220 + 0x400 * channel, 0x0f003);</span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x4230 + 0x400 * channel, 0x41001);</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x4220 + 0x400 * channel) = 0x0f003;</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x4230 + 0x400 * channel) = 0x41001;</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x4200 + 0x400 * channel,</span><br><span style="color: hsl(0, 100%, 40%);">- (slotrank << 24) | 0x60000);</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x4200 + 0x400 * channel) = (slotrank << 24) | 0x60000;</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x4210 + 0x400 * channel, 0x3e0);</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x4210 + 0x400 * channel) = 0x3e0;</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x4284 + 0x400 * channel, 1);</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x4284 + 0x400 * channel) = 1;</span><br><span> wait_428c(channel);</span><br><span> }</span><br><span> </span><br><span>@@ -1994,21 +1943,20 @@</span><br><span> {</span><br><span> int channel, slotrank, lane;</span><br><span> int err;</span><br><span style="color: hsl(120, 100%, 40%);">+ volatile u32 tmp;</span><br><span> </span><br><span> FOR_ALL_POPULATED_CHANNELS</span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x4008 + 0x400 * channel,</span><br><span style="color: hsl(0, 100%, 40%);">- read32(DEFAULT_MCHBAR + 0x4008 +</span><br><span style="color: hsl(0, 100%, 40%);">- 0x400 * channel) | 0x8000000);</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x4008 + 0x400 * channel) =</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x4008 + 0x400 * channel) | 0x8000000;</span><br><span> </span><br><span> FOR_ALL_POPULATED_CHANNELS {</span><br><span> write_op(ctrl, channel);</span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x4020 + 0x400 * channel,</span><br><span style="color: hsl(0, 100%, 40%);">- read32(DEFAULT_MCHBAR + 0x4020 +</span><br><span style="color: hsl(0, 100%, 40%);">- 0x400 * channel) | 0x200000);</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x4020 + 0x400 * channel) =</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x4020 + 0x400 * channel) | 0x200000;</span><br><span> }</span><br><span> </span><br><span> /* refresh disable */</span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x5030, read32(DEFAULT_MCHBAR + 0x5030) & ~8);</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x5030) = MCHBAR32(0x5030) & ~8;</span><br><span> FOR_ALL_POPULATED_CHANNELS {</span><br><span> write_op(ctrl, channel);</span><br><span> }</span><br><span>@@ -2017,11 +1965,11 @@</span><br><span> * disable all DQ outputs</span><br><span> * only NOP is allowed in this mode */</span><br><span> FOR_ALL_CHANNELS</span><br><span style="color: hsl(0, 100%, 40%);">- FOR_ALL_POPULATED_RANKS</span><br><span style="color: hsl(0, 100%, 40%);">- write_mrreg(ctrl, channel, slotrank, 1,</span><br><span style="color: hsl(0, 100%, 40%);">- make_mr1(ctrl, slotrank, channel) | 0x1080);</span><br><span style="color: hsl(120, 100%, 40%);">+ FOR_ALL_POPULATED_RANKS</span><br><span style="color: hsl(120, 100%, 40%);">+ write_mrreg(ctrl, channel, slotrank, 1,</span><br><span style="color: hsl(120, 100%, 40%);">+ make_mr1(ctrl, slotrank, channel) | 0x1080);</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x3400, 0x108052);</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x3400) = 0x108052;</span><br><span> </span><br><span> toggle_io_reset();</span><br><span> </span><br><span>@@ -2035,30 +1983,29 @@</span><br><span> /* disable write leveling on all ranks */</span><br><span> FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS</span><br><span> write_mrreg(ctrl, channel,</span><br><span style="color: hsl(0, 100%, 40%);">- slotrank, 1, make_mr1(ctrl, slotrank, channel));</span><br><span style="color: hsl(120, 100%, 40%);">+ slotrank, 1, make_mr1(ctrl, slotrank, channel));</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x3400, 0);</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x3400) = 0;</span><br><span> </span><br><span> FOR_ALL_POPULATED_CHANNELS</span><br><span> wait_428c(channel);</span><br><span> </span><br><span> /* refresh enable */</span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x5030, read32(DEFAULT_MCHBAR + 0x5030) | 8);</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x5030) = MCHBAR32(0x5030) | 8;</span><br><span> </span><br><span> FOR_ALL_POPULATED_CHANNELS {</span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x4020 + 0x400 * channel,</span><br><span style="color: hsl(0, 100%, 40%);">- ~0x00200000 & read32(DEFAULT_MCHBAR + 0x4020 +</span><br><span style="color: hsl(0, 100%, 40%);">- 0x400 * channel));</span><br><span style="color: hsl(0, 100%, 40%);">- read32(DEFAULT_MCHBAR + 0x428c + 0x400 * channel);</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x4020 + 0x400 * channel) =</span><br><span style="color: hsl(120, 100%, 40%);">+ ~0x00200000 & MCHBAR32(0x4020 + 0x400 * channel);</span><br><span style="color: hsl(120, 100%, 40%);">+ tmp = MCHBAR32(0x428c + 0x400 * channel);</span><br><span> wait_428c(channel);</span><br><span> </span><br><span> /* DRAM command ZQCS */</span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x4220 + 0x400 * channel, 0x0f003);</span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x4230 + 0x400 * channel, 0x659001);</span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x4200 + 0x400 * channel, 0x60000);</span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x4210 + 0x400 * channel, 0x3e0);</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x4220 + 0x400 * channel) = 0x0f003;</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x4230 + 0x400 * channel) = 0x659001;</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x4200 + 0x400 * channel) = 0x60000;</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x4210 + 0x400 * channel) = 0x3e0;</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x4284 + 0x400 * channel, 1);</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x4284 + 0x400 * channel) = 1;</span><br><span> wait_428c(channel);</span><br><span> }</span><br><span> </span><br><span>@@ -2069,14 +2016,13 @@</span><br><span> printram("CPF\n");</span><br><span> </span><br><span> FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS FOR_ALL_LANES {</span><br><span style="color: hsl(0, 100%, 40%);">- read32(DEFAULT_MCHBAR + 0x4080 + 0x400 * channel + 4 * lane);</span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x4080 + 0x400 * channel + 4 * lane,</span><br><span style="color: hsl(0, 100%, 40%);">- 0);</span><br><span style="color: hsl(120, 100%, 40%);">+ tmp = MCHBAR32(0x4080 + 0x400 * channel + 4 * lane);</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x4080 + 0x400 * channel + 4 * lane) = 0;</span><br><span> }</span><br><span> </span><br><span> FOR_ALL_POPULATED_CHANNELS {</span><br><span> fill_pattern0(ctrl, channel, 0xaaaaaaaa, 0x55555555);</span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x4288 + (channel << 10), 0);</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x4288 + (channel << 10)) = 0;</span><br><span> }</span><br><span> </span><br><span> FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS {</span><br><span>@@ -2095,9 +2041,8 @@</span><br><span> program_timings(ctrl, channel);</span><br><span> </span><br><span> FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS FOR_ALL_LANES {</span><br><span style="color: hsl(0, 100%, 40%);">- read32(DEFAULT_MCHBAR + 0x4080 + 0x400 * channel + 4 * lane);</span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x4080 + 0x400 * channel + 4 * lane,</span><br><span style="color: hsl(0, 100%, 40%);">- 0);</span><br><span style="color: hsl(120, 100%, 40%);">+ tmp = MCHBAR32(0x4080 + 0x400 * channel + 4 * lane);</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x4080 + 0x400 * channel + 4 * lane) = 0;</span><br><span> }</span><br><span> return 0;</span><br><span> }</span><br><span>@@ -2117,53 +2062,48 @@</span><br><span> }</span><br><span> program_timings(ctrl, channel);</span><br><span> FOR_ALL_LANES {</span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 4 * lane + 0x4f40, 0);</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(4 * lane + 0x4f40) = 0;</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x4288 + 0x400 * channel, 0x1f);</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x4288 + 0x400 * channel) = 0x1f;</span><br><span> </span><br><span> wait_428c(channel);</span><br><span> /* DRAM command ACT */</span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x4220 + 0x400 * channel, 0x1f006);</span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x4230 + 0x400 * channel,</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x4220 + 0x400 * channel) = 0x1f006;</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x4230 + 0x400 * channel) =</span><br><span> ((max(ctrl->tRRD, (ctrl->tFAW >> 2) + 1)) << 10)</span><br><span style="color: hsl(0, 100%, 40%);">- | 8 | (ctrl->tRCD << 16));</span><br><span style="color: hsl(120, 100%, 40%);">+ | 8 | (ctrl->tRCD << 16);</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x4200 + 0x400 * channel,</span><br><span style="color: hsl(0, 100%, 40%);">- (slotrank << 24) | ctr | 0x60000);</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x4200 + 0x400 * channel) =</span><br><span style="color: hsl(120, 100%, 40%);">+ (slotrank << 24) | ctr | 0x60000;</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x4210 + 0x400 * channel, 0x244);</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x4210 + 0x400 * channel) = 0x244;</span><br><span> /* DRAM command WR */</span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x4224 + 0x400 * channel, 0x1f201);</span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x4234 + 0x400 * channel,</span><br><span style="color: hsl(0, 100%, 40%);">- 0x8001020 | ((ctrl->CWL + ctrl->tWTR + 8) << 16));</span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x4204 + 0x400 * channel,</span><br><span style="color: hsl(0, 100%, 40%);">- (slotrank << 24));</span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x4244 + 0x400 * channel, 0x389abcd);</span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x4214 + 0x400 * channel, 0x20e42);</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x4224 + 0x400 * channel) = 0x1f201;</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x4234 + 0x400 * channel) =</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x8001020 | ((ctrl->CWL + ctrl->tWTR + 8) << 16);</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x4204 + 0x400 * channel) = (slotrank << 24);</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x4244 + 0x400 * channel) = 0x389abcd;</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x4214 + 0x400 * channel) = 0x20e42;</span><br><span> </span><br><span> /* DRAM command RD */</span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x4228 + 0x400 * channel, 0x1f105);</span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x4238 + 0x400 * channel,</span><br><span style="color: hsl(0, 100%, 40%);">- 0x4001020 | (max(ctrl->tRTP, 8) << 16));</span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x4208 + 0x400 * channel,</span><br><span style="color: hsl(0, 100%, 40%);">- (slotrank << 24));</span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x4248 + 0x400 * channel, 0x389abcd);</span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x4218 + 0x400 * channel, 0x20e42);</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x4228 + 0x400 * channel) = 0x1f105;</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x4238 + 0x400 * channel) =</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x4001020 | (max(ctrl->tRTP, 8) << 16);</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x4208 + 0x400 * channel) = (slotrank << 24);</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x4248 + 0x400 * channel) = 0x389abcd;</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x4218 + 0x400 * channel) = 0x20e42;</span><br><span> </span><br><span> /* DRAM command PRE */</span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x422c + 0x400 * channel, 0x1f002);</span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x423c + 0x400 * channel, 0xf1001);</span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x420c + 0x400 * channel,</span><br><span style="color: hsl(0, 100%, 40%);">- (slotrank << 24) | 0x60400);</span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x421c + 0x400 * channel, 0x240);</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x422c + 0x400 * channel) = 0x1f002;</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x423c + 0x400 * channel) = 0xf1001;</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x420c + 0x400 * channel) = (slotrank << 24) | 0x60400;</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x421c + 0x400 * channel) = 0x240;</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x4284 + 0x400 * channel, 0xc0001);</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x4284 + 0x400 * channel) = 0xc0001;</span><br><span> wait_428c(channel);</span><br><span> FOR_ALL_LANES {</span><br><span style="color: hsl(0, 100%, 40%);">- u32 r32 =</span><br><span style="color: hsl(0, 100%, 40%);">- read32(DEFAULT_MCHBAR + 0x4340 + 4 * lane +</span><br><span style="color: hsl(0, 100%, 40%);">- 0x400 * channel);</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 r32 = MCHBAR32(0x4340 + 4 * lane + 0x400 * channel);</span><br><span> </span><br><span> if (r32 == 0)</span><br><span> lanes_ok |= 1 << lane;</span><br><span>@@ -2221,23 +2161,21 @@</span><br><span> slotrank = !(ctrl->rankmap[channel] & 1) ? 2 : 0;</span><br><span> </span><br><span> /* DRAM command ZQCS */</span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x4220 + 0x400 * channel, 0x0f003);</span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x4230 + 0x400 * channel, 0x41001);</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x4220 + 0x400 * channel) = 0x0f003;</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x4230 + 0x400 * channel) = 0x41001;</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x4200 + 0x400 * channel,</span><br><span style="color: hsl(0, 100%, 40%);">- (slotrank << 24) | 0x60000);</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x4200 + 0x400 * channel) = (slotrank << 24) | 0x60000;</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x4210 + 0x400 * channel, 0x3e0);</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x4210 + 0x400 * channel) = 0x3e0;</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x4284 + 0x400 * channel, 1);</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x4284 + 0x400 * channel) = 1;</span><br><span> wait_428c(channel);</span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x4020 + 0x400 * channel,</span><br><span style="color: hsl(0, 100%, 40%);">- read32(DEFAULT_MCHBAR + 0x4020 +</span><br><span style="color: hsl(0, 100%, 40%);">- 0x400 * channel) | 0x200000);</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x4020 + 0x400 * channel) =</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x4020 + 0x400 * channel) | 0x200000;</span><br><span> }</span><br><span> </span><br><span> /* refresh disable */</span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x5030, read32(DEFAULT_MCHBAR + 0x5030) & ~8);</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x5030) = MCHBAR32(0x5030) & ~8;</span><br><span> FOR_ALL_POPULATED_CHANNELS {</span><br><span> wait_428c(channel);</span><br><span> </span><br><span>@@ -2245,15 +2183,14 @@</span><br><span> slotrank = !(ctrl->rankmap[channel] & 1) ? 2 : 0;</span><br><span> </span><br><span> /* DRAM command ZQCS */</span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x4220 + 0x400 * channel, 0x0f003);</span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x4230 + 0x400 * channel, 0x41001);</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x4220 + 0x400 * channel) = 0x0f003;</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x4230 + 0x400 * channel) = 0x41001;</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x4200 + 0x400 * channel,</span><br><span style="color: hsl(0, 100%, 40%);">- (slotrank << 24) | 0x60000);</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x4200 + 0x400 * channel) = (slotrank << 24) | 0x60000;</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x4210 + 0x400 * channel, 0x3e0);</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x4210 + 0x400 * channel) = 0x3e0;</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x4284 + 0x400 * channel, 1);</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x4284 + 0x400 * channel) = 1;</span><br><span> wait_428c(channel);</span><br><span> }</span><br><span> </span><br><span>@@ -2316,8 +2253,7 @@</span><br><span> FOR_ALL_POPULATED_RANKS {</span><br><span> struct run rn =</span><br><span> get_longest_zero_run(stat[slotrank], 255);</span><br><span style="color: hsl(0, 100%, 40%);">- ctrl->timings[channel][slotrank].val_320c =</span><br><span style="color: hsl(0, 100%, 40%);">- rn.middle - 127;</span><br><span style="color: hsl(120, 100%, 40%);">+ ctrl->timings[channel][slotrank].val_320c = rn.middle - 127;</span><br><span> printram("cmd_stretch: %d, %d: 0x%02x-0x%02x-0x%02x\n",</span><br><span> channel, slotrank, rn.start, rn.middle, rn.end);</span><br><span> if (rn.all || rn.length < MIN_C320C_LEN) {</span><br><span>@@ -2341,7 +2277,7 @@</span><br><span> </span><br><span> FOR_ALL_POPULATED_CHANNELS {</span><br><span> fill_pattern5(ctrl, channel, 0);</span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x4288 + 0x400 * channel, 0x1f);</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x4288 + 0x400 * channel) = 0x1f;</span><br><span> }</span><br><span> </span><br><span> FOR_ALL_POPULATED_CHANNELS {</span><br><span>@@ -2405,10 +2341,9 @@</span><br><span> program_timings(ctrl, channel);</span><br><span> </span><br><span> FOR_ALL_LANES {</span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x4340 + 0x400 * channel +</span><br><span style="color: hsl(0, 100%, 40%);">- 4 * lane, 0);</span><br><span style="color: hsl(0, 100%, 40%);">- read32(DEFAULT_MCHBAR + 0x400 * channel + 4 * lane +</span><br><span style="color: hsl(0, 100%, 40%);">- 0x4140);</span><br><span style="color: hsl(120, 100%, 40%);">+ volatile u32 tmp;</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x4340 + 0x400 * channel + 4 * lane = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+ tmp = MCHBAR32(0x400 * channel + 4 * lane + 0x4140);</span><br><span> }</span><br><span> </span><br><span> wait_428c(channel);</span><br><span>@@ -2416,45 +2351,41 @@</span><br><span> * write MR3 MPR enable</span><br><span> * in this mode only RD and RDA are allowed</span><br><span> * all reads return a predefined pattern */</span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x4220 + 0x400 * channel, 0x1f000);</span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x4230 + 0x400 * channel,</span><br><span style="color: hsl(0, 100%, 40%);">- (0xc01 | (ctrl->tMOD << 16)));</span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x4200 + 0x400 * channel,</span><br><span style="color: hsl(0, 100%, 40%);">- (slotrank << 24) | 0x360004);</span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x4210 + 0x400 * channel, 0);</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x4220 + 0x400 * channel) = 0x1f000;</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x4230 + 0x400 * channel) =</span><br><span style="color: hsl(120, 100%, 40%);">+ 0xc01 | (ctrl->tMOD << 16);</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x4200 + 0x400 * channel) =</span><br><span style="color: hsl(120, 100%, 40%);">+ (slotrank << 24) | 0x360004;</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x4210 + 0x400 * channel) = 0;</span><br><span> </span><br><span> /* DRAM command RD */</span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x4224 + 0x400 * channel, 0x1f105);</span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x4234 + 0x400 * channel, 0x40411f4);</span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x4204 + 0x400 * channel,</span><br><span style="color: hsl(0, 100%, 40%);">- (slotrank << 24));</span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x4214 + 0x400 * channel, 0);</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x4224 + 0x400 * channel) = 0x1f105;</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x4234 + 0x400 * channel) = 0x40411f4;</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x4204 + 0x400 * channel) = slotrank << 24;</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x4214 + 0x400 * channel) = 0;</span><br><span> </span><br><span> /* DRAM command RD */</span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x4228 + 0x400 * channel, 0x1f105);</span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x4238 + 0x400 * channel,</span><br><span style="color: hsl(0, 100%, 40%);">- 0x1001 | ((ctrl->CAS + 8) << 16));</span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x4208 + 0x400 * channel,</span><br><span style="color: hsl(0, 100%, 40%);">- (slotrank << 24) | 0x60000);</span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x4218 + 0x400 * channel, 0);</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x4228 + 0x400 * channel) = 0x1f105;</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x4238 + 0x400 * channel) =</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x1001 | ((ctrl->CAS + 8) << 16);</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x4208 + 0x400 * channel) = (slotrank << 24) | 0x60000;</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x4218 + 0x400 * channel) = 0;</span><br><span> </span><br><span> /* DRAM command MRS</span><br><span> * MR3 disable MPR */</span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x422c + 0x400 * channel, 0x1f000);</span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x423c + 0x400 * channel,</span><br><span style="color: hsl(0, 100%, 40%);">- (0xc01 | (ctrl->tMOD << 16)));</span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x420c + 0x400 * channel,</span><br><span style="color: hsl(0, 100%, 40%);">- (slotrank << 24) | 0x360000);</span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x421c + 0x400 * channel, 0);</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x422c + 0x400 * channel) = 0x1f000;</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x423c + 0x400 * channel) = 0xc01 | (ctrl->tMOD << 16);</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x420c + 0x400 * channel) =</span><br><span style="color: hsl(120, 100%, 40%);">+ (slotrank << 24) | 0x360000;</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x421c + 0x400 * channel) = 0;</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x4284 + 0x400 * channel, 0xc0001);</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x4284 + 0x400 * channel) = 0xc0001;</span><br><span> </span><br><span> wait_428c(channel);</span><br><span> </span><br><span> FOR_ALL_LANES {</span><br><span> statistics[lane][edge] =</span><br><span style="color: hsl(0, 100%, 40%);">- read32(DEFAULT_MCHBAR + 0x4340 + 0x400 * channel +</span><br><span style="color: hsl(0, 100%, 40%);">- lane * 4);</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x4340 + 0x400 * channel + lane * 4);</span><br><span> }</span><br><span> }</span><br><span> FOR_ALL_LANES {</span><br><span>@@ -2479,21 +2410,20 @@</span><br><span> int channel, slotrank, lane;</span><br><span> int err;</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x3400, 0);</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x3400) = 0;</span><br><span> </span><br><span> toggle_io_reset();</span><br><span> </span><br><span> FOR_ALL_POPULATED_CHANNELS FOR_ALL_LANES {</span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 4 * lane +</span><br><span style="color: hsl(0, 100%, 40%);">- 0x400 * channel + 0x4080, 0);</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(4 * lane + 0x400 * channel + 0x4080) = 0;</span><br><span> }</span><br><span> </span><br><span> FOR_ALL_POPULATED_CHANNELS {</span><br><span> fill_pattern0(ctrl, channel, 0, 0);</span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x4288 + (channel << 10), 0);</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x4288 + (channel << 10)) = 0;</span><br><span> FOR_ALL_LANES {</span><br><span style="color: hsl(0, 100%, 40%);">- read32(DEFAULT_MCHBAR + 0x400 * channel +</span><br><span style="color: hsl(0, 100%, 40%);">- lane * 4 + 0x4140);</span><br><span style="color: hsl(120, 100%, 40%);">+ volatile u32 tmp;</span><br><span style="color: hsl(120, 100%, 40%);">+ tmp = MCHBAR32(0x400 * channel + lane * 4 + 0x4140);</span><br><span> }</span><br><span> </span><br><span> FOR_ALL_POPULATED_RANKS FOR_ALL_LANES {</span><br><span>@@ -2513,43 +2443,37 @@</span><br><span> * write MR3 MPR enable</span><br><span> * in this mode only RD and RDA are allowed</span><br><span> * all reads return a predefined pattern */</span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x4220 + 0x400 * channel,</span><br><span style="color: hsl(0, 100%, 40%);">- 0x1f000);</span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x4230 + 0x400 * channel,</span><br><span style="color: hsl(0, 100%, 40%);">- 0xc01 | (ctrl->tMOD << 16));</span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x4200 + 0x400 * channel,</span><br><span style="color: hsl(0, 100%, 40%);">- (slotrank << 24) | 0x360004);</span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x4210 + 0x400 * channel, 0);</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x4220 + 0x400 * channel) = 0x1f000;</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x4230 + 0x400 * channel) =</span><br><span style="color: hsl(120, 100%, 40%);">+ 0xc01 | (ctrl->tMOD << 16);</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x4200 + 0x400 * channel) =</span><br><span style="color: hsl(120, 100%, 40%);">+ (slotrank << 24) | 0x360004;</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x4210 + 0x400 * channel) = 0;</span><br><span> </span><br><span> /* DRAM command RD */</span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x4224 + 0x400 * channel,</span><br><span style="color: hsl(0, 100%, 40%);">- 0x1f105);</span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x4234 + 0x400 * channel,</span><br><span style="color: hsl(0, 100%, 40%);">- 0x4041003);</span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x4204 + 0x400 * channel,</span><br><span style="color: hsl(0, 100%, 40%);">- (slotrank << 24) | 0);</span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x4214 + 0x400 * channel, 0);</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x4224 + 0x400 * channel) = 0x1f105;</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x4234 + 0x400 * channel) = 0x4041003;</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x4204 + 0x400 * channel) =</span><br><span style="color: hsl(120, 100%, 40%);">+ (slotrank << 24) | 0;</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x4214 + 0x400 * channel) = 0;</span><br><span> </span><br><span> /* DRAM command RD */</span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x4228 + 0x400 * channel,</span><br><span style="color: hsl(0, 100%, 40%);">- 0x1f105);</span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x4238 + 0x400 * channel,</span><br><span style="color: hsl(0, 100%, 40%);">- 0x1001 | ((ctrl->CAS + 8) << 16));</span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x4208 + 0x400 * channel,</span><br><span style="color: hsl(0, 100%, 40%);">- (slotrank << 24) | 0x60000);</span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x4218 + 0x400 * channel, 0);</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x4228 + 0x400 * channel) = 0x1f105;</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x4238 + 0x400 * channel) =</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x1001 | ((ctrl->CAS + 8) << 16);</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x4208 + 0x400 * channel) =</span><br><span style="color: hsl(120, 100%, 40%);">+ (slotrank << 24) | 0x60000;</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x4218 + 0x400 * channel) = 0;</span><br><span> </span><br><span> /* DRAM command MRS</span><br><span> * MR3 disable MPR */</span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x422c + 0x400 * channel,</span><br><span style="color: hsl(0, 100%, 40%);">- 0x1f000);</span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x423c + 0x400 * channel,</span><br><span style="color: hsl(0, 100%, 40%);">- 0xc01 | (ctrl->tMOD << 16));</span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x420c + 0x400 * channel,</span><br><span style="color: hsl(0, 100%, 40%);">- (slotrank << 24) | 0x360000);</span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x421c + 0x400 * channel, 0);</span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x4284 + 0x400 * channel,</span><br><span style="color: hsl(0, 100%, 40%);">- 0xc0001);</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x422c + 0x400 * channel) = 0x1f000;</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x423c + 0x400 * channel) =</span><br><span style="color: hsl(120, 100%, 40%);">+ 0xc01 | (ctrl->tMOD << 16);</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x420c + 0x400 * channel) =</span><br><span style="color: hsl(120, 100%, 40%);">+ (slotrank << 24) | 0x360000;</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x421c + 0x400 * channel) = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x4284 + 0x400 * channel) = 0xc0001;</span><br><span> </span><br><span> wait_428c(channel);</span><br><span> }</span><br><span>@@ -2573,72 +2497,65 @@</span><br><span> * write MR3 MPR enable</span><br><span> * in this mode only RD and RDA are allowed</span><br><span> * all reads return a predefined pattern */</span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x4220 + 0x400 * channel,</span><br><span style="color: hsl(0, 100%, 40%);">- 0x1f000);</span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x4230 + 0x400 * channel,</span><br><span style="color: hsl(0, 100%, 40%);">- 0xc01 | (ctrl->tMOD << 16));</span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x4200 + 0x400 * channel,</span><br><span style="color: hsl(0, 100%, 40%);">- (slotrank << 24) | 0x360004);</span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x4210 + 0x400 * channel, 0);</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x4220 + 0x400 * channel) = 0x1f000;</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x4230 + 0x400 * channel) =</span><br><span style="color: hsl(120, 100%, 40%);">+ 0xc01 | (ctrl->tMOD << 16);</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x4200 + 0x400 * channel) =</span><br><span style="color: hsl(120, 100%, 40%);">+ (slotrank << 24) | 0x360004;</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x4210 + 0x400 * channel) = 0;</span><br><span> </span><br><span> /* DRAM command RD */</span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x4224 + 0x400 * channel,</span><br><span style="color: hsl(0, 100%, 40%);">- 0x1f105);</span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x4234 + 0x400 * channel,</span><br><span style="color: hsl(0, 100%, 40%);">- 0x4041003);</span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x4204 + 0x400 * channel,</span><br><span style="color: hsl(0, 100%, 40%);">- (slotrank << 24) | 0);</span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x4214 + 0x400 * channel, 0);</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x4224 + 0x400 * channel) = 0x1f105;</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x4234 + 0x400 * channel) = 0x4041003;</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x4204 + 0x400 * channel) =</span><br><span style="color: hsl(120, 100%, 40%);">+ (slotrank << 24) | 0;</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x4214 + 0x400 * channel) = 0;</span><br><span> </span><br><span> /* DRAM command RD */</span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x4228 + 0x400 * channel,</span><br><span style="color: hsl(0, 100%, 40%);">- 0x1f105);</span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x4238 + 0x400 * channel,</span><br><span style="color: hsl(0, 100%, 40%);">- 0x1001 | ((ctrl->CAS + 8) << 16));</span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x4208 + 0x400 * channel,</span><br><span style="color: hsl(0, 100%, 40%);">- (slotrank << 24) | 0x60000);</span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x4218 + 0x400 * channel, 0);</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x4228 + 0x400 * channel) = 0x1f105;</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x4238 + 0x400 * channel) =</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x1001 | ((ctrl->CAS + 8) << 16);</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x4208 + 0x400 * channel) =</span><br><span style="color: hsl(120, 100%, 40%);">+ (slotrank << 24) | 0x60000;</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x4218 + 0x400 * channel) = 0;</span><br><span> </span><br><span> /* DRAM command MRS</span><br><span> * MR3 disable MPR */</span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x422c + 0x400 * channel,</span><br><span style="color: hsl(0, 100%, 40%);">- 0x1f000);</span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x423c + 0x400 * channel,</span><br><span style="color: hsl(0, 100%, 40%);">- 0xc01 | (ctrl->tMOD << 16));</span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x420c + 0x400 * channel,</span><br><span style="color: hsl(0, 100%, 40%);">- (slotrank << 24) | 0x360000);</span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x421c + 0x400 * channel, 0);</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x422c + 0x400 * channel) = 0x1f000;</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x423c + 0x400 * channel) =</span><br><span style="color: hsl(120, 100%, 40%);">+ 0xc01 | (ctrl->tMOD << 16);</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x420c + 0x400 * channel) =</span><br><span style="color: hsl(120, 100%, 40%);">+ (slotrank << 24) | 0x360000;</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x421c + 0x400 * channel) = 0;</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x4284 + 0x400 * channel,</span><br><span style="color: hsl(0, 100%, 40%);">- 0xc0001);</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x4284 + 0x400 * channel) = 0xc0001;</span><br><span> wait_428c(channel);</span><br><span> }</span><br><span> </span><br><span> /* XXX: check any measured value ? */</span><br><span> </span><br><span> FOR_ALL_LANES {</span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x4080 + 0x400 * channel +</span><br><span style="color: hsl(0, 100%, 40%);">- lane * 4,</span><br><span style="color: hsl(0, 100%, 40%);">- ~read32(DEFAULT_MCHBAR + 0x4040 +</span><br><span style="color: hsl(0, 100%, 40%);">- 0x400 * channel + lane * 4) & 0xff);</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x4080 + 0x400 * channel + lane * 4) =</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x4040 + 0x400 * channel + lane * 4)</span><br><span style="color: hsl(120, 100%, 40%);">+ & 0xff;</span><br><span> }</span><br><span> </span><br><span> fill_pattern0(ctrl, channel, 0, 0xffffffff);</span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x4288 + (channel << 10), 0);</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x4288 + (channel << 10)) = 0;</span><br><span> }</span><br><span> </span><br><span> /* FIXME: under some conditions (older chipsets?) vendor BIOS sets both edges to the same value. */</span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x4eb0, 0x300);</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x4eb0) = 0x300;</span><br><span> printram("discover falling edges:\n[%x] = %x\n", 0x4eb0, 0x300);</span><br><span> </span><br><span> FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS {</span><br><span> err = discover_edges_real(ctrl, channel, slotrank,</span><br><span style="color: hsl(0, 100%, 40%);">- falling_edges[channel][slotrank]);</span><br><span style="color: hsl(120, 100%, 40%);">+ falling_edges[channel][slotrank]);</span><br><span> if (err)</span><br><span> return err;</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x4eb0, 0x200);</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x4eb0) = 0x200;</span><br><span> printram("discover rising edges:\n[%x] = %x\n", 0x4eb0, 0x200);</span><br><span> </span><br><span> FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS {</span><br><span>@@ -2648,7 +2565,7 @@</span><br><span> return err;</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x4eb0, 0);</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x4eb0) = 0;</span><br><span> </span><br><span> FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS FOR_ALL_LANES {</span><br><span> ctrl->timings[channel][slotrank].lanes[lane].falling =</span><br><span>@@ -2662,8 +2579,7 @@</span><br><span> }</span><br><span> </span><br><span> FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS FOR_ALL_LANES {</span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x4080 + 0x400 * channel + 4 * lane,</span><br><span style="color: hsl(0, 100%, 40%);">- 0);</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x4080 + 0x400 * channel + 4 * lane) = 0;</span><br><span> }</span><br><span> return 0;</span><br><span> }</span><br><span>@@ -2679,6 +2595,7 @@</span><br><span> int lower[NUM_LANES];</span><br><span> int upper[NUM_LANES];</span><br><span> int pat;</span><br><span style="color: hsl(120, 100%, 40%);">+ volatile u32 tmp;</span><br><span> </span><br><span> FOR_ALL_LANES {</span><br><span> lower[lane] = 0;</span><br><span>@@ -2686,13 +2603,12 @@</span><br><span> }</span><br><span> </span><br><span> for (i = 0; i < 3; i++) {</span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x3000 + 0x100 * channel,</span><br><span style="color: hsl(0, 100%, 40%);">- reg3000b24[i] << 24);</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x3000 + 0x100 * channel) = reg3000b24[i] << 24;</span><br><span> printram("[%x] = 0x%08x\n",</span><br><span> 0x3000 + 0x100 * channel, reg3000b24[i] << 24);</span><br><span> for (pat = 0; pat < NUM_PATTERNS; pat++) {</span><br><span> fill_pattern5(ctrl, channel, pat);</span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x4288 + 0x400 * channel, 0x1f);</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x4288 + 0x400 * channel) = 0x1f;</span><br><span> printram("using pattern %d\n", pat);</span><br><span> for (edge = 0; edge <= MAX_EDGE_TIMING; edge++) {</span><br><span> FOR_ALL_LANES {</span><br><span>@@ -2704,60 +2620,51 @@</span><br><span> program_timings(ctrl, channel);</span><br><span> </span><br><span> FOR_ALL_LANES {</span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x4340 +</span><br><span style="color: hsl(0, 100%, 40%);">- 0x400 * channel + 4 * lane, 0);</span><br><span style="color: hsl(0, 100%, 40%);">- read32(DEFAULT_MCHBAR + 0x400 * channel +</span><br><span style="color: hsl(0, 100%, 40%);">- 4 * lane + 0x4140);</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x4340 + 0x400 * channel +</span><br><span style="color: hsl(120, 100%, 40%);">+ 4 * lane) = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+ tmp = MCHBAR32(0x400 * channel +</span><br><span style="color: hsl(120, 100%, 40%);">+ 4 * lane + 0x4140);</span><br><span> }</span><br><span> wait_428c(channel);</span><br><span> </span><br><span> /* DRAM command ACT */</span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x4220 + 0x400 * channel,</span><br><span style="color: hsl(0, 100%, 40%);">- 0x1f006);</span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x4230 + 0x400 * channel,</span><br><span style="color: hsl(0, 100%, 40%);">- 0x4 | (ctrl->tRCD << 16)</span><br><span style="color: hsl(0, 100%, 40%);">- | (max(ctrl->tRRD, (ctrl->tFAW >> 2) + 1) <<</span><br><span style="color: hsl(0, 100%, 40%);">- 10));</span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x4200 + 0x400 * channel,</span><br><span style="color: hsl(0, 100%, 40%);">- (slotrank << 24) | 0x60000);</span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x4210 + 0x400 * channel,</span><br><span style="color: hsl(0, 100%, 40%);">- 0x240);</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x4220 + 0x400 * channel) = 0x1f006;</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x4230 + 0x400 * channel) =</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x4 | (ctrl->tRCD << 16) |</span><br><span style="color: hsl(120, 100%, 40%);">+ (max(ctrl->tRRD, (ctrl->tFAW >> 2) + 1)</span><br><span style="color: hsl(120, 100%, 40%);">+ << 10);</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x4200 + 0x400 * channel) =</span><br><span style="color: hsl(120, 100%, 40%);">+ (slotrank << 24) | 0x60000;</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x4210 + 0x400 * channel) = 0x240;</span><br><span> </span><br><span> /* DRAM command WR */</span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x4224 + 0x400 * channel,</span><br><span style="color: hsl(0, 100%, 40%);">- 0x1f201);</span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x4234 + 0x400 * channel,</span><br><span style="color: hsl(0, 100%, 40%);">- 0x8005020 | ((ctrl->tWTR + ctrl->CWL + 8) <<</span><br><span style="color: hsl(0, 100%, 40%);">- 16));</span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x4204 + 0x400 * channel,</span><br><span style="color: hsl(0, 100%, 40%);">- (slotrank << 24));</span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x4214 + 0x400 * channel,</span><br><span style="color: hsl(0, 100%, 40%);">- 0x242);</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x4224 + 0x400 * channel) = 0x1f201;</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x4234 + 0x400 * channel) = 0x8005020 |</span><br><span style="color: hsl(120, 100%, 40%);">+ ((ctrl->tWTR + ctrl->CWL + 8) << 16);</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x4204 + 0x400 * channel) =</span><br><span style="color: hsl(120, 100%, 40%);">+ slotrank << 24;</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x4214 + 0x400 * channel) = 0x242;</span><br><span> </span><br><span> /* DRAM command RD */</span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x4228 + 0x400 * channel,</span><br><span style="color: hsl(0, 100%, 40%);">- 0x1f105);</span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x4238 + 0x400 * channel,</span><br><span style="color: hsl(0, 100%, 40%);">- 0x4005020 | (max(ctrl->tRTP, 8) << 16));</span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x4208 + 0x400 * channel,</span><br><span style="color: hsl(0, 100%, 40%);">- (slotrank << 24));</span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x4218 + 0x400 * channel,</span><br><span style="color: hsl(0, 100%, 40%);">- 0x242);</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x4228 + 0x400 * channel) = 0x1f105;</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x4238 + 0x400 * channel) =</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x4005020 | (max(ctrl->tRTP, 8) << 16);</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x4208 + 0x400 * channel) =</span><br><span style="color: hsl(120, 100%, 40%);">+ slotrank << 24;</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x4218 + 0x400 * channel) = 0x242;</span><br><span> </span><br><span> /* DRAM command PRE */</span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x422c + 0x400 * channel,</span><br><span style="color: hsl(0, 100%, 40%);">- 0x1f002);</span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x423c + 0x400 * channel,</span><br><span style="color: hsl(0, 100%, 40%);">- 0xc01 | (ctrl->tRP << 16));</span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x420c + 0x400 * channel,</span><br><span style="color: hsl(0, 100%, 40%);">- (slotrank << 24) | 0x60400);</span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x421c + 0x400 * channel, 0);</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x422c + 0x400 * channel) = 0x1f002;</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x423c + 0x400 * channel) =</span><br><span style="color: hsl(120, 100%, 40%);">+ 0xc01 | (ctrl->tRP << 16);</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x420c + 0x400 * channel) =</span><br><span style="color: hsl(120, 100%, 40%);">+ (slotrank << 24) | 0x60400;</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x421c + 0x400 * channel) = 0;</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x4284 + 0x400 * channel,</span><br><span style="color: hsl(0, 100%, 40%);">- 0xc0001);</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x4284 + 0x400 * channel) = 0xc0001;</span><br><span> wait_428c(channel);</span><br><span> FOR_ALL_LANES {</span><br><span style="color: hsl(0, 100%, 40%);">- read32(DEFAULT_MCHBAR + 0x4340 +</span><br><span style="color: hsl(120, 100%, 40%);">+ tmp = MCHBAR32(0x4340 +</span><br><span> 0x400 * channel + lane * 4);</span><br><span> }</span><br><span> </span><br><span>@@ -2789,7 +2696,7 @@</span><br><span> }</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x3000, 0);</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x3000) = 0;</span><br><span> printram("CPA\n");</span><br><span> return 0;</span><br><span> }</span><br><span>@@ -2802,7 +2709,7 @@</span><br><span> int err;</span><br><span> </span><br><span> /* FIXME: under some conditions (older chipsets?) vendor BIOS sets both edges to the same value. */</span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x4eb0, 0x300);</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x4eb0) = 0x300;</span><br><span> printram("discover falling edges write:\n[%x] = %x\n", 0x4eb0, 0x300);</span><br><span> </span><br><span> FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS {</span><br><span>@@ -2812,7 +2719,7 @@</span><br><span> return err;</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x4eb0, 0x200);</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x4eb0) = 0x200;</span><br><span> printram("discover rising edges write:\n[%x] = %x\n", 0x4eb0, 0x200);</span><br><span> </span><br><span> FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS {</span><br><span>@@ -2822,7 +2729,7 @@</span><br><span> return err;</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x4eb0, 0);</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x4eb0) = 0;</span><br><span> </span><br><span> FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS FOR_ALL_LANES {</span><br><span> ctrl->timings[channel][slotrank].lanes[lane].falling =</span><br><span>@@ -2835,8 +2742,7 @@</span><br><span> program_timings(ctrl, channel);</span><br><span> </span><br><span> FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS FOR_ALL_LANES {</span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x4080 + 0x400 * channel + 4 * lane,</span><br><span style="color: hsl(0, 100%, 40%);">- 0);</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x4080 + 0x400 * channel + 4 * lane) = 0;</span><br><span> }</span><br><span> return 0;</span><br><span> }</span><br><span>@@ -2845,49 +2751,35 @@</span><br><span> {</span><br><span> wait_428c(channel);</span><br><span> /* DRAM command ACT */</span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x4220 + 0x400 * channel, 0x1f006);</span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x4230 + 0x400 * channel,</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x4220 + 0x400 * channel) = 0x1f006;</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x4230 + 0x400 * channel) =</span><br><span> (max((ctrl->tFAW >> 2) + 1, ctrl->tRRD)</span><br><span style="color: hsl(0, 100%, 40%);">- << 10) | (ctrl->tRCD << 16) | 4);</span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x4200 + 0x400 * channel,</span><br><span style="color: hsl(0, 100%, 40%);">- (slotrank << 24) | 0x60000);</span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x4210 + 0x400 * channel, 0x244);</span><br><span style="color: hsl(120, 100%, 40%);">+ << 10) | (ctrl->tRCD << 16) | 4;</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x4200 + 0x400 * channel) =</span><br><span style="color: hsl(120, 100%, 40%);">+ (slotrank << 24) | 0x60000;</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x4210 + 0x400 * channel) = 0x244;</span><br><span> </span><br><span> /* DRAM command WR */</span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x4224 + 0x400 * channel, 0x1f201);</span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x4234 + 0x400 * channel,</span><br><span style="color: hsl(0, 100%, 40%);">- 0x80011e0 |</span><br><span style="color: hsl(0, 100%, 40%);">- ((ctrl->tWTR + ctrl->CWL + 8) << 16));</span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x4204 +</span><br><span style="color: hsl(0, 100%, 40%);">- 0x400 * channel, (slotrank << 24));</span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x4214 +</span><br><span style="color: hsl(0, 100%, 40%);">- 0x400 * channel, 0x242);</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x4224 + 0x400 * channel) = 0x1f201;</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x4234 + 0x400 * channel) =</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x80011e0 | ((ctrl->tWTR + ctrl->CWL + 8) << 16);</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x4204 + 0x400 * channel) = slotrank << 24;</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x4214 + 0x400 * channel) = 0x242;</span><br><span> </span><br><span> /* DRAM command RD */</span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x4228 +</span><br><span style="color: hsl(0, 100%, 40%);">- 0x400 * channel, 0x1f105);</span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x4238 +</span><br><span style="color: hsl(0, 100%, 40%);">- 0x400 * channel,</span><br><span style="color: hsl(0, 100%, 40%);">- 0x40011e0 | (max(ctrl->tRTP, 8) << 16));</span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x4208 +</span><br><span style="color: hsl(0, 100%, 40%);">- 0x400 * channel, (slotrank << 24));</span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x4218 +</span><br><span style="color: hsl(0, 100%, 40%);">- 0x400 * channel, 0x242);</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x4228 + 0x400 * channel) = 0x1f105;</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x4238 + 0x400 * channel) =</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x40011e0 | (max(ctrl->tRTP, 8) << 16);</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x4208 + 0x400 * channel) = slotrank << 24;</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x4218 + 0x400 * channel) = 0x242;</span><br><span> </span><br><span> /* DRAM command PRE */</span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x422c +</span><br><span style="color: hsl(0, 100%, 40%);">- 0x400 * channel, 0x1f002);</span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x423c +</span><br><span style="color: hsl(0, 100%, 40%);">- 0x400 * channel,</span><br><span style="color: hsl(0, 100%, 40%);">- 0x1001 | (ctrl->tRP << 16));</span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x420c +</span><br><span style="color: hsl(0, 100%, 40%);">- 0x400 * channel,</span><br><span style="color: hsl(0, 100%, 40%);">- (slotrank << 24) | 0x60400);</span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x421c +</span><br><span style="color: hsl(0, 100%, 40%);">- 0x400 * channel, 0);</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x422c + 0x400 * channel) = 0x1f002;</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x423c + 0x400 * channel) = 0x1001 | (ctrl->tRP << 16);</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x420c + 0x400 * channel) = (slotrank << 24) | 0x60400;</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x421c + 0x400 * channel) = 0;</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x4284 +</span><br><span style="color: hsl(0, 100%, 40%);">- 0x400 * channel, 0xc0001);</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x4284 + 0x400 * channel) = 0xc0001;</span><br><span> wait_428c(channel);</span><br><span> }</span><br><span> </span><br><span>@@ -2905,15 +2797,15 @@</span><br><span> upper[channel][slotrank][lane] = MAX_TIMC;</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x4ea8, 1);</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x4ea8) = 1;</span><br><span> printram("discover timC write:\n");</span><br><span> </span><br><span> for (i = 0; i < 3; i++)</span><br><span> FOR_ALL_POPULATED_CHANNELS {</span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0xe3c + (channel * 0x100),</span><br><span style="color: hsl(0, 100%, 40%);">- (rege3c_b24[i] << 24)</span><br><span style="color: hsl(0, 100%, 40%);">- | (read32(DEFAULT_MCHBAR + 0xe3c + (channel * 0x100))</span><br><span style="color: hsl(0, 100%, 40%);">- & ~0x3f000000));</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0xe3c + (channel * 0x100)) =</span><br><span style="color: hsl(120, 100%, 40%);">+ (rege3c_b24[i] << 24) |</span><br><span style="color: hsl(120, 100%, 40%);">+ (MCHBAR32(0xe3c + (channel * 0x100))</span><br><span style="color: hsl(120, 100%, 40%);">+ & ~0x3f000000)</span><br><span> udelay(2);</span><br><span> for (pat = 0; pat < NUM_PATTERNS; pat++) {</span><br><span> FOR_ALL_POPULATED_RANKS {</span><br><span>@@ -2925,7 +2817,8 @@</span><br><span> statistics[MAX_TIMC] = 1;</span><br><span> </span><br><span> fill_pattern5(ctrl, channel, pat);</span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x4288 + 0x400 * channel, 0x1f);</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x4288 + 0x400 * channel) =</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x1f;</span><br><span> for (timC = 0; timC < MAX_TIMC; timC++) {</span><br><span> FOR_ALL_LANES</span><br><span> ctrl->timings[channel][slotrank].lanes[lane].timC = timC;</span><br><span>@@ -2968,13 +2861,12 @@</span><br><span> }</span><br><span> </span><br><span> FOR_ALL_CHANNELS {</span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + (channel * 0x100) + 0xe3c,</span><br><span style="color: hsl(0, 100%, 40%);">- 0 | (read32(DEFAULT_MCHBAR + (channel * 0x100) + 0xe3c) &</span><br><span style="color: hsl(0, 100%, 40%);">- ~0x3f000000));</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32((channel * 0x100) + 0xe3c) =</span><br><span style="color: hsl(120, 100%, 40%);">+ 0 | (MCHBAR32((channel * 0x100) + 0xe3c) & ~0x3f000000);</span><br><span> udelay(2);</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x4ea8, 0);</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x4ea8) = 0;</span><br><span> </span><br><span> printram("CPB\n");</span><br><span> </span><br><span>@@ -3024,11 +2916,10 @@</span><br><span> int channel, slotrank;</span><br><span> </span><br><span> FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS {</span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x0004 + (channel << 8) +</span><br><span style="color: hsl(0, 100%, 40%);">- lane_registers[slotrank], make_mr0(ctrl, slotrank));</span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x0008 + (channel << 8) +</span><br><span style="color: hsl(0, 100%, 40%);">- lane_registers[slotrank],</span><br><span style="color: hsl(0, 100%, 40%);">- make_mr1(ctrl, slotrank, channel));</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x0004 + (channel << 8) + lane_registers[slotrank]) =</span><br><span style="color: hsl(120, 100%, 40%);">+ make_mr0(ctrl, slotrank);</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x0008 + (channel << 8) + lane_registers[slotrank]) =</span><br><span style="color: hsl(120, 100%, 40%);">+ make_mr1(ctrl, slotrank, channel);</span><br><span> }</span><br><span> }</span><br><span> </span><br><span>@@ -3038,7 +2929,7 @@</span><br><span> </span><br><span> slotrank = 0;</span><br><span> FOR_ALL_POPULATED_CHANNELS</span><br><span style="color: hsl(0, 100%, 40%);">- if (read32(DEFAULT_MCHBAR + 0x42a0 + (channel << 10)) & 0xa000) {</span><br><span style="color: hsl(120, 100%, 40%);">+ if (MCHBAR32(0x42a0 + (channel << 10)) & 0xa000) {</span><br><span> printk(BIOS_EMERG, "Mini channel test failed (1): %d\n",</span><br><span> channel);</span><br><span> return MAKE_ERR;</span><br><span>@@ -3046,45 +2937,45 @@</span><br><span> FOR_ALL_POPULATED_CHANNELS {</span><br><span> fill_pattern0(ctrl, channel, 0x12345678, 0x98765432);</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x4288 + (channel << 10), 0);</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x4288 + (channel << 10)) = 0;</span><br><span> }</span><br><span> </span><br><span> for (slotrank = 0; slotrank < 4; slotrank++)</span><br><span> FOR_ALL_CHANNELS</span><br><span> if (ctrl->rankmap[channel] & (1 << slotrank)) {</span><br><span> FOR_ALL_LANES {</span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + (0x4f40 + 4 * lane), 0);</span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + (0x4d40 + 4 * lane), 0);</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x4f40 + 4 * lane) = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x4d40 + 4 * lane) = 0;</span><br><span> }</span><br><span> wait_428c(channel);</span><br><span> /* DRAM command ACT */</span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x4220 + (channel << 10), 0x0001f006);</span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x4230 + (channel << 10), 0x0028a004);</span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x4200 + (channel << 10),</span><br><span style="color: hsl(0, 100%, 40%);">- 0x00060000 | (slotrank << 24));</span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x4210 + (channel << 10), 0x00000244);</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x4220 + (channel << 10)) = 0x0001f006;</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x4230 + (channel << 10)) = 0x0028a004;</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x4200 + (channel << 10)) =</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x00060000 | (slotrank << 24);</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x4210 + (channel << 10)) = 0x00000244;</span><br><span> /* DRAM command WR */</span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x4224 + (channel << 10), 0x0001f201);</span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x4234 + (channel << 10), 0x08281064);</span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x4204 + (channel << 10),</span><br><span style="color: hsl(0, 100%, 40%);">- 0x00000000 | (slotrank << 24));</span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x4214 + (channel << 10), 0x00000242);</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x4224 + (channel << 10)) = 0x0001f201;</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x4234 + (channel << 10)) = 0x08281064;</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x4204 + (channel << 10)) =</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x00000000 | (slotrank << 24);</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x4214 + (channel << 10)) = 0x00000242;</span><br><span> /* DRAM command RD */</span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x4228 + (channel << 10), 0x0001f105);</span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x4238 + (channel << 10), 0x04281064);</span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x4208 + (channel << 10),</span><br><span style="color: hsl(0, 100%, 40%);">- 0x00000000 | (slotrank << 24));</span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x4218 + (channel << 10), 0x00000242);</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x4228 + (channel << 10)) = 0x0001f105;</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x4238 + (channel << 10)) = 0x04281064;</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x4208 + (channel << 10)) =</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x00000000 | (slotrank << 24);</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x4218 + (channel << 10)) = 0x00000242;</span><br><span> /* DRAM command PRE */</span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x422c + (channel << 10), 0x0001f002);</span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x423c + (channel << 10), 0x00280c01);</span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x420c + (channel << 10),</span><br><span style="color: hsl(0, 100%, 40%);">- 0x00060400 | (slotrank << 24));</span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x421c + (channel << 10), 0x00000240);</span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x4284 + (channel << 10), 0x000c0001);</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x422c + (channel << 10)) = 0x0001f002;</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x423c + (channel << 10)) = 0x00280c01;</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x420c + (channel << 10)) =</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x00060400 | (slotrank << 24);</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x421c + (channel << 10)) = 0x00000240;</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x4284 + (channel << 10)) = 0x000c0001;</span><br><span> wait_428c(channel);</span><br><span> FOR_ALL_LANES</span><br><span style="color: hsl(0, 100%, 40%);">- if (read32(DEFAULT_MCHBAR + 0x4340 + (channel << 10) + 4 * lane)) {</span><br><span style="color: hsl(120, 100%, 40%);">+ if (MCHBAR32(0x4340 + (channel << 10) + 4 * lane)) {</span><br><span> printk(BIOS_EMERG, "Mini channel test failed (2): %d, %d, %d\n",</span><br><span> channel, slotrank, lane);</span><br><span> return MAKE_ERR;</span><br><span>@@ -3167,11 +3058,11 @@</span><br><span> </span><br><span> dram_odt_stretch(ctrl, channel);</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x4008 + (channel << 10),</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x4008 + (channel << 10)) =</span><br><span> 0x0a000000</span><br><span> | (b20 << 20)</span><br><span> | ((ctrl->ref_card_offset[channel] + 2) << 16)</span><br><span style="color: hsl(0, 100%, 40%);">- | b4_8_12);</span><br><span style="color: hsl(120, 100%, 40%);">+ | b4_8_12;</span><br><span> }</span><br><span> }</span><br><span> </span><br><span>@@ -3179,8 +3070,8 @@</span><br><span> {</span><br><span> int channel;</span><br><span> FOR_ALL_POPULATED_CHANNELS {</span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + (0x42a0 + 0x400 * channel),</span><br><span style="color: hsl(0, 100%, 40%);">- 0x00001000 | ctrl->rankmap[channel]);</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x42a0 + 0x400 * channel) =</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x00001000 | ctrl->rankmap[channel];</span><br><span> MCHBAR32(0x4004 + 0x400 * channel) &= ~0x20000000; // OK</span><br><span> }</span><br><span> }</span><br><span>@@ -3198,10 +3089,10 @@</span><br><span> int t3_ns;</span><br><span> u32 r32;</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x4cd4, 0x00000046);</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x4cd4) = 0x00000046;</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x400c, (read32(DEFAULT_MCHBAR + 0x400c) & 0xFFFFCFFF) | 0x1000); // OK</span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x440c, (read32(DEFAULT_MCHBAR + 0x440c) & 0xFFFFCFFF) | 0x1000); // OK</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x400c) = (MCHBAR32(0x400c) & 0xFFFFCFFF) | 0x1000; // OK</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x440c) = (MCHBAR32(0x440c) & 0xFFFFCFFF) | 0x1000; // OK</span><br><span> </span><br><span> if (ctrl->mobile)</span><br><span> /* APD - DLL Off, 64 DCLKs until idle, decision per rank */</span><br><span>@@ -3210,40 +3101,35 @@</span><br><span> /* APD - PPD, 64 DCLKs until idle, decision per rank */</span><br><span> MCHBAR32(PM_PDWN_Config) = 0x00000340;</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x4380, 0x00000aaa); // OK</span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x4780, 0x00000aaa); // OK</span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x4f88, 0x5f7003ff); // OK</span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x5064, 0x00073000 | ctrl->reg_5064b0); // OK</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x4380) = 0x00000aaa; // OK</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x4780) = 0x00000aaa; // OK</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x4f88) = 0x5f7003ff; // OK</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x5064) = 0x00073000 | ctrl->reg_5064b0; // OK</span><br><span> </span><br><span> FOR_ALL_CHANNELS {</span><br><span> switch (ctrl->rankmap[channel]) {</span><br><span> /* Unpopulated channel. */</span><br><span> case 0:</span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x4384 + channel * 0x400, 0);</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x4384 + channel * 0x400) = 0;</span><br><span> break;</span><br><span> /* Only single-ranked dimms. */</span><br><span> case 1:</span><br><span> case 4:</span><br><span> case 5:</span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x4384 + channel * 0x400, 0x373131);</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x4384 + channel * 0x400) = 0x373131;</span><br><span> break;</span><br><span> /* Dual-ranked dimms present. */</span><br><span> default:</span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x4384 + channel * 0x400, 0x9b6ea1);</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x4384 + channel * 0x400) = 0x9b6ea1;</span><br><span> break;</span><br><span> }</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- write32 (DEFAULT_MCHBAR + 0x5880, 0xca9171e5);</span><br><span style="color: hsl(0, 100%, 40%);">- write32 (DEFAULT_MCHBAR + 0x5888,</span><br><span style="color: hsl(0, 100%, 40%);">- (read32 (DEFAULT_MCHBAR + 0x5888) & ~0xffffff) | 0xe4d5d0);</span><br><span style="color: hsl(0, 100%, 40%);">- write32 (DEFAULT_MCHBAR + 0x58a8, read32 (DEFAULT_MCHBAR + 0x58a8) & ~0x1f);</span><br><span style="color: hsl(0, 100%, 40%);">- write32 (DEFAULT_MCHBAR + 0x4294,</span><br><span style="color: hsl(0, 100%, 40%);">- (read32 (DEFAULT_MCHBAR + 0x4294) & ~0x30000)</span><br><span style="color: hsl(0, 100%, 40%);">- | (1 << 16));</span><br><span style="color: hsl(0, 100%, 40%);">- write32 (DEFAULT_MCHBAR + 0x4694,</span><br><span style="color: hsl(0, 100%, 40%);">- (read32 (DEFAULT_MCHBAR + 0x4694) & ~0x30000)</span><br><span style="color: hsl(0, 100%, 40%);">- | (1 << 16));</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x5880) = 0xca9171e5;</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x5888) = MCHBAR32(0x5888) & ~0xffffff) | 0xe4d5d0;</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x58a8) = MCHBAR32(0x58a8) & ~0x1f;</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x4294) = MCHBAR32(0x4294) & ~0x30000 | (1 << 16);</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x4694) = MCHBAR32(0x4694) & ~0x30000 | (1 << 16);</span><br><span> </span><br><span> MCHBAR32(0x5030) |= 1; // OK</span><br><span> MCHBAR32(0x5030) |= 0x80; // OK</span><br><span>@@ -3253,20 +3139,20 @@</span><br><span> FOR_ALL_POPULATED_CHANNELS</span><br><span> break;</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- t1_cycles = ((read32(DEFAULT_MCHBAR + 0x4290 + channel * 0x400) >> 8) & 0xff);</span><br><span style="color: hsl(0, 100%, 40%);">- r32 = read32(DEFAULT_MCHBAR + 0x5064);</span><br><span style="color: hsl(120, 100%, 40%);">+ t1_cycles = (MCHBAR32(0x4290 + channel * 0x400) >> 8) & 0xff;</span><br><span style="color: hsl(120, 100%, 40%);">+ r32 = MCHBAR32(0x5064);</span><br><span> if (r32 & 0x20000)</span><br><span> t1_cycles += (r32 & 0xfff);</span><br><span style="color: hsl(0, 100%, 40%);">- t1_cycles += (read32(DEFAULT_MCHBAR + channel * 0x400 + 0x42a4) & 0xfff);</span><br><span style="color: hsl(120, 100%, 40%);">+ t1_cycles += MCHBAR32(channel * 0x400 + 0x42a4) & 0xfff;</span><br><span> t1_ns = t1_cycles * ctrl->tCK / 256 + 544;</span><br><span> if (!(r32 & 0x20000))</span><br><span> t1_ns += 500;</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- t2_ns = 10 * ((read32(DEFAULT_MCHBAR + 0x5f10) >> 8) & 0xfff);</span><br><span style="color: hsl(0, 100%, 40%);">- if ( read32(DEFAULT_MCHBAR + 0x5f00) & 8 )</span><br><span style="color: hsl(120, 100%, 40%);">+ t2_ns = 10 * ((MCHBAR32(0x5f10) >> 8) & 0xfff);</span><br><span style="color: hsl(120, 100%, 40%);">+ if (MCHBAR32(0x5f00) & 8)</span><br><span> {</span><br><span style="color: hsl(0, 100%, 40%);">- t3_ns = 10 * ((read32(DEFAULT_MCHBAR + 0x5f20) >> 8) & 0xfff);</span><br><span style="color: hsl(0, 100%, 40%);">- t3_ns += 10 * (read32(DEFAULT_MCHBAR + 0x5f18) & 0xff);</span><br><span style="color: hsl(120, 100%, 40%);">+ t3_ns = 10 * ((MCHBAR32(0x5f20) >> 8) & 0xfff);</span><br><span style="color: hsl(120, 100%, 40%);">+ t3_ns += 10 * (MCHBAR32(0x5f18) & 0xff);</span><br><span> }</span><br><span> else</span><br><span> {</span><br><span>@@ -3274,12 +3160,10 @@</span><br><span> }</span><br><span> printk(BIOS_DEBUG, "t123: %d, %d, %d\n",</span><br><span> t1_ns, t2_ns, t3_ns);</span><br><span style="color: hsl(0, 100%, 40%);">- write32 (DEFAULT_MCHBAR + 0x5d10,</span><br><span style="color: hsl(0, 100%, 40%);">- ((encode_5d10(t1_ns) + encode_5d10(t2_ns)) << 16)</span><br><span style="color: hsl(0, 100%, 40%);">- | (encode_5d10(t1_ns) << 8)</span><br><span style="color: hsl(0, 100%, 40%);">- | ((encode_5d10(t3_ns) + encode_5d10(t2_ns) + encode_5d10(t1_ns)) << 24)</span><br><span style="color: hsl(0, 100%, 40%);">- | (read32(DEFAULT_MCHBAR + 0x5d10) & 0xC0C0C0C0)</span><br><span style="color: hsl(0, 100%, 40%);">- | 0xc);</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x5d10) = ((encode_5d10(t1_ns) + encode_5d10(t2_ns)) << 16) |</span><br><span style="color: hsl(120, 100%, 40%);">+ (encode_5d10(t1_ns) << 8) | ((encode_5d10(t3_ns) +</span><br><span style="color: hsl(120, 100%, 40%);">+ encode_5d10(t2_ns) + encode_5d10(t1_ns)) << 24) |</span><br><span style="color: hsl(120, 100%, 40%);">+ (MCHBAR32(0x5d10) & 0xC0C0C0C0) | 0xc;</span><br><span> }</span><br><span> </span><br><span> void restore_timings(ramctr_timing * ctrl)</span><br><span>@@ -3303,26 +3187,23 @@</span><br><span> }</span><br><span> </span><br><span> FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS FOR_ALL_LANES {</span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x4080 + 0x400 * channel</span><br><span style="color: hsl(0, 100%, 40%);">- + 4 * lane, 0);</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x4080 + 0x400 * channel + 4 * lane) = 0;</span><br><span> }</span><br><span> </span><br><span> FOR_ALL_POPULATED_CHANNELS</span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x4008 + 0x400 * channel,</span><br><span style="color: hsl(0, 100%, 40%);">- read32(DEFAULT_MCHBAR + 0x4008 +</span><br><span style="color: hsl(0, 100%, 40%);">- 0x400 * channel) | 0x8000000);</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x4008 + 0x400 * channel) =</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x4008 + 0x400 * channel) | 0x8000000;</span><br><span> </span><br><span> FOR_ALL_POPULATED_CHANNELS {</span><br><span> udelay (1);</span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x4020 + 0x400 * channel,</span><br><span style="color: hsl(0, 100%, 40%);">- read32(DEFAULT_MCHBAR + 0x4020 +</span><br><span style="color: hsl(0, 100%, 40%);">- 0x400 * channel) | 0x200000);</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x4020 + 0x400 * channel) =</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x4020 + 0x400 * channel) | 0x200000;</span><br><span> }</span><br><span> </span><br><span> printram("CPE\n");</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x3400, 0);</span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x4eb0, 0);</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x3400) = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x4eb0) = 0;</span><br><span> </span><br><span> printram("CP5b\n");</span><br><span> </span><br><span>@@ -3366,14 +3247,13 @@</span><br><span> </span><br><span> printram("CP5c\n");</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x3000, 0);</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x3000) = 0;</span><br><span> </span><br><span> FOR_ALL_CHANNELS {</span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + (channel * 0x100) + 0xe3c,</span><br><span style="color: hsl(0, 100%, 40%);">- 0 | (read32(DEFAULT_MCHBAR + (channel * 0x100) + 0xe3c) &</span><br><span style="color: hsl(0, 100%, 40%);">- ~0x3f000000));</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(channel * 0x100 + 0xe3c) =</span><br><span style="color: hsl(120, 100%, 40%);">+ 0 | (MCHBAR32(channel * 0x100 + 0xe3c) & ~0x3f000000);</span><br><span> udelay(2);</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- write32(DEFAULT_MCHBAR + 0x4ea8, 0);</span><br><span style="color: hsl(120, 100%, 40%);">+ MCHBAR32(0x4ea8) = 0;</span><br><span> }</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/27674">change 27674</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/27674"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I22f1c7dbdaf42722115d9e5913d47aa2c9dc7e9a </div>
<div style="display:none"> Gerrit-Change-Number: 27674 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Felix Held <felix-coreboot@felixheld.de> </div>