<p>Marc Jones has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/27653">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">soc/amd/stoneyridge: Add IGFX device ACPI ASL entry<br><br>Add internal graphics device 00.01.00 to the ACPI tables so that the<br>ACPI PCI option ROM save functions have a proper scope to save the<br>ROM to.<br><br>BUG=b:111697181<br>TEST=Check coreboot log doesn't have "PCI: 00:01.0: Missing ACPI scope"<br>and check _ROM method is added in the SSDT1.<br><br>Change-Id: I2c9ef8d9dff76805b1fcde2ccceef958a5b53b4f<br>Signed-off-by: Marc Jones <marcj303@gmail.com><br>---<br>M src/soc/amd/stoneyridge/acpi/northbridge.asl<br>M src/soc/amd/stoneyridge/chip.c<br>2 files changed, 7 insertions(+), 0 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/27653/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/soc/amd/stoneyridge/acpi/northbridge.asl b/src/soc/amd/stoneyridge/acpi/northbridge.asl</span><br><span>index 4df6567..fe78534 100644</span><br><span>--- a/src/soc/amd/stoneyridge/acpi/northbridge.asl</span><br><span>+++ b/src/soc/amd/stoneyridge/acpi/northbridge.asl</span><br><span>@@ -46,6 +46,11 @@</span><br><span>         Name(_ADR, 0x00000000)</span><br><span> } /* end AMRT */</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+/* Internal Graphics */</span><br><span style="color: hsl(120, 100%, 40%);">+Device(IGFX) {</span><br><span style="color: hsl(120, 100%, 40%);">+       Name(_ADR, 0x00010000)</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> /* Gpp 0 */</span><br><span> Device(PBR4) {</span><br><span>         Name(_ADR, 0x00020001)</span><br><span>diff --git a/src/soc/amd/stoneyridge/chip.c b/src/soc/amd/stoneyridge/chip.c</span><br><span>index 9ca2db7..33c1730 100644</span><br><span>--- a/src/soc/amd/stoneyridge/chip.c</span><br><span>+++ b/src/soc/amd/stoneyridge/chip.c</span><br><span>@@ -82,6 +82,8 @@</span><br><span>              return NULL;</span><br><span> </span><br><span>     switch (dev->path.pci.devfn) {</span><br><span style="color: hsl(120, 100%, 40%);">+     case GFX_DEVFN:</span><br><span style="color: hsl(120, 100%, 40%);">+               return "IGFX";</span><br><span>     case PCIE0_DEVFN:</span><br><span>            return "PBR4";</span><br><span>     case PCIE1_DEVFN:</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/27653">change 27653</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/27653"/><meta itemprop="name" content="View Change"/></div></div>

<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I2c9ef8d9dff76805b1fcde2ccceef958a5b53b4f </div>
<div style="display:none"> Gerrit-Change-Number: 27653 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Marc Jones <marc@marcjonesconsulting.com> </div>