<p>Lijian Zhao has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/27628">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">mainboard/intel/coffeelake_rvp: Add new board<br><br>Add new mainboard variant of whiskey lake rvp.<br><br>BUG=N/A<br>TEST=Build and flash, confirm boot up into kernel on whiskeylake rvp<br>platform.<br><br>Change-Id: I4a5e8a9ec76d5e55e55ef9bf968825c17fbe9816<br>Signed-off-by: Lijian Zhao <lijian.zhao@intel.com><br>---<br>M src/mainboard/intel/coffeelake_rvp/Kconfig<br>M src/mainboard/intel/coffeelake_rvp/Kconfig.name<br>M src/mainboard/intel/coffeelake_rvp/romstage.c<br>M src/mainboard/intel/coffeelake_rvp/spd/spd_util.c<br>A src/mainboard/intel/coffeelake_rvp/variants/whl_w/devicetree.cb<br>A src/mainboard/intel/coffeelake_rvp/variants/whl_w/include/variant/gpio.h<br>6 files changed, 191 insertions(+), 13 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/27628/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/mainboard/intel/coffeelake_rvp/Kconfig b/src/mainboard/intel/coffeelake_rvp/Kconfig</span><br><span>index 5bd7531..0af1723 100644</span><br><span>--- a/src/mainboard/intel/coffeelake_rvp/Kconfig</span><br><span>+++ b/src/mainboard/intel/coffeelake_rvp/Kconfig</span><br><span>@@ -1,4 +1,4 @@</span><br><span style="color: hsl(0, 100%, 40%);">-if BOARD_INTEL_COFFEELAKE_RVP11 || BOARD_INTEL_COFFEELAKE_RVPU</span><br><span style="color: hsl(120, 100%, 40%);">+if BOARD_INTEL_COFFEELAKE_RVP11 || BOARD_INTEL_COFFEELAKE_RVPU || BOARD_INTEL_WHISKEYLAKE_RVP</span><br><span> </span><br><span> config BOARD_SPECIFIC_OPTIONS</span><br><span> def_bool y</span><br><span>@@ -23,11 +23,13 @@</span><br><span> string</span><br><span> default "cfl_u" if BOARD_INTEL_COFFEELAKE_RVPU</span><br><span> default "cfl_h" if BOARD_INTEL_COFFEELAKE_RVP11</span><br><span style="color: hsl(120, 100%, 40%);">+ default "whl_w" if BOARD_INTEL_WHISKEYLAKE_RVP</span><br><span> </span><br><span> config MAINBOARD_PART_NUMBER</span><br><span> string</span><br><span> default "Coffeelake U RVP" if BOARD_INTEL_COFFEELAKE_RVPU</span><br><span> default "Coffeelake H RVP11" if BOARD_INTEL_COFFEELAKE_RVP11</span><br><span style="color: hsl(120, 100%, 40%);">+ default "Whiskeylake RVP" if BOARD_INTEL_WHISKEYLAKE_RVP</span><br><span> </span><br><span> config MAINBOARD_VENDOR</span><br><span> string</span><br><span>diff --git a/src/mainboard/intel/coffeelake_rvp/Kconfig.name b/src/mainboard/intel/coffeelake_rvp/Kconfig.name</span><br><span>index 0dc7079..9bf3ac8 100644</span><br><span>--- a/src/mainboard/intel/coffeelake_rvp/Kconfig.name</span><br><span>+++ b/src/mainboard/intel/coffeelake_rvp/Kconfig.name</span><br><span>@@ -2,3 +2,5 @@</span><br><span> bool "Coffeelake U LPDDR4 RVP"</span><br><span> config BOARD_INTEL_COFFEELAKE_RVP11</span><br><span> bool "Coffeelake H LPDDR4 RVP11"</span><br><span style="color: hsl(120, 100%, 40%);">+config BOARD_INTEL_WHISKEYLAKE_RVP</span><br><span style="color: hsl(120, 100%, 40%);">+ bool "Whiskeylake DDR4 RVP"</span><br><span>diff --git a/src/mainboard/intel/coffeelake_rvp/romstage.c b/src/mainboard/intel/coffeelake_rvp/romstage.c</span><br><span>index e0699da..9fddc8b 100644</span><br><span>--- a/src/mainboard/intel/coffeelake_rvp/romstage.c</span><br><span>+++ b/src/mainboard/intel/coffeelake_rvp/romstage.c</span><br><span>@@ -27,7 +27,6 @@</span><br><span> {</span><br><span> FSP_M_CONFIG *mem_cfg;</span><br><span> mem_cfg = &mupd->FspmConfig;</span><br><span style="color: hsl(0, 100%, 40%);">- u8 spd_index;</span><br><span> </span><br><span> mainboard_fill_dq_map_ch0(&mem_cfg->DqByteMapCh0);</span><br><span> mainboard_fill_dq_map_ch1(&mem_cfg->DqByteMapCh1);</span><br><span>@@ -36,10 +35,17 @@</span><br><span> mainboard_fill_rcomp_res_data(&mem_cfg->RcompResistor);</span><br><span> mainboard_fill_rcomp_strength_data(&mem_cfg->RcompTarget);</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- mem_cfg->DqPinsInterleaved = 0;</span><br><span style="color: hsl(0, 100%, 40%);">- mem_cfg->CaVrefConfig = 0; /* VREF_CA->CHA/CHB */</span><br><span style="color: hsl(0, 100%, 40%);">- mem_cfg->ECT = 1; /* Early Command Training Enabled */</span><br><span style="color: hsl(0, 100%, 40%);">- spd_index = 2;</span><br><span style="color: hsl(120, 100%, 40%);">+#if !IS_ENABLED(CONFIG_BOARD_INTEL_COFFEELAKE_RVPU)</span><br><span style="color: hsl(120, 100%, 40%);">+ mem_cfg->DqPinsInterleaved = 1;</span><br><span style="color: hsl(120, 100%, 40%);">+ mem_cfg->CaVrefConfig = 2; /* VREF_CA->CHA/CHB */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* TODO: Hard coding SpdAddress */</span><br><span style="color: hsl(120, 100%, 40%);">+ mem_cfg->SpdAddressTable[0] = 0xA0;</span><br><span style="color: hsl(120, 100%, 40%);">+ mem_cfg->SpdAddressTable[1] = 0xA2;</span><br><span style="color: hsl(120, 100%, 40%);">+ mem_cfg->SpdAddressTable[2] = 0xA4;</span><br><span style="color: hsl(120, 100%, 40%);">+ mem_cfg->SpdAddressTable[3] = 0xA6;</span><br><span style="color: hsl(120, 100%, 40%);">+#else</span><br><span style="color: hsl(120, 100%, 40%);">+ u8 spd_index = 2;</span><br><span> </span><br><span> struct region_device spd_rdev;</span><br><span> </span><br><span>@@ -49,6 +55,7 @@</span><br><span> mem_cfg->MemorySpdDataLen = region_device_sz(&spd_rdev);</span><br><span> /* Memory leak is ok since we have memory mapped boot media */</span><br><span> mem_cfg->MemorySpdPtr00 = (uintptr_t)rdev_mmap_full(&spd_rdev);</span><br><span style="color: hsl(0, 100%, 40%);">- mem_cfg->RefClk = 0; /* Auto Select CLK freq */</span><br><span> mem_cfg->MemorySpdPtr10 = mem_cfg->MemorySpdPtr00;</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+ mem_cfg->SafeMode = 0;</span><br><span> }</span><br><span>diff --git a/src/mainboard/intel/coffeelake_rvp/spd/spd_util.c b/src/mainboard/intel/coffeelake_rvp/spd/spd_util.c</span><br><span>index c6f9511..48575ab 100644</span><br><span>--- a/src/mainboard/intel/coffeelake_rvp/spd/spd_util.c</span><br><span>+++ b/src/mainboard/intel/coffeelake_rvp/spd/spd_util.c</span><br><span>@@ -31,11 +31,18 @@</span><br><span> </span><br><span> void mainboard_fill_dq_map_ch1(void *dq_map_ptr)</span><br><span> {</span><br><span style="color: hsl(0, 100%, 40%);">- const u8 dq_map[12] = {</span><br><span style="color: hsl(120, 100%, 40%);">+ const u8 dq_map_u[12] = {</span><br><span> 0x0F, 0xF0, 0x0F, 0xF0, 0xFF, 0x00,</span><br><span> 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 };</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- memcpy(dq_map_ptr, dq_map, sizeof(dq_map));</span><br><span style="color: hsl(120, 100%, 40%);">+ const u8 dq_map_h[12] = {</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x33, 0xCC, 0x00, 0xCC, 0x33, 0xCC,</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x33, 0x00, 0xFF, 0x00, 0xFF, 0x00 };</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ if (IS_ENABLED(CONFIG_BOARD_INTEL_COFFEELAKE_RVPU))</span><br><span style="color: hsl(120, 100%, 40%);">+ memcpy(dq_map_ptr, dq_map_u, sizeof(dq_map_u));</span><br><span style="color: hsl(120, 100%, 40%);">+ else</span><br><span style="color: hsl(120, 100%, 40%);">+ memcpy(dq_map_ptr, dq_map_h, sizeof(dq_map_h));</span><br><span> }</span><br><span> </span><br><span> void mainboard_fill_dqs_map_ch0(void *dqs_map_ptr)</span><br><span>@@ -43,12 +50,12 @@</span><br><span> /* DQS CPU<>DRAM map Ch0 */</span><br><span> const u8 dqs_map_u[8] = { 0, 3, 2, 1, 5, 6, 7, 4 };</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- const u8 dqs_map_y[8] = { 2, 0, 3, 1, 6, 5, 7, 4 };</span><br><span style="color: hsl(120, 100%, 40%);">+ const u8 dqs_map_h[8] = { 0, 1, 3, 2, 4, 5, 6, 7 };</span><br><span> </span><br><span> if (IS_ENABLED(CONFIG_BOARD_INTEL_COFFEELAKE_RVPU))</span><br><span> memcpy(dqs_map_ptr, dqs_map_u, sizeof(dqs_map_u));</span><br><span> else</span><br><span style="color: hsl(0, 100%, 40%);">- memcpy(dqs_map_ptr, dqs_map_y, sizeof(dqs_map_y));</span><br><span style="color: hsl(120, 100%, 40%);">+ memcpy(dqs_map_ptr, dqs_map_h, sizeof(dqs_map_h));</span><br><span> }</span><br><span> </span><br><span> void mainboard_fill_dqs_map_ch1(void *dqs_map_ptr)</span><br><span>@@ -56,12 +63,12 @@</span><br><span> /* DQS CPU<>DRAM map Ch1 */</span><br><span> const u8 dqs_map_u[8] = { 3, 0, 1, 2, 5, 6, 4, 7 };</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- const u8 dqs_map_y[8] = { 3, 1, 2, 0, 4, 5, 6, 7 };</span><br><span style="color: hsl(120, 100%, 40%);">+ const u8 dqs_map_h[8] = { 1, 0, 4, 5, 3, 2, 6, 7 };</span><br><span> </span><br><span> if (IS_ENABLED(CONFIG_BOARD_INTEL_COFFEELAKE_RVPU))</span><br><span> memcpy(dqs_map_ptr, dqs_map_u, sizeof(dqs_map_u));</span><br><span> else</span><br><span style="color: hsl(0, 100%, 40%);">- memcpy(dqs_map_ptr, dqs_map_y, sizeof(dqs_map_y));</span><br><span style="color: hsl(120, 100%, 40%);">+ memcpy(dqs_map_ptr, dqs_map_h, sizeof(dqs_map_h));</span><br><span> }</span><br><span> </span><br><span> void mainboard_fill_rcomp_res_data(void *rcomp_ptr)</span><br><span>diff --git a/src/mainboard/intel/coffeelake_rvp/variants/whl_w/devicetree.cb b/src/mainboard/intel/coffeelake_rvp/variants/whl_w/devicetree.cb</span><br><span>new file mode 100644</span><br><span>index 0000000..62a6635</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/intel/coffeelake_rvp/variants/whl_w/devicetree.cb</span><br><span>@@ -0,0 +1,139 @@</span><br><span style="color: hsl(120, 100%, 40%);">+chip soc/intel/cannonlake</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ device cpu_cluster 0 on</span><br><span style="color: hsl(120, 100%, 40%);">+ device lapic 0 on end</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ # FSP configuration</span><br><span style="color: hsl(120, 100%, 40%);">+ register "SaGv" = "3"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "SmbusEnable" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "ScsEmmcEnabled" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "ScsEmmcHs400Enabled" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "ScsSdCardEnabled" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "HeciEnabled" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC0)"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "usb2_ports[1]" = "USB2_PORT_MID(OC0)"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "usb2_ports[2]" = "USB2_PORT_MID(OC0)"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "usb2_ports[3]" = "USB2_PORT_MID(OC0)"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "usb2_ports[4]" = "USB2_PORT_MID(OC0)"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "usb2_ports[5]" = "USB2_PORT_MID(OC0)"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "usb2_ports[6]" = "USB2_PORT_MID(OC0)"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "usb2_ports[7]" = "USB2_PORT_MID(OC0)"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "usb2_ports[8]" = "USB2_PORT_MID(OC0)"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "usb2_ports[9]" = "USB2_PORT_MID(OC0)"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC0)"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC0)"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC0)"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC0)"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC0)"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ register "SataEnable" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "SataSalpSupport" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "SataPortsEnable[0]" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "SataPortsEnable[1]" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "SataPortsEnable[2]" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "SataPortsEnable[3]" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "SataPortsEnable[4]" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "SataPortsEnable[5]" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "SataPortsEnable[6]" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "SataPortsEnable[7]" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PchHdaDspEnable" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PchHdaAudioLinkHda" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieRpEnable[0]" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieRpEnable[1]" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieRpEnable[2]" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieRpEnable[3]" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieRpEnable[4]" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieRpEnable[5]" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieRpEnable[6]" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieRpEnable[7]" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieRpEnable[8]" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieRpEnable[9]" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieRpEnable[10]" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieRpEnable[11]" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieRpEnable[12]" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieRpEnable[13]" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieRpEnable[14]" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieRpEnable[15]" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieClkSrcUsage[0]" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieClkSrcUsage[1]" = "8"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieClkSrcUsage[2]" = "PCIE_CLK_LAN"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieClkSrcUsage[3]" = "13"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieClkSrcUsage[4]" = "4"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieClkSrcUsage[5]" = "14"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieClkSrcClkReq[0]" = "0"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieClkSrcClkReq[1]" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieClkSrcClkReq[2]" = "2"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieClkSrcClkReq[3]" = "3"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieClkSrcClkReq[4]" = "4"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieClkSrcClkReq[5]" = "5"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ # Enable "Intel Speed Shift Technology"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "speed_shift_enable" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ # GPIO for SD card detect</span><br><span style="color: hsl(120, 100%, 40%);">+ register "sdcard_cd_gpio" = "GPP_G5"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ device domain 0 on</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 00.0 on end # Host Bridge</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 02.0 on end # Integrated Graphics Device</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 04.0 on end # SA Thermal device</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 12.0 on end # Thermal Subsystem</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 12.5 off end # UFS SCS</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 12.6 off end # GSPI #2</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 14.0 on end # USB xHCI</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 14.1 off end # USB xDCI (OTG)</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 14.3 on end # CNVi wifi</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 14.5 on end # SDCard</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 15.0 on end # I2C #0</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 15.1 on end # I2C #1</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 15.2 off end # I2C #2</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 15.3 off end # I2C #3</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 16.0 on end # Management Engine Interface 1</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 16.1 off end # Management Engine Interface 2</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 16.2 off end # Management Engine IDE-R</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 16.3 off end # Management Engine KT Redirection</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 16.4 off end # Management Engine Interface 3</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 16.5 off end # Management Engine Interface 4</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 17.0 on end # SATA</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 19.0 on end # I2C #4</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 19.1 off end # I2C #5</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 19.2 on end # UART #2</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1a.0 on end # eMMC</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1c.0 on end # PCI Express Port 1 x4 SLOT1</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1c.4 on end # PCI Express Port 5 x1 SLOT2/LAN</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1c.5 off end # PCI Express Port 6</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1c.6 off end # PCI Express Port 7</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1c.7 off end # PCI Express Port 8</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1d.0 on end # PCI Express Port 9</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1d.1 off end # PCI Express Port 10</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1d.2 off end # PCI Express Port 11</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1d.3 off end # PCI Express Port 12</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1d.4 off end # PCI Express Port 13</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1d.5 off end # PCI Express Port 14</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1d.6 off end # PCI Express Port 15</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1d.7 off end # PCI Express Port 16</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1e.0 on end # UART #0</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1e.1 off end # UART #1</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1e.2 off end # GSPI #0</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1e.3 off end # GSPI #1</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1f.0 on</span><br><span style="color: hsl(120, 100%, 40%);">+ chip drivers/pc80/tpm</span><br><span style="color: hsl(120, 100%, 40%);">+ device pnp 0c31.0 on end</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ end # LPC Interface</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1f.1 on end # P2SB</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1f.2 on end # Power Management Controller</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1f.3 on end # Intel HDA</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1f.4 on end # SMBus</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1f.5 on end # PCH SPI</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1f.6 off end # GbE</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+end</span><br><span>diff --git a/src/mainboard/intel/coffeelake_rvp/variants/whl_w/include/variant/gpio.h b/src/mainboard/intel/coffeelake_rvp/variants/whl_w/include/variant/gpio.h</span><br><span>new file mode 100644</span><br><span>index 0000000..4b6f579</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/intel/coffeelake_rvp/variants/whl_w/include/variant/gpio.h</span><br><span>@@ -0,0 +1,21 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright 2017 Intel Corporation.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef __MAINBOARD_GPIO_H__</span><br><span style="color: hsl(120, 100%, 40%);">+#define __MAINBOARD_GPIO_H__</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <baseboard/gpio.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#endif /* __MAINBOARD_GPIO_H__ */</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/27628">change 27628</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/27628"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I4a5e8a9ec76d5e55e55ef9bf968825c17fbe9816 </div>
<div style="display:none"> Gerrit-Change-Number: 27628 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Lijian Zhao <lijian.zhao@intel.com> </div>