<p><a href="https://review.coreboot.org/15164">View Change</a></p><p>75 comments:</p><ul style="list-style: none; padding: 0;"><li style="margin: 0; padding: 0;"><p><a href="https://review.coreboot.org/#/c/15164/17/src/northbridge/amd/pi/00730F01/northbridge.c">File src/northbridge/amd/pi/00730F01/northbridge.c:</a></p><ul style="list-style: none; padding: 0;"><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/15164/17/src/northbridge/amd/pi/00730F01/northbridge.c@457">Patch Set #17, Line 457:</a> <code style="font-family:monospace,monospace"> if ((dev->bus->secondary == 0x0) && (dev->path.pci.devfn == 0x0)) {</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/15164/17/src/northbridge/amd/pi/00730F01/northbridge.c@457">Patch Set #17, Line 457:</a> <code style="font-family:monospace,monospace"> if ((dev->bus->secondary == 0x0) && (dev->path.pci.devfn == 0x0)) {</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">braces {} are not necessary for single statement blocks</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/15164/17/src/northbridge/amd/pi/00730F01/northbridge.c@466">Patch Set #17, Line 466:</a> <code style="font-family:monospace,monospace"> p[0] = 0x2; /* Entry type */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/15164/17/src/northbridge/amd/pi/00730F01/northbridge.c@467">Patch Set #17, Line 467:</a> <code style="font-family:monospace,monospace"> p[1] = dev->path.pci.devfn; /* Device */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/15164/17/src/northbridge/amd/pi/00730F01/northbridge.c@468">Patch Set #17, Line 468:</a> <code style="font-family:monospace,monospace"> p[2] = dev->bus->secondary; /* Bus */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/15164/17/src/northbridge/amd/pi/00730F01/northbridge.c@469">Patch Set #17, Line 469:</a> <code style="font-family:monospace,monospace"> p[3] = 0x0; /* Data */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/15164/17/src/northbridge/amd/pi/00730F01/northbridge.c@470">Patch Set #17, Line 470:</a> <code style="font-family:monospace,monospace"> p[4] = 0x0; /* Padding */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/15164/17/src/northbridge/amd/pi/00730F01/northbridge.c@471">Patch Set #17, Line 471:</a> <code style="font-family:monospace,monospace"> p[5] = 0x0; /* Padding */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/15164/17/src/northbridge/amd/pi/00730F01/northbridge.c@472">Patch Set #17, Line 472:</a> <code style="font-family:monospace,monospace"> p[6] = 0x0; /* Padding */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/15164/17/src/northbridge/amd/pi/00730F01/northbridge.c@473">Patch Set #17, Line 473:</a> <code style="font-family:monospace,monospace"> p[7] = 0x0; /* Padding */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/15164/17/src/northbridge/amd/pi/00730F01/northbridge.c@480">Patch Set #17, Line 480:</a> <code style="font-family:monospace,monospace"> && (dev->path.pci.devfn < (0x3 << 3))) {</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/15164/17/src/northbridge/amd/pi/00730F01/northbridge.c@483">Patch Set #17, Line 483:</a> <code style="font-family:monospace,monospace"> p[0] = 0x2; /* Entry type */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/15164/17/src/northbridge/amd/pi/00730F01/northbridge.c@484">Patch Set #17, Line 484:</a> <code style="font-family:monospace,monospace"> p[1] = dev->path.pci.devfn; /* Device */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/15164/17/src/northbridge/amd/pi/00730F01/northbridge.c@485">Patch Set #17, Line 485:</a> <code style="font-family:monospace,monospace"> p[2] = dev->bus->secondary; /* Bus */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/15164/17/src/northbridge/amd/pi/00730F01/northbridge.c@486">Patch Set #17, Line 486:</a> <code style="font-family:monospace,monospace"> p[3] = 0x0; /* Data */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/15164/17/src/northbridge/amd/pi/00730F01/northbridge.c@487">Patch Set #17, Line 487:</a> <code style="font-family:monospace,monospace"> p[4] = 0x0; /* Padding */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/15164/17/src/northbridge/amd/pi/00730F01/northbridge.c@488">Patch Set #17, Line 488:</a> <code style="font-family:monospace,monospace"> p[5] = 0x0; /* Padding */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/15164/17/src/northbridge/amd/pi/00730F01/northbridge.c@489">Patch Set #17, Line 489:</a> <code style="font-family:monospace,monospace"> p[6] = 0x0; /* Padding */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/15164/17/src/northbridge/amd/pi/00730F01/northbridge.c@490">Patch Set #17, Line 490:</a> <code style="font-family:monospace,monospace"> p[7] = 0x0; /* Padding */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/15164/17/src/northbridge/amd/pi/00730F01/northbridge.c@496">Patch Set #17, Line 496:</a> <code style="font-family:monospace,monospace"> p[0] = 0x2; /* Entry type */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/15164/17/src/northbridge/amd/pi/00730F01/northbridge.c@497">Patch Set #17, Line 497:</a> <code style="font-family:monospace,monospace"> p[1] = dev->path.pci.devfn; /* Device */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/15164/17/src/northbridge/amd/pi/00730F01/northbridge.c@498">Patch Set #17, Line 498:</a> <code style="font-family:monospace,monospace"> p[2] = dev->bus->secondary; /* Bus */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/15164/17/src/northbridge/amd/pi/00730F01/northbridge.c@499">Patch Set #17, Line 499:</a> <code style="font-family:monospace,monospace"> p[3] = 0x97; /* Data */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/15164/17/src/northbridge/amd/pi/00730F01/northbridge.c@500">Patch Set #17, Line 500:</a> <code style="font-family:monospace,monospace"> p[4] = 0x0; /* Padding */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/15164/17/src/northbridge/amd/pi/00730F01/northbridge.c@501">Patch Set #17, Line 501:</a> <code style="font-family:monospace,monospace"> p[5] = 0x0; /* Padding */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/15164/17/src/northbridge/amd/pi/00730F01/northbridge.c@502">Patch Set #17, Line 502:</a> <code style="font-family:monospace,monospace"> p[6] = 0x0; /* Padding */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/15164/17/src/northbridge/amd/pi/00730F01/northbridge.c@503">Patch Set #17, Line 503:</a> <code style="font-family:monospace,monospace"> p[7] = 0x0; /* Padding */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/15164/17/src/northbridge/amd/pi/00730F01/northbridge.c@509">Patch Set #17, Line 509:</a> <code style="font-family:monospace,monospace"> p[0] = 0x2; /* Entry type */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/15164/17/src/northbridge/amd/pi/00730F01/northbridge.c@510">Patch Set #17, Line 510:</a> <code style="font-family:monospace,monospace"> p[1] = dev->path.pci.devfn; /* Device */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/15164/17/src/northbridge/amd/pi/00730F01/northbridge.c@511">Patch Set #17, Line 511:</a> <code style="font-family:monospace,monospace"> p[2] = dev->bus->secondary; /* Bus */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/15164/17/src/northbridge/amd/pi/00730F01/northbridge.c@512">Patch Set #17, Line 512:</a> <code style="font-family:monospace,monospace"> p[3] = 0x0; /* Data */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/15164/17/src/northbridge/amd/pi/00730F01/northbridge.c@513">Patch Set #17, Line 513:</a> <code style="font-family:monospace,monospace"> p[4] = 0x0; /* Padding */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/15164/17/src/northbridge/amd/pi/00730F01/northbridge.c@514">Patch Set #17, Line 514:</a> <code style="font-family:monospace,monospace"> p[5] = 0x0; /* Padding */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/15164/17/src/northbridge/amd/pi/00730F01/northbridge.c@515">Patch Set #17, Line 515:</a> <code style="font-family:monospace,monospace"> p[6] = 0x0; /* Padding */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/15164/17/src/northbridge/amd/pi/00730F01/northbridge.c@516">Patch Set #17, Line 516:</a> <code style="font-family:monospace,monospace"> p[7] = 0x0; /* Padding */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/15164/17/src/northbridge/amd/pi/00730F01/northbridge.c@521">Patch Set #17, Line 521:</a> <code style="font-family:monospace,monospace"> if ((dev->hdr_type & 0x7f) == PCI_HEADER_TYPE_NORMAL) {</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/15164/17/src/northbridge/amd/pi/00730F01/northbridge.c@523">Patch Set #17, Line 523:</a> <code style="font-family:monospace,monospace"> if (pci_find_capability(dev, PCI_CAP_ID_PCIE)) {</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/15164/17/src/northbridge/amd/pi/00730F01/northbridge.c@526">Patch Set #17, Line 526:</a> <code style="font-family:monospace,monospace"> p[0] = 0x2; /* Entry type */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/15164/17/src/northbridge/amd/pi/00730F01/northbridge.c@527">Patch Set #17, Line 527:</a> <code style="font-family:monospace,monospace"> p[1] = dev->path.pci.devfn; /* Device */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/15164/17/src/northbridge/amd/pi/00730F01/northbridge.c@528">Patch Set #17, Line 528:</a> <code style="font-family:monospace,monospace"> p[2] = dev->bus->secondary; /* Bus */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/15164/17/src/northbridge/amd/pi/00730F01/northbridge.c@529">Patch Set #17, Line 529:</a> <code style="font-family:monospace,monospace"> p[3] = 0x0; /* Data */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/15164/17/src/northbridge/amd/pi/00730F01/northbridge.c@530">Patch Set #17, Line 530:</a> <code style="font-family:monospace,monospace"> p[4] = 0x0; /* Padding */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/15164/17/src/northbridge/amd/pi/00730F01/northbridge.c@531">Patch Set #17, Line 531:</a> <code style="font-family:monospace,monospace"> p[5] = 0x0; /* Padding */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/15164/17/src/northbridge/amd/pi/00730F01/northbridge.c@532">Patch Set #17, Line 532:</a> <code style="font-family:monospace,monospace"> p[6] = 0x0; /* Padding */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/15164/17/src/northbridge/amd/pi/00730F01/northbridge.c@533">Patch Set #17, Line 533:</a> <code style="font-family:monospace,monospace"> p[7] = 0x0; /* Padding */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/15164/17/src/northbridge/amd/pi/00730F01/northbridge.c@537">Patch Set #17, Line 537:</a> <code style="font-family:monospace,monospace"> /* Device is legacy PCI or PCI-X */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/15164/17/src/northbridge/amd/pi/00730F01/northbridge.c@539">Patch Set #17, Line 539:</a> <code style="font-family:monospace,monospace"> p[0] = 0x42; /* Entry type */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/15164/17/src/northbridge/amd/pi/00730F01/northbridge.c@540">Patch Set #17, Line 540:</a> <code style="font-family:monospace,monospace"> p[1] = dev->path.pci.devfn; /* Device */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/15164/17/src/northbridge/amd/pi/00730F01/northbridge.c@541">Patch Set #17, Line 541:</a> <code style="font-family:monospace,monospace"> p[2] = dev->bus->secondary; /* Bus */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/15164/17/src/northbridge/amd/pi/00730F01/northbridge.c@542">Patch Set #17, Line 542:</a> <code style="font-family:monospace,monospace"> p[3] = 0x0; /* Data */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/15164/17/src/northbridge/amd/pi/00730F01/northbridge.c@543">Patch Set #17, Line 543:</a> <code style="font-family:monospace,monospace"> p[4] = 0x0; /* Reserved */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/15164/17/src/northbridge/amd/pi/00730F01/northbridge.c@544">Patch Set #17, Line 544:</a> <code style="font-family:monospace,monospace"> p[5] = parent->path.pci.devfn; /* Device */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/15164/17/src/northbridge/amd/pi/00730F01/northbridge.c@545">Patch Set #17, Line 545:</a> <code style="font-family:monospace,monospace"> p[6] = parent->bus->secondary; /* Bus */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/15164/17/src/northbridge/amd/pi/00730F01/northbridge.c@546">Patch Set #17, Line 546:</a> <code style="font-family:monospace,monospace"> p[7] = 0x0; /* Reserved */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/15164/17/src/northbridge/amd/pi/00730F01/northbridge.c@550">Patch Set #17, Line 550:</a> <code style="font-family:monospace,monospace"> } else if ((dev->hdr_type & 0x7f) == PCI_HEADER_TYPE_BRIDGE) {</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/15164/17/src/northbridge/amd/pi/00730F01/northbridge.c@551">Patch Set #17, Line 551:</a> <code style="font-family:monospace,monospace"> if (pci_find_capability(dev, PCI_CAP_ID_PCIE)) {</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/15164/17/src/northbridge/amd/pi/00730F01/northbridge.c@554">Patch Set #17, Line 554:</a> <code style="font-family:monospace,monospace"> p[0] = 0x2; /* Entry type */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/15164/17/src/northbridge/amd/pi/00730F01/northbridge.c@555">Patch Set #17, Line 555:</a> <code style="font-family:monospace,monospace"> p[1] = dev->path.pci.devfn; /* Device */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/15164/17/src/northbridge/amd/pi/00730F01/northbridge.c@556">Patch Set #17, Line 556:</a> <code style="font-family:monospace,monospace"> p[2] = dev->bus->secondary; /* Bus */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/15164/17/src/northbridge/amd/pi/00730F01/northbridge.c@557">Patch Set #17, Line 557:</a> <code style="font-family:monospace,monospace"> p[3] = 0x0; /* Data */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/15164/17/src/northbridge/amd/pi/00730F01/northbridge.c@558">Patch Set #17, Line 558:</a> <code style="font-family:monospace,monospace"> p[4] = 0x0; /* Padding */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/15164/17/src/northbridge/amd/pi/00730F01/northbridge.c@559">Patch Set #17, Line 559:</a> <code style="font-family:monospace,monospace"> p[5] = 0x0; /* Padding */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/15164/17/src/northbridge/amd/pi/00730F01/northbridge.c@560">Patch Set #17, Line 560:</a> <code style="font-family:monospace,monospace"> p[6] = 0x0; /* Padding */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/15164/17/src/northbridge/amd/pi/00730F01/northbridge.c@561">Patch Set #17, Line 561:</a> <code style="font-family:monospace,monospace"> p[7] = 0x0; /* Padding */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/15164/17/src/northbridge/amd/pi/00730F01/northbridge.c@571">Patch Set #17, Line 571:</a> <code style="font-family:monospace,monospace"> for (sibling = link->children; sibling; sibling = sibling->sibling)</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/15164/17/src/northbridge/amd/pi/00730F01/northbridge.c@572">Patch Set #17, Line 572:</a> <code style="font-family:monospace,monospace"> add_ivrs_device_entries(dev, sibling, depth + 1, depth, root_level, current, length);</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/15164/17/src/northbridge/amd/pi/00730F01/northbridge.c@577">Patch Set #17, Line 577:</a> <code style="font-family:monospace,monospace">unsigned long acpi_fill_ivrs_ioapic(acpi_ivrs_t* ivrs, unsigned long current)</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">"foo* bar" should be "foo *bar"</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/15164/17/src/northbridge/amd/pi/00730F01/northbridge.c@614">Patch Set #17, Line 614:</a> <code style="font-family:monospace,monospace">static unsigned long acpi_fill_ivrs(acpi_ivrs_t* ivrs, unsigned long current)</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">"foo* bar" should be "foo *bar"</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/15164/17/src/northbridge/amd/pi/00730F01/northbridge.c@620">Patch Set #17, Line 620:</a> <code style="font-family:monospace,monospace"> printk(BIOS_WARNING, "acpi_fill_ivrs: Unable to locate G-series northbridge device! IVRS table not generated...\n");</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">Prefer using '"%s...", __func__' to using 'acpi_fill_ivrs', this function's name, in a string</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/15164/17/src/northbridge/amd/pi/00730F01/northbridge.c@625">Patch Set #17, Line 625:</a> <code style="font-family:monospace,monospace"> ivrs->iv_info |= (0x40 << 15); /* Maximum supported virtual address size */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/15164/17/src/northbridge/amd/pi/00730F01/northbridge.c@626">Patch Set #17, Line 626:</a> <code style="font-family:monospace,monospace"> ivrs->iv_info |= (0x30 << 8); /* Maximum supported physical address size */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/15164/17/src/northbridge/amd/pi/00730F01/northbridge.c@631">Patch Set #17, Line 631:</a> <code style="font-family:monospace,monospace"> ivrs->ivhd.flags |= 0x10; /* Enable ATS support */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/15164/17/src/northbridge/amd/pi/00730F01/northbridge.c@633">Patch Set #17, Line 633:</a> <code style="font-family:monospace,monospace"> ivrs->ivhd.device_id = 0x2 | (nb_dev->bus->secondary << 8); /* BDF <bus>:00.2 */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/15164/17/src/northbridge/amd/pi/00730F01/northbridge.c@634">Patch Set #17, Line 634:</a> <code style="font-family:monospace,monospace"> ivrs->ivhd.capability_offset = 0x40; /* Capability block 0x40 (type 0xf, "Secure device") */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/15164/17/src/northbridge/amd/pi/00730F01/northbridge.c@656">Patch Set #17, Line 656:</a> <code style="font-family:monospace,monospace"> add_ivrs_device_entries(NULL, all_devices, 0, -1, NULL, ¤t, &ivrs->ivhd.length);</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li></ul></li></ul><p>To view, visit <a href="https://review.coreboot.org/15164">change 15164</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/15164"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
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<div style="display:none"> Gerrit-Change-Id: I1ae789f75363435accd14a1b556e1570f43f94c4 </div>
<div style="display:none"> Gerrit-Change-Number: 15164 </div>
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<div style="display:none"> Gerrit-Comment-Date: Tue, 24 Jul 2018 14:07:51 +0000 </div>
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