<p>Arthur Heymans has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/27618">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">[NOTFORMERGE]mb/gigabyte/m57sli: Add mainboard<br><br>This board used to reside in the coreboot tree but with amdk8 support. This<br>attempts to port it to the amdfam10 codebase.<br><br>Currently it gets to the payload but seems to have problems loading the OS from<br>SATA disks. Needs further testing...<br><br>Change-Id: I20a437f6952d9f919ad186d4862ca00853d9ebca<br>Signed-off-by: Arthur Heymans <arthur@aheymans.xyz><br>---<br>A src/mainboard/gigabyte/m57sli/Kconfig<br>A src/mainboard/gigabyte/m57sli/Kconfig.name<br>A src/mainboard/gigabyte/m57sli/Makefile.inc<br>A src/mainboard/gigabyte/m57sli/acpi_tables.c<br>A src/mainboard/gigabyte/m57sli/board_info.txt<br>A src/mainboard/gigabyte/m57sli/cmos.default<br>A src/mainboard/gigabyte/m57sli/cmos.layout<br>A src/mainboard/gigabyte/m57sli/devicetree.cb<br>A src/mainboard/gigabyte/m57sli/dsdt.asl<br>A src/mainboard/gigabyte/m57sli/fanctl.c<br>A src/mainboard/gigabyte/m57sli/get_bus_conf.c<br>A src/mainboard/gigabyte/m57sli/hda_verb.c<br>A src/mainboard/gigabyte/m57sli/irq_tables.c<br>A src/mainboard/gigabyte/m57sli/mptable.c<br>A src/mainboard/gigabyte/m57sli/resourcemap.c<br>A src/mainboard/gigabyte/m57sli/romstage.c<br>M src/mainboard/gigabyte/ma78gm/romstage.c<br>17 files changed, 1,680 insertions(+), 10 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/18/27618/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/mainboard/gigabyte/m57sli/Kconfig b/src/mainboard/gigabyte/m57sli/Kconfig</span><br><span>new file mode 100644</span><br><span>index 0000000..179e5c3</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/gigabyte/m57sli/Kconfig</span><br><span>@@ -0,0 +1,59 @@</span><br><span style="color: hsl(120, 100%, 40%);">+if BOARD_GIGABYTE_M57SLI</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+config BOARD_SPECIFIC_OPTIONS # dummy</span><br><span style="color: hsl(120, 100%, 40%);">+ def_bool y</span><br><span style="color: hsl(120, 100%, 40%);">+ select CPU_AMD_SOCKET_AM2R2</span><br><span style="color: hsl(120, 100%, 40%);">+ select DIMM_DDR2</span><br><span style="color: hsl(120, 100%, 40%);">+ select NORTHBRIDGE_AMD_AMDFAM10</span><br><span style="color: hsl(120, 100%, 40%);">+ select SOUTHBRIDGE_NVIDIA_MCP55</span><br><span style="color: hsl(120, 100%, 40%);">+ select MCP55_USE_NIC</span><br><span style="color: hsl(120, 100%, 40%);">+ select MCP55_USE_AZA</span><br><span style="color: hsl(120, 100%, 40%);">+ select SUPERIO_ITE_IT8716F</span><br><span style="color: hsl(120, 100%, 40%);">+ select SUPERIO_ITE_IT8716F_OVERRIDE_FANCTL</span><br><span style="color: hsl(120, 100%, 40%);">+ select HAVE_OPTION_TABLE</span><br><span style="color: hsl(120, 100%, 40%);">+ select HAVE_CMOS_DEFAULT</span><br><span style="color: hsl(120, 100%, 40%);">+ select HAVE_PIRQ_TABLE</span><br><span style="color: hsl(120, 100%, 40%);">+ select HAVE_MP_TABLE</span><br><span style="color: hsl(120, 100%, 40%);">+ select LIFT_BSP_APIC_ID</span><br><span style="color: hsl(120, 100%, 40%);">+ select HAVE_ACPI_TABLES</span><br><span style="color: hsl(120, 100%, 40%);">+ select BOARD_ROMSIZE_KB_512</span><br><span style="color: hsl(120, 100%, 40%);">+ select SET_FIDVID</span><br><span style="color: hsl(120, 100%, 40%);">+ select ENABLE_APIC_EXT_ID</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+config MAINBOARD_DIR</span><br><span style="color: hsl(120, 100%, 40%);">+ string</span><br><span style="color: hsl(120, 100%, 40%);">+ default gigabyte/m57sli</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+config APIC_ID_OFFSET</span><br><span style="color: hsl(120, 100%, 40%);">+ hex</span><br><span style="color: hsl(120, 100%, 40%);">+ default 0x0</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+config MAINBOARD_PART_NUMBER</span><br><span style="color: hsl(120, 100%, 40%);">+ string</span><br><span style="color: hsl(120, 100%, 40%);">+ default "GA-M57SLI-S4"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+config MAX_CPUS</span><br><span style="color: hsl(120, 100%, 40%);">+ int</span><br><span style="color: hsl(120, 100%, 40%);">+ default 8</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+config MAX_PHYSICAL_CPUS</span><br><span style="color: hsl(120, 100%, 40%);">+ int</span><br><span style="color: hsl(120, 100%, 40%);">+ default 1</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+config HT_CHAIN_UNITID_BASE</span><br><span style="color: hsl(120, 100%, 40%);">+ hex</span><br><span style="color: hsl(120, 100%, 40%);">+ default 0x0</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+config HT_CHAIN_END_UNITID_BASE</span><br><span style="color: hsl(120, 100%, 40%);">+ hex</span><br><span style="color: hsl(120, 100%, 40%);">+ default 0x20</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+config IRQ_SLOT_COUNT</span><br><span style="color: hsl(120, 100%, 40%);">+ int</span><br><span style="color: hsl(120, 100%, 40%);">+ default 11</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+config MCP55_PCI_E_X_0</span><br><span style="color: hsl(120, 100%, 40%);">+ int</span><br><span style="color: hsl(120, 100%, 40%);">+ default 0</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+endif # BOARD_GIGABYTE_M57SLI</span><br><span>diff --git a/src/mainboard/gigabyte/m57sli/Kconfig.name b/src/mainboard/gigabyte/m57sli/Kconfig.name</span><br><span>new file mode 100644</span><br><span>index 0000000..32a5470</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/gigabyte/m57sli/Kconfig.name</span><br><span>@@ -0,0 +1,2 @@</span><br><span style="color: hsl(120, 100%, 40%);">+config BOARD_GIGABYTE_M57SLI</span><br><span style="color: hsl(120, 100%, 40%);">+ bool "GA-M57SLI-S4"</span><br><span>diff --git a/src/mainboard/gigabyte/m57sli/Makefile.inc b/src/mainboard/gigabyte/m57sli/Makefile.inc</span><br><span>new file mode 100644</span><br><span>index 0000000..c18f224</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/gigabyte/m57sli/Makefile.inc</span><br><span>@@ -0,0 +1,16 @@</span><br><span style="color: hsl(120, 100%, 40%);">+##</span><br><span style="color: hsl(120, 100%, 40%);">+## This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+##</span><br><span style="color: hsl(120, 100%, 40%);">+## Copyright (C) 2007-2008 coresystems GmbH</span><br><span style="color: hsl(120, 100%, 40%);">+##</span><br><span style="color: hsl(120, 100%, 40%);">+## This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+## it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+## the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+##</span><br><span style="color: hsl(120, 100%, 40%);">+## This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+## but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+## GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+##</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ramstage-$(CONFIG_SUPERIO_ITE_IT8716F_OVERRIDE_FANCTL) += fanctl.c</span><br><span>diff --git a/src/mainboard/gigabyte/m57sli/acpi_tables.c b/src/mainboard/gigabyte/m57sli/acpi_tables.c</span><br><span>new file mode 100644</span><br><span>index 0000000..abe1c57</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/gigabyte/m57sli/acpi_tables.c</span><br><span>@@ -0,0 +1,81 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Written by Stefan Reinauer <stepan@openbios.org>.</span><br><span style="color: hsl(120, 100%, 40%);">+ * ACPI FADT, FACS, and DSDT table support added by</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2004 Stefan Reinauer <stepan@openbios.org></span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2005 Nick Barker <nick.barker9@btinternet.com></span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2007, 2008 Rudolf Marek <r.marek@assembler.cz></span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2009 Harald Gutmann <harald.gutmann@gmx.net></span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <console/console.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <string.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <arch/acpi.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <arch/smp/mpspec.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <device/device.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <device/pci_ids.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <cpu/amd/powernow.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <device/pci.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <cpu/amd/amdfam10_sysconf.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+unsigned long acpi_fill_madt(unsigned long current)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ unsigned int gsi_base = 0x18;</span><br><span style="color: hsl(120, 100%, 40%);">+ extern unsigned char bus_mcp55[8];</span><br><span style="color: hsl(120, 100%, 40%);">+ extern unsigned apicid_mcp55;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ unsigned sbdn;</span><br><span style="color: hsl(120, 100%, 40%);">+ struct resource *res;</span><br><span style="color: hsl(120, 100%, 40%);">+ device_t dev;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ get_bus_conf();</span><br><span style="color: hsl(120, 100%, 40%);">+ sbdn = sysconf.sbdn;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Create all subtables for processors. */</span><br><span style="color: hsl(120, 100%, 40%);">+ current = acpi_create_madt_lapics(current);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Write SB IOAPIC. */</span><br><span style="color: hsl(120, 100%, 40%);">+ dev = dev_find_slot(bus_mcp55[0], PCI_DEVFN(sbdn+ 0x1,0));</span><br><span style="color: hsl(120, 100%, 40%);">+ if (dev) {</span><br><span style="color: hsl(120, 100%, 40%);">+ res = find_resource(dev, PCI_BASE_ADDRESS_1);</span><br><span style="color: hsl(120, 100%, 40%);">+ if (res) {</span><br><span style="color: hsl(120, 100%, 40%);">+ current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current,</span><br><span style="color: hsl(120, 100%, 40%);">+ apicid_mcp55, res->base, 0);</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Write NB IOAPIC. */</span><br><span style="color: hsl(120, 100%, 40%);">+ dev = dev_find_slot(bus_mcp55[0], PCI_DEVFN(sbdn+ 0x12,1));</span><br><span style="color: hsl(120, 100%, 40%);">+ if (dev) {</span><br><span style="color: hsl(120, 100%, 40%);">+ res = find_resource(dev, PCI_BASE_ADDRESS_1);</span><br><span style="color: hsl(120, 100%, 40%);">+ if (res) {</span><br><span style="color: hsl(120, 100%, 40%);">+ current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current,</span><br><span style="color: hsl(120, 100%, 40%);">+ apicid_mcp55++, res->base, gsi_base);</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* IRQ9 ACPI active low. */</span><br><span style="color: hsl(120, 100%, 40%);">+ current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)</span><br><span style="color: hsl(120, 100%, 40%);">+ current, 0, 9, 9, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* IRQ0 -> APIC IRQ2. */</span><br><span style="color: hsl(120, 100%, 40%);">+ current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)</span><br><span style="color: hsl(120, 100%, 40%);">+ current, 0, 0, 2, 0x0);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Create all subtables for processors. */</span><br><span style="color: hsl(120, 100%, 40%);">+ current = acpi_create_madt_lapic_nmis(current,</span><br><span style="color: hsl(120, 100%, 40%);">+ MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, 1);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ return current;</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span>diff --git a/src/mainboard/gigabyte/m57sli/board_info.txt b/src/mainboard/gigabyte/m57sli/board_info.txt</span><br><span>new file mode 100644</span><br><span>index 0000000..33c3655</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/gigabyte/m57sli/board_info.txt</span><br><span>@@ -0,0 +1,7 @@</span><br><span style="color: hsl(120, 100%, 40%);">+Category: desktop</span><br><span style="color: hsl(120, 100%, 40%);">+Board URL: http://www.gigabyte.com/products/product-page.aspx?pid=2287#ov</span><br><span style="color: hsl(120, 100%, 40%);">+ROM socketed: n</span><br><span style="color: hsl(120, 100%, 40%);">+Flashrom support: y</span><br><span style="color: hsl(120, 100%, 40%);">+Vendor cooperation score: 3</span><br><span style="color: hsl(120, 100%, 40%);">+Vendor cooperation page: Gigabyte m57sli Vendor Cooperation Score</span><br><span style="color: hsl(120, 100%, 40%);">+Release year: 2006</span><br><span>diff --git a/src/mainboard/gigabyte/m57sli/cmos.default b/src/mainboard/gigabyte/m57sli/cmos.default</span><br><span>new file mode 100644</span><br><span>index 0000000..bfc7392</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/gigabyte/m57sli/cmos.default</span><br><span>@@ -0,0 +1,9 @@</span><br><span style="color: hsl(120, 100%, 40%);">+debug_level = Spew</span><br><span style="color: hsl(120, 100%, 40%);">+multi_core = Enable</span><br><span style="color: hsl(120, 100%, 40%);">+slow_cpu = off</span><br><span style="color: hsl(120, 100%, 40%);">+max_mem_clock = 400Mhz</span><br><span style="color: hsl(120, 100%, 40%);">+ECC_memory = Enable</span><br><span style="color: hsl(120, 100%, 40%);">+hw_scrubber = Enable</span><br><span style="color: hsl(120, 100%, 40%);">+interleave_chip_selects = Enable</span><br><span style="color: hsl(120, 100%, 40%);">+power_on_after_fail = Disable</span><br><span style="color: hsl(120, 100%, 40%);">+boot_option = Fallback</span><br><span>diff --git a/src/mainboard/gigabyte/m57sli/cmos.layout b/src/mainboard/gigabyte/m57sli/cmos.layout</span><br><span>new file mode 100644</span><br><span>index 0000000..c960223</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/gigabyte/m57sli/cmos.layout</span><br><span>@@ -0,0 +1,69 @@</span><br><span style="color: hsl(120, 100%, 40%);">+##</span><br><span style="color: hsl(120, 100%, 40%);">+## This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+##</span><br><span style="color: hsl(120, 100%, 40%);">+## Copyright (C) 2007 AMD</span><br><span style="color: hsl(120, 100%, 40%);">+## Written by Yinghai Lu <yinghailu@amd.com> for AMD.</span><br><span style="color: hsl(120, 100%, 40%);">+##</span><br><span style="color: hsl(120, 100%, 40%);">+## This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+## it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+## the Free Software Foundation; either version 2 of the License, or</span><br><span style="color: hsl(120, 100%, 40%);">+## (at your option) any later version.</span><br><span style="color: hsl(120, 100%, 40%);">+##</span><br><span style="color: hsl(120, 100%, 40%);">+## This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+## but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+## GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+##</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+entries</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+0 384 r 0 reserved_memory</span><br><span style="color: hsl(120, 100%, 40%);">+384 1 e 4 boot_option</span><br><span style="color: hsl(120, 100%, 40%);">+388 4 h 0 reboot_counter</span><br><span style="color: hsl(120, 100%, 40%);">+#392 3 r 0 unused</span><br><span style="color: hsl(120, 100%, 40%);">+395 1 e 1 hw_scrubber</span><br><span style="color: hsl(120, 100%, 40%);">+396 1 e 1 interleave_chip_selects</span><br><span style="color: hsl(120, 100%, 40%);">+397 2 e 8 max_mem_clock</span><br><span style="color: hsl(120, 100%, 40%);">+399 1 e 2 multi_core</span><br><span style="color: hsl(120, 100%, 40%);">+400 1 e 1 power_on_after_fail</span><br><span style="color: hsl(120, 100%, 40%);">+412 4 e 6 debug_level</span><br><span style="color: hsl(120, 100%, 40%);">+440 4 e 9 slow_cpu</span><br><span style="color: hsl(120, 100%, 40%);">+444 1 e 1 nmi</span><br><span style="color: hsl(120, 100%, 40%);">+445 1 e 1 gart</span><br><span style="color: hsl(120, 100%, 40%);">+456 1 e 1 ECC_memory</span><br><span style="color: hsl(120, 100%, 40%);">+728 256 h 0 user_data</span><br><span style="color: hsl(120, 100%, 40%);">+984 16 h 0 check_sum</span><br><span style="color: hsl(120, 100%, 40%);">+# Reserve the extended AMD configuration registers</span><br><span style="color: hsl(120, 100%, 40%);">+1000 24 r 0 amd_reserved</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+enumerations</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#ID value text</span><br><span style="color: hsl(120, 100%, 40%);">+1 0 Disable</span><br><span style="color: hsl(120, 100%, 40%);">+1 1 Enable</span><br><span style="color: hsl(120, 100%, 40%);">+2 0 Enable</span><br><span style="color: hsl(120, 100%, 40%);">+2 1 Disable</span><br><span style="color: hsl(120, 100%, 40%);">+4 0 Fallback</span><br><span style="color: hsl(120, 100%, 40%);">+4 1 Normal</span><br><span style="color: hsl(120, 100%, 40%);">+6 6 Notice</span><br><span style="color: hsl(120, 100%, 40%);">+6 7 Info</span><br><span style="color: hsl(120, 100%, 40%);">+6 8 Debug</span><br><span style="color: hsl(120, 100%, 40%);">+6 9 Spew</span><br><span style="color: hsl(120, 100%, 40%);">+8 0 400Mhz</span><br><span style="color: hsl(120, 100%, 40%);">+8 1 333Mhz</span><br><span style="color: hsl(120, 100%, 40%);">+8 2 266Mhz</span><br><span style="color: hsl(120, 100%, 40%);">+8 3 200Mhz</span><br><span style="color: hsl(120, 100%, 40%);">+9 0 off</span><br><span style="color: hsl(120, 100%, 40%);">+9 1 87.5%</span><br><span style="color: hsl(120, 100%, 40%);">+9 2 75.0%</span><br><span style="color: hsl(120, 100%, 40%);">+9 3 62.5%</span><br><span style="color: hsl(120, 100%, 40%);">+9 4 50.0%</span><br><span style="color: hsl(120, 100%, 40%);">+9 5 37.5%</span><br><span style="color: hsl(120, 100%, 40%);">+9 6 25.0%</span><br><span style="color: hsl(120, 100%, 40%);">+9 7 12.5%</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+checksums</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+checksum 392 983 984</span><br><span>diff --git a/src/mainboard/gigabyte/m57sli/devicetree.cb b/src/mainboard/gigabyte/m57sli/devicetree.cb</span><br><span>new file mode 100644</span><br><span>index 0000000..eb43836</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/gigabyte/m57sli/devicetree.cb</span><br><span>@@ -0,0 +1,153 @@</span><br><span style="color: hsl(120, 100%, 40%);">+chip northbridge/amd/amdfam10/root_complex # Root complex</span><br><span style="color: hsl(120, 100%, 40%);">+ device cpu_cluster 0 on # (L)APIC cluster</span><br><span style="color: hsl(120, 100%, 40%);">+ chip cpu/amd/socket_AM2r2 # CPU socket</span><br><span style="color: hsl(120, 100%, 40%);">+ device lapic 0 on end # Local APIC of the CPU</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ device domain 0 on # PCI domain</span><br><span style="color: hsl(120, 100%, 40%);">+ subsystemid 0x1022 0x2b80 inherit</span><br><span style="color: hsl(120, 100%, 40%);">+ chip northbridge/amd/amdfam10 # Northbridge / RAM controller</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 18.0 on # Link 0 == LDT 0</span><br><span style="color: hsl(120, 100%, 40%);">+ chip southbridge/nvidia/mcp55 # Southbridge</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 0.0 on end # HT</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1.0 on # LPC</span><br><span style="color: hsl(120, 100%, 40%);">+ chip superio/ite/it8716f # Super I/O</span><br><span style="color: hsl(120, 100%, 40%);">+ device pnp 2e.0 on # Floppy and any LDN</span><br><span style="color: hsl(120, 100%, 40%);">+ # Watchdog from CLKIN (24 MHz)</span><br><span style="color: hsl(120, 100%, 40%);">+ irq 0x23 = 0x11</span><br><span style="color: hsl(120, 100%, 40%);">+ # Serial Flash (SPI only)</span><br><span style="color: hsl(120, 100%, 40%);">+ # 0x24 = 0x1a</span><br><span style="color: hsl(120, 100%, 40%);">+ io 0x60 = 0x3f0</span><br><span style="color: hsl(120, 100%, 40%);">+ irq 0x70 = 6</span><br><span style="color: hsl(120, 100%, 40%);">+ drq 0x74 = 2</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ device pnp 2e.1 on # Com1</span><br><span style="color: hsl(120, 100%, 40%);">+ io 0x60 = 0x3f8</span><br><span style="color: hsl(120, 100%, 40%);">+ irq 0x70 = 4</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ device pnp 2e.2 off # Com2</span><br><span style="color: hsl(120, 100%, 40%);">+ io 0x60 = 0x2f8</span><br><span style="color: hsl(120, 100%, 40%);">+ irq 0x70 = 3</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ device pnp 2e.3 on # Parallel port</span><br><span style="color: hsl(120, 100%, 40%);">+ io 0x60 = 0x378</span><br><span style="color: hsl(120, 100%, 40%);">+ irq 0x70 = 7</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ device pnp 2e.4 on # Embedded controller</span><br><span style="color: hsl(120, 100%, 40%);">+ io 0x60 = 0x290</span><br><span style="color: hsl(120, 100%, 40%);">+ io 0x62 = 0x230</span><br><span style="color: hsl(120, 100%, 40%);">+ irq 0x70 = 9</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ device pnp 2e.5 on # PS/2 keyboard</span><br><span style="color: hsl(120, 100%, 40%);">+ io 0x60 = 0x60</span><br><span style="color: hsl(120, 100%, 40%);">+ io 0x62 = 0x64</span><br><span style="color: hsl(120, 100%, 40%);">+ irq 0x70 = 1</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ device pnp 2e.6 on # PS/2 mouse</span><br><span style="color: hsl(120, 100%, 40%);">+ irq 0x70 = 12</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ device pnp 2e.7 on # GPIO, SPI flash</span><br><span style="color: hsl(120, 100%, 40%);">+ # Pin 84 is not GP10</span><br><span style="color: hsl(120, 100%, 40%);">+ irq 0x25 = 0x0</span><br><span style="color: hsl(120, 100%, 40%);">+ # Pin 21 is GP26, pin 26 is GP21, pin 27 is GP20</span><br><span style="color: hsl(120, 100%, 40%);">+ irq 0x26 = 0x43</span><br><span style="color: hsl(120, 100%, 40%);">+ # Pin 13 is GP35</span><br><span style="color: hsl(120, 100%, 40%);">+ irq 0x27 = 0x20</span><br><span style="color: hsl(120, 100%, 40%);">+ # Pin 70 is not GP46</span><br><span style="color: hsl(120, 100%, 40%);">+ # irq 0x28 = 0x0</span><br><span style="color: hsl(120, 100%, 40%);">+ # Pin 6,3,128,127,126 is GP63,64,65,66,67</span><br><span style="color: hsl(120, 100%, 40%);">+ irq 0x29 = 0x81</span><br><span style="color: hsl(120, 100%, 40%);">+ # Enable FAN_CTL/FAN_TAC set to 5 (pin 21, 23),</span><br><span style="color: hsl(120, 100%, 40%);">+ # enable FAN_CTL/FAN_TAC set to 4 (pin 20, 22),</span><br><span style="color: hsl(120, 100%, 40%);">+ # pin 48 is PCIRST5#, pin91 is PCIRSTIN#, VIN7 is internal</span><br><span style="color: hsl(120, 100%, 40%);">+ # voltage divider for VCCH5V, pin 95 is ATXPG, VIN3 is internal</span><br><span style="color: hsl(120, 100%, 40%);">+ # voltage divider for VCC5V</span><br><span style="color: hsl(120, 100%, 40%);">+ # irq 0x2c = 0x1f</span><br><span style="color: hsl(120, 100%, 40%);">+ # Simple I/O base</span><br><span style="color: hsl(120, 100%, 40%);">+ io 0x62 = 0x800</span><br><span style="color: hsl(120, 100%, 40%);">+ # Serial Flash I/O (SPI only)</span><br><span style="color: hsl(120, 100%, 40%);">+ io 0x64 = 0x820</span><br><span style="color: hsl(120, 100%, 40%);">+ # Watchdog force timeout (parallel flash only)</span><br><span style="color: hsl(120, 100%, 40%);">+ # irq 0x71 = 0x1</span><br><span style="color: hsl(120, 100%, 40%);">+ # No WDT interrupt</span><br><span style="color: hsl(120, 100%, 40%);">+ irq 0x72 = 0x0</span><br><span style="color: hsl(120, 100%, 40%);">+ # GPIO pin set 1 disable internal pullup</span><br><span style="color: hsl(120, 100%, 40%);">+ irq 0xb8 = 0x0</span><br><span style="color: hsl(120, 100%, 40%);">+ # GPIO pin set 5 enable internal pullup</span><br><span style="color: hsl(120, 100%, 40%);">+ irq 0xbc = 0x01</span><br><span style="color: hsl(120, 100%, 40%);">+ # SIO pin set 1 alternate function</span><br><span style="color: hsl(120, 100%, 40%);">+ # irq 0xc0 = 0x0</span><br><span style="color: hsl(120, 100%, 40%);">+ # SIO pin set 2 mixed function</span><br><span style="color: hsl(120, 100%, 40%);">+ irq 0xc1 = 0x43</span><br><span style="color: hsl(120, 100%, 40%);">+ # SIO pin set 3 mixed function</span><br><span style="color: hsl(120, 100%, 40%);">+ irq 0xc2 = 0x20</span><br><span style="color: hsl(120, 100%, 40%);">+ # SIO pin set 4 alternate function</span><br><span style="color: hsl(120, 100%, 40%);">+ # irq 0xc3 = 0x0</span><br><span style="color: hsl(120, 100%, 40%);">+ # SIO pin set 1 input mode</span><br><span style="color: hsl(120, 100%, 40%);">+ # irq 0xc8 = 0x0</span><br><span style="color: hsl(120, 100%, 40%);">+ # SIO pin set 2 input mode</span><br><span style="color: hsl(120, 100%, 40%);">+ irq 0xc9 = 0x0</span><br><span style="color: hsl(120, 100%, 40%);">+ # SIO pin set 4 input mode</span><br><span style="color: hsl(120, 100%, 40%);">+ # irq 0xcb = 0x0</span><br><span style="color: hsl(120, 100%, 40%);">+ # Generate SMI# on EC IRQ</span><br><span style="color: hsl(120, 100%, 40%);">+ # irq 0xf0 = 0x10</span><br><span style="color: hsl(120, 100%, 40%);">+ # SMI# level trigger</span><br><span style="color: hsl(120, 100%, 40%);">+ # irq 0xf1 = 0x40</span><br><span style="color: hsl(120, 100%, 40%);">+ # HWMON alert beep pin location</span><br><span style="color: hsl(120, 100%, 40%);">+ irq 0xf6 = 0x28</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ device pnp 2e.8 off # MIDI</span><br><span style="color: hsl(120, 100%, 40%);">+ io 0x60 = 0x300</span><br><span style="color: hsl(120, 100%, 40%);">+ irq 0x70 = 10</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ device pnp 2e.9 off # Game port</span><br><span style="color: hsl(120, 100%, 40%);">+ io 0x60 = 0x220</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ device pnp 2e.a off end # Consumer IR</span><br><span style="color: hsl(120, 100%, 40%);">+ end # superio/ite/it8716f</span><br><span style="color: hsl(120, 100%, 40%);">+ end # pci 1.0</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1.1 on # SM 0</span><br><span style="color: hsl(120, 100%, 40%);">+ chip drivers/generic/generic # DIMM 0-0-0</span><br><span style="color: hsl(120, 100%, 40%);">+ device i2c 50 on end</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ chip drivers/generic/generic # DIMM 0-0-1</span><br><span style="color: hsl(120, 100%, 40%);">+ device i2c 51 on end</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ chip drivers/generic/generic # DIMM 0-1-0</span><br><span style="color: hsl(120, 100%, 40%);">+ device i2c 52 on end</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ chip drivers/generic/generic # DIMM 0-1-1</span><br><span style="color: hsl(120, 100%, 40%);">+ device i2c 53 on end</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 2.0 on end # USB 1.1</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 2.1 on end # USB 2</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 4.0 on end # IDE</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 5.0 on end # SATA 0</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 5.1 on end # SATA 1</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 5.2 on end # SATA 2</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 6.0 on end # PCI</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 6.1 on end # AUDIO</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 8.0 on end # NIC</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 9.0 off end # N/A</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci a.0 on end # PCI E 5</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci b.0 on end # PCI E 4</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci c.0 on end # PCI E 3</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci d.0 on end # PCI E 2</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci e.0 on end # PCI E 1</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci f.0 on end # PCI E 0</span><br><span style="color: hsl(120, 100%, 40%);">+ register "ide0_enable" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "sata0_enable" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "sata1_enable" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ # 1: SMBus under 2e.8, 2: SM0 3: SM1</span><br><span style="color: hsl(120, 100%, 40%);">+ register "mac_eeprom_smbus" = "3"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "mac_eeprom_addr" = "0x51"</span><br><span style="color: hsl(120, 100%, 40%);">+ end # southbridge/nvidia/mcp55</span><br><span style="color: hsl(120, 100%, 40%);">+ end # pci 18.0</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 18.1 on end</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 18.2 on end</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 18.3 on end</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 18.4 on end</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ end #domain</span><br><span style="color: hsl(120, 100%, 40%);">+end</span><br><span>diff --git a/src/mainboard/gigabyte/m57sli/dsdt.asl b/src/mainboard/gigabyte/m57sli/dsdt.asl</span><br><span>new file mode 100644</span><br><span>index 0000000..b844ee6</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/gigabyte/m57sli/dsdt.asl</span><br><span>@@ -0,0 +1,300 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2004 Nick Barker <Nick.Barker9@btinternet.com></span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2007, 2008 Rudolf Marek <r.marek@assembler.cz></span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2009 Harald Gutmann <harald.gutmann@gmx.net></span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * ISA portions taken from QEMU acpi-dsdt.dsl.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+DefinitionBlock ("DSDT.aml", "DSDT", 1, "CORE ", "COREBOOT", 1)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ #include "northbridge/amd/amdfam10/amdfam10_util.asl"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* For now only define 2 power states:</span><br><span style="color: hsl(120, 100%, 40%);">+ * - S0 which is fully on</span><br><span style="color: hsl(120, 100%, 40%);">+ * - S5 which is soft off</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+ Name (\_S0, Package () { 0x00, 0x00, 0x00, 0x00 })</span><br><span style="color: hsl(120, 100%, 40%);">+ Name (\_S5, Package () { 0x07, 0x00, 0x00, 0x00 })</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Root of the bus hierarchy */</span><br><span style="color: hsl(120, 100%, 40%);">+ Scope (\_SB)</span><br><span style="color: hsl(120, 100%, 40%);">+ {</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Top PCI device */</span><br><span style="color: hsl(120, 100%, 40%);">+ Device (PCI0)</span><br><span style="color: hsl(120, 100%, 40%);">+ {</span><br><span style="color: hsl(120, 100%, 40%);">+ Name (_HID, EisaId ("PNP0A03"))</span><br><span style="color: hsl(120, 100%, 40%);">+ Name (_ADR, 0x00)</span><br><span style="color: hsl(120, 100%, 40%);">+ Name (_UID, 0x00)</span><br><span style="color: hsl(120, 100%, 40%);">+ Name (_BBN, 0x00)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ External (BUSN)</span><br><span style="color: hsl(120, 100%, 40%);">+ External (MMIO)</span><br><span style="color: hsl(120, 100%, 40%);">+ External (PCIO)</span><br><span style="color: hsl(120, 100%, 40%);">+ External (SBLK)</span><br><span style="color: hsl(120, 100%, 40%);">+ External (TOM1)</span><br><span style="color: hsl(120, 100%, 40%);">+ External (HCLK)</span><br><span style="color: hsl(120, 100%, 40%);">+ External (SBDN)</span><br><span style="color: hsl(120, 100%, 40%);">+ External (HCDN)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ Method (_CRS, 0, NotSerialized)</span><br><span style="color: hsl(120, 100%, 40%);">+ {</span><br><span style="color: hsl(120, 100%, 40%);">+ Name (BUF0, ResourceTemplate ()</span><br><span style="color: hsl(120, 100%, 40%);">+ {</span><br><span style="color: hsl(120, 100%, 40%);">+ IO (Decode16,</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x0CF8, // Address Range Minimum</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x0CF8, // Address Range Maximum</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x01, // Address Alignment</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x08, // Address Length</span><br><span style="color: hsl(120, 100%, 40%);">+ )</span><br><span style="color: hsl(120, 100%, 40%);">+ WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x0000, // Address Space Granularity</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x0000, // Address Range Minimum</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x0CF7, // Address Range Maximum</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x0000, // Address Translation Offset</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x0CF8, // Address Length</span><br><span style="color: hsl(120, 100%, 40%);">+ ,, , TypeStatic)</span><br><span style="color: hsl(120, 100%, 40%);">+ })</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Methods bellow use SSDT to get actual MMIO regs</span><br><span style="color: hsl(120, 100%, 40%);">+ The IO ports are from 0xd00, optionally an VGA,</span><br><span style="color: hsl(120, 100%, 40%);">+ otherwise the info from MMIO is used.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+ Concatenate (\_SB.GMEM (0x00, \_SB.PCI0.SBLK), BUF0, Local1)</span><br><span style="color: hsl(120, 100%, 40%);">+ Concatenate (\_SB.GIOR (0x00, \_SB.PCI0.SBLK), Local1, Local2)</span><br><span style="color: hsl(120, 100%, 40%);">+ Concatenate (\_SB.GWBN (0x00, \_SB.PCI0.SBLK), Local2, Local3)</span><br><span style="color: hsl(120, 100%, 40%);">+ Return (Local3)</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* PCI Routing Table */</span><br><span style="color: hsl(120, 100%, 40%);">+ Name (_PRT, Package () {</span><br><span style="color: hsl(120, 100%, 40%);">+ Package (0x04) { 0x0001FFFF, 0x01, 0x00, 0x0A }, /* 0x1 - 00:01.1 - IRQ 10 - SMBus */</span><br><span style="color: hsl(120, 100%, 40%);">+ Package (0x04) { 0x0002FFFF, 0x00, 0x00, 0x16 }, /* 0x2 - 00:02.0 - IRQ 22 - USB */</span><br><span style="color: hsl(120, 100%, 40%);">+ Package (0x04) { 0x0002FFFF, 0x01, 0x00, 0x17 }, /* 0x2 - 00:01.1 - IRQ 23 - USB */</span><br><span style="color: hsl(120, 100%, 40%);">+ Package (0x04) { 0x0004FFFF, 0x00, 0x00, 0x15 }, /* 0x4 - 00:04.0 - IRQ 21 - IDE */</span><br><span style="color: hsl(120, 100%, 40%);">+ Package (0x04) { 0x0005FFFF, 0x00, 0x00, 0x14 }, /* 0x5 - 00:05.0 - IRQ 20 - SATA */</span><br><span style="color: hsl(120, 100%, 40%);">+ Package (0x04) { 0x0005FFFF, 0x01, 0x00, 0x15 }, /* 0x5 - 00:05.1 - IRQ 21 - SATA */</span><br><span style="color: hsl(120, 100%, 40%);">+ Package (0x04) { 0x0005FFFF, 0x02, 0x00, 0x16 }, /* 0x5 - 00:05.2 - IRQ 22 - SATA */</span><br><span style="color: hsl(120, 100%, 40%);">+ Package (0x04) { 0x0006FFFF, 0x01, 0x00, 0x17 }, /* 0x6 - 00:06.1 - IRQ 23 - HD Audio */</span><br><span style="color: hsl(120, 100%, 40%);">+ Package (0x04) { 0x0008FFFF, 0x00, 0x00, 0x14 }, /* 0x8 - 00:08.0 - IRQ 20 - GBit Ethernet */</span><br><span style="color: hsl(120, 100%, 40%);">+ })</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ Device (PEBF) /* PCI-E Bridge F */</span><br><span style="color: hsl(120, 100%, 40%);">+ {</span><br><span style="color: hsl(120, 100%, 40%);">+ Name (_ADR, 0x000F0000)</span><br><span style="color: hsl(120, 100%, 40%);">+ Name (_UID, 0x00)</span><br><span style="color: hsl(120, 100%, 40%);">+ Name (_BBN, 0x07)</span><br><span style="color: hsl(120, 100%, 40%);">+ Name (_PRT, Package () {</span><br><span style="color: hsl(120, 100%, 40%);">+ Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x11 },</span><br><span style="color: hsl(120, 100%, 40%);">+ Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x12 },</span><br><span style="color: hsl(120, 100%, 40%);">+ Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x13 },</span><br><span style="color: hsl(120, 100%, 40%);">+ Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x10 },</span><br><span style="color: hsl(120, 100%, 40%);">+ })</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ Device (PEBE) /* PCI-E Bridge E */</span><br><span style="color: hsl(120, 100%, 40%);">+ {</span><br><span style="color: hsl(120, 100%, 40%);">+ Name (_ADR, 0x000E0000)</span><br><span style="color: hsl(120, 100%, 40%);">+ Name (_UID, 0x00)</span><br><span style="color: hsl(120, 100%, 40%);">+ Name (_BBN, 0x06)</span><br><span style="color: hsl(120, 100%, 40%);">+ Name (_PRT, Package () {</span><br><span style="color: hsl(120, 100%, 40%);">+ Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x12 },</span><br><span style="color: hsl(120, 100%, 40%);">+ Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x13 },</span><br><span style="color: hsl(120, 100%, 40%);">+ Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x10 },</span><br><span style="color: hsl(120, 100%, 40%);">+ Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x11 },</span><br><span style="color: hsl(120, 100%, 40%);">+ })</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ Device (PEBD) /* PCI-E Bridge D */</span><br><span style="color: hsl(120, 100%, 40%);">+ {</span><br><span style="color: hsl(120, 100%, 40%);">+ Name (_ADR, 0x000D0000)</span><br><span style="color: hsl(120, 100%, 40%);">+ Name (_UID, 0x00)</span><br><span style="color: hsl(120, 100%, 40%);">+ Name (_BBN, 0x05)</span><br><span style="color: hsl(120, 100%, 40%);">+ Name (_PRT, Package () {</span><br><span style="color: hsl(120, 100%, 40%);">+ Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x13 },</span><br><span style="color: hsl(120, 100%, 40%);">+ Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x10 },</span><br><span style="color: hsl(120, 100%, 40%);">+ Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x11 },</span><br><span style="color: hsl(120, 100%, 40%);">+ Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x12 },</span><br><span style="color: hsl(120, 100%, 40%);">+ })</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ Device (PEBC) /* PCI-E Bridge C */</span><br><span style="color: hsl(120, 100%, 40%);">+ {</span><br><span style="color: hsl(120, 100%, 40%);">+ Name (_ADR, 0x000C0000)</span><br><span style="color: hsl(120, 100%, 40%);">+ Name (_UID, 0x00)</span><br><span style="color: hsl(120, 100%, 40%);">+ Name (_BBN, 0x04)</span><br><span style="color: hsl(120, 100%, 40%);">+ Name (_PRT, Package () {</span><br><span style="color: hsl(120, 100%, 40%);">+ Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x10 },</span><br><span style="color: hsl(120, 100%, 40%);">+ Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x11 },</span><br><span style="color: hsl(120, 100%, 40%);">+ Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x12 },</span><br><span style="color: hsl(120, 100%, 40%);">+ Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x13 },</span><br><span style="color: hsl(120, 100%, 40%);">+ })</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ Device (PEBB) /* PCI-E Bridge B */</span><br><span style="color: hsl(120, 100%, 40%);">+ {</span><br><span style="color: hsl(120, 100%, 40%);">+ Name (_ADR, 0x000B0000)</span><br><span style="color: hsl(120, 100%, 40%);">+ Name (_UID, 0x00)</span><br><span style="color: hsl(120, 100%, 40%);">+ Name (_BBN, 0x03)</span><br><span style="color: hsl(120, 100%, 40%);">+ Name (_PRT, Package () {</span><br><span style="color: hsl(120, 100%, 40%);">+ Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x11 },</span><br><span style="color: hsl(120, 100%, 40%);">+ Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x12 },</span><br><span style="color: hsl(120, 100%, 40%);">+ Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x13 },</span><br><span style="color: hsl(120, 100%, 40%);">+ Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x10 },</span><br><span style="color: hsl(120, 100%, 40%);">+ })</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ Device (PEBA) /* PCI-E Bridge A */</span><br><span style="color: hsl(120, 100%, 40%);">+ {</span><br><span style="color: hsl(120, 100%, 40%);">+ Name (_ADR, 0x000A0000)</span><br><span style="color: hsl(120, 100%, 40%);">+ Name (_UID, 0x00)</span><br><span style="color: hsl(120, 100%, 40%);">+ Name (_BBN, 0x02)</span><br><span style="color: hsl(120, 100%, 40%);">+ Name (_PRT, Package () {</span><br><span style="color: hsl(120, 100%, 40%);">+ Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x12 },</span><br><span style="color: hsl(120, 100%, 40%);">+ Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x13 },</span><br><span style="color: hsl(120, 100%, 40%);">+ Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x10 },</span><br><span style="color: hsl(120, 100%, 40%);">+ Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x11 },</span><br><span style="color: hsl(120, 100%, 40%);">+ })</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ Device (PCID) /* PCI Device */</span><br><span style="color: hsl(120, 100%, 40%);">+ {</span><br><span style="color: hsl(120, 100%, 40%);">+ Name (_ADR, 0x00060000)</span><br><span style="color: hsl(120, 100%, 40%);">+ Name (_UID, 0x00)</span><br><span style="color: hsl(120, 100%, 40%);">+ Name (_BBN, 0x01)</span><br><span style="color: hsl(120, 100%, 40%);">+ Name (_PRT, Package () {</span><br><span style="color: hsl(120, 100%, 40%);">+ Package (0x04) { 0x0006FFFF, 0x00, 0x00, 0x12 },</span><br><span style="color: hsl(120, 100%, 40%);">+ Package (0x04) { 0x0006FFFF, 0x01, 0x00, 0x13 },</span><br><span style="color: hsl(120, 100%, 40%);">+ Package (0x04) { 0x0006FFFF, 0x02, 0x00, 0x10 },</span><br><span style="color: hsl(120, 100%, 40%);">+ Package (0x04) { 0x0006FFFF, 0x03, 0x00, 0x11 },</span><br><span style="color: hsl(120, 100%, 40%);">+ Package (0x04) { 0x0007FFFF, 0x00, 0x00, 0x13 }, /* PCI slot 1 */</span><br><span style="color: hsl(120, 100%, 40%);">+ Package (0x04) { 0x0007FFFF, 0x01, 0x00, 0x10 },</span><br><span style="color: hsl(120, 100%, 40%);">+ Package (0x04) { 0x0007FFFF, 0x02, 0x00, 0x11 },</span><br><span style="color: hsl(120, 100%, 40%);">+ Package (0x04) { 0x0007FFFF, 0x03, 0x00, 0x12 },</span><br><span style="color: hsl(120, 100%, 40%);">+ Package (0x04) { 0x0008FFFF, 0x00, 0x00, 0x10 }, /* PCI slot 2 */</span><br><span style="color: hsl(120, 100%, 40%);">+ Package (0x04) { 0x0008FFFF, 0x01, 0x00, 0x11 },</span><br><span style="color: hsl(120, 100%, 40%);">+ Package (0x04) { 0x0008FFFF, 0x02, 0x00, 0x12 },</span><br><span style="color: hsl(120, 100%, 40%);">+ Package (0x04) { 0x0008FFFF, 0x03, 0x00, 0x13 },</span><br><span style="color: hsl(120, 100%, 40%);">+ Package (0x04) { 0x0009FFFF, 0x00, 0x00, 0x11 },</span><br><span style="color: hsl(120, 100%, 40%);">+ Package (0x04) { 0x0009FFFF, 0x01, 0x00, 0x12 },</span><br><span style="color: hsl(120, 100%, 40%);">+ Package (0x04) { 0x0009FFFF, 0x02, 0x00, 0x13 },</span><br><span style="color: hsl(120, 100%, 40%);">+ Package (0x04) { 0x0009FFFF, 0x03, 0x00, 0x10 },</span><br><span style="color: hsl(120, 100%, 40%);">+ Package (0x04) { 0x000AFFFF, 0x00, 0x00, 0x12 }, /* FireWire */</span><br><span style="color: hsl(120, 100%, 40%);">+ Package (0x04) { 0x000AFFFF, 0x01, 0x00, 0x13 },</span><br><span style="color: hsl(120, 100%, 40%);">+ Package (0x04) { 0x000AFFFF, 0x02, 0x00, 0x10 },</span><br><span style="color: hsl(120, 100%, 40%);">+ Package (0x04) { 0x000AFFFF, 0x03, 0x00, 0x11 },</span><br><span style="color: hsl(120, 100%, 40%);">+ })</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ Device (ISA) {</span><br><span style="color: hsl(120, 100%, 40%);">+ Name (_ADR, 0x000010000)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* PS/2 keyboard (seems to be important for WinXP install) */</span><br><span style="color: hsl(120, 100%, 40%);">+ Device (KBD)</span><br><span style="color: hsl(120, 100%, 40%);">+ {</span><br><span style="color: hsl(120, 100%, 40%);">+ Name (_HID, EisaId ("PNP0303"))</span><br><span style="color: hsl(120, 100%, 40%);">+ Method (_STA, 0, NotSerialized)</span><br><span style="color: hsl(120, 100%, 40%);">+ {</span><br><span style="color: hsl(120, 100%, 40%);">+ Return (0x0f)</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ Method (_CRS, 0, NotSerialized)</span><br><span style="color: hsl(120, 100%, 40%);">+ {</span><br><span style="color: hsl(120, 100%, 40%);">+ Name (TMP0, ResourceTemplate () {</span><br><span style="color: hsl(120, 100%, 40%);">+ IO (Decode16, 0x0060, 0x0060, 0x01, 0x01)</span><br><span style="color: hsl(120, 100%, 40%);">+ IO (Decode16, 0x0064, 0x0064, 0x01, 0x01)</span><br><span style="color: hsl(120, 100%, 40%);">+ IRQNoFlags () {1}</span><br><span style="color: hsl(120, 100%, 40%);">+ })</span><br><span style="color: hsl(120, 100%, 40%);">+ Return (TMP0)</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* PS/2 mouse */</span><br><span style="color: hsl(120, 100%, 40%);">+ Device (MOU)</span><br><span style="color: hsl(120, 100%, 40%);">+ {</span><br><span style="color: hsl(120, 100%, 40%);">+ Name (_HID, EisaId ("PNP0F13"))</span><br><span style="color: hsl(120, 100%, 40%);">+ Method (_STA, 0, NotSerialized)</span><br><span style="color: hsl(120, 100%, 40%);">+ {</span><br><span style="color: hsl(120, 100%, 40%);">+ Return (0x0f)</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ Method (_CRS, 0, NotSerialized)</span><br><span style="color: hsl(120, 100%, 40%);">+ {</span><br><span style="color: hsl(120, 100%, 40%);">+ Name (TMP1, ResourceTemplate () {</span><br><span style="color: hsl(120, 100%, 40%);">+ IO (Decode16, 0x0060, 0x0060, 0x01, 0x01)</span><br><span style="color: hsl(120, 100%, 40%);">+ IO (Decode16, 0x0064, 0x0064, 0x01, 0x01)</span><br><span style="color: hsl(120, 100%, 40%);">+ IRQNoFlags () {12}</span><br><span style="color: hsl(120, 100%, 40%);">+ })</span><br><span style="color: hsl(120, 100%, 40%);">+ Return (TMP1)</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* PS/2 floppy controller */</span><br><span style="color: hsl(120, 100%, 40%);">+ Device (FDC0)</span><br><span style="color: hsl(120, 100%, 40%);">+ {</span><br><span style="color: hsl(120, 100%, 40%);">+ Name (_HID, EisaId ("PNP0700"))</span><br><span style="color: hsl(120, 100%, 40%);">+ Method (_STA, 0, NotSerialized)</span><br><span style="color: hsl(120, 100%, 40%);">+ {</span><br><span style="color: hsl(120, 100%, 40%);">+ Return (0x0f)</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ Method (_CRS, 0, NotSerialized)</span><br><span style="color: hsl(120, 100%, 40%);">+ {</span><br><span style="color: hsl(120, 100%, 40%);">+ Name (BUF0, ResourceTemplate () {</span><br><span style="color: hsl(120, 100%, 40%);">+ IO (Decode16, 0x03F0, 0x03F0, 0x01, 0x06)</span><br><span style="color: hsl(120, 100%, 40%);">+ IO (Decode16, 0x03F7, 0x03F7, 0x01, 0x01)</span><br><span style="color: hsl(120, 100%, 40%);">+ IRQNoFlags () {6}</span><br><span style="color: hsl(120, 100%, 40%);">+ DMA (Compatibility, NotBusMaster, Transfer8) {2}</span><br><span style="color: hsl(120, 100%, 40%);">+ })</span><br><span style="color: hsl(120, 100%, 40%);">+ Return (BUF0)</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Parallel Port */</span><br><span style="color: hsl(120, 100%, 40%);">+ Device (LPT1)</span><br><span style="color: hsl(120, 100%, 40%);">+ {</span><br><span style="color: hsl(120, 100%, 40%);">+ Name (_HID, EisaId ("PNP0400"))</span><br><span style="color: hsl(120, 100%, 40%);">+ Method (_STA, 0, NotSerialized)</span><br><span style="color: hsl(120, 100%, 40%);">+ {</span><br><span style="color: hsl(120, 100%, 40%);">+ Return (0x0f)</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ Method (_CRS, 0, NotSerialized)</span><br><span style="color: hsl(120, 100%, 40%);">+ {</span><br><span style="color: hsl(120, 100%, 40%);">+ Name (BUF1, ResourceTemplate () {</span><br><span style="color: hsl(120, 100%, 40%);">+ IO (Decode16, 0x0378, 0x0378, 0x01, 0x08)</span><br><span style="color: hsl(120, 100%, 40%);">+ IRQNoFlags () {7}</span><br><span style="color: hsl(120, 100%, 40%);">+ })</span><br><span style="color: hsl(120, 100%, 40%);">+ Return (BUF1)</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Parallel Port ECP */</span><br><span style="color: hsl(120, 100%, 40%);">+ Device (ECP1)</span><br><span style="color: hsl(120, 100%, 40%);">+ {</span><br><span style="color: hsl(120, 100%, 40%);">+ Name (_HID, EisaId ("PNP0401"))</span><br><span style="color: hsl(120, 100%, 40%);">+ Method (_STA, 0, NotSerialized)</span><br><span style="color: hsl(120, 100%, 40%);">+ {</span><br><span style="color: hsl(120, 100%, 40%);">+ Return (0x0f)</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ Method (_CRS, 0, NotSerialized)</span><br><span style="color: hsl(120, 100%, 40%);">+ {</span><br><span style="color: hsl(120, 100%, 40%);">+ Name (BUF1, ResourceTemplate () {</span><br><span style="color: hsl(120, 100%, 40%);">+ IO (Decode16, 0x0378, 0x0378, 0x01, 0x04)</span><br><span style="color: hsl(120, 100%, 40%);">+ IO (Decode16, 0x0778, 0x0778, 0x01, 0x04)</span><br><span style="color: hsl(120, 100%, 40%);">+ IRQNoFlags() {7}</span><br><span style="color: hsl(120, 100%, 40%);">+ DMA (Compatibility, NotBusMaster, Transfer8) {0,1,3}</span><br><span style="color: hsl(120, 100%, 40%);">+ })</span><br><span style="color: hsl(120, 100%, 40%);">+ Return (BUF1)</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span>diff --git a/src/mainboard/gigabyte/m57sli/fanctl.c b/src/mainboard/gigabyte/m57sli/fanctl.c</span><br><span>new file mode 100644</span><br><span>index 0000000..cc0cdca</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/gigabyte/m57sli/fanctl.c</span><br><span>@@ -0,0 +1,81 @@</span><br><span style="color: hsl(120, 100%, 40%);">+#include <arch/io.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <stdlib.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <superio/ite/it8716f/it8716f.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static void write_index(uint16_t port_base, uint8_t reg, uint8_t value)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ outb(reg, port_base);</span><br><span style="color: hsl(120, 100%, 40%);">+ outb(value, port_base + 1);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static const struct {</span><br><span style="color: hsl(120, 100%, 40%);">+ uint8_t index, value;</span><br><span style="color: hsl(120, 100%, 40%);">+} sequence[]= {</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Make sure we can monitor, and enable SMI# interrupt output */</span><br><span style="color: hsl(120, 100%, 40%);">+ { 0x00, 0x13},</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Disable fan interrupt status bits for SMI# */</span><br><span style="color: hsl(120, 100%, 40%);">+ { 0x04, 0x37},</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Disable VIN interrupt status bits for SMI# */</span><br><span style="color: hsl(120, 100%, 40%);">+ { 0x05, 0xff},</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Disable fan interrupt status bits for IRQ */</span><br><span style="color: hsl(120, 100%, 40%);">+ { 0x07, 0x37},</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Disable VIN interrupt status bits for IRQ */</span><br><span style="color: hsl(120, 100%, 40%);">+ { 0x08, 0xff},</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Disable external sensor interrupt */</span><br><span style="color: hsl(120, 100%, 40%);">+ { 0x09, 0x87},</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Enable 16 bit counter divisors */</span><br><span style="color: hsl(120, 100%, 40%);">+ { 0x0c, 0x07},</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Set FAN_CTL control register (0x14) polarity to high, and</span><br><span style="color: hsl(120, 100%, 40%);">+ activate fans 1, 2 and 3. */</span><br><span style="color: hsl(120, 100%, 40%);">+ { 0x14, 0xd7},</span><br><span style="color: hsl(120, 100%, 40%);">+ /* set the correct sensor types 1,2 thermistor; 3 diode */</span><br><span style="color: hsl(120, 100%, 40%);">+ { 0x51, 0x1c},</span><br><span style="color: hsl(120, 100%, 40%);">+ /* set the 'zero' voltage for diode type sensor 3 */</span><br><span style="color: hsl(120, 100%, 40%);">+ { 0x5c, 0x80},</span><br><span style="color: hsl(120, 100%, 40%);">+// { 0x56, 0xe5},</span><br><span style="color: hsl(120, 100%, 40%);">+// { 0x57, 0xe5},</span><br><span style="color: hsl(120, 100%, 40%);">+ { 0x59, 0xec},</span><br><span style="color: hsl(120, 100%, 40%);">+ { 0x5c, 0x00},</span><br><span style="color: hsl(120, 100%, 40%);">+ /* fan1 (controlled by temp3) control parameters */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* fan off limit */</span><br><span style="color: hsl(120, 100%, 40%);">+ { 0x60, 0xff},</span><br><span style="color: hsl(120, 100%, 40%);">+ /* fan start limit */</span><br><span style="color: hsl(120, 100%, 40%);">+ { 0x61, 0x14},</span><br><span style="color: hsl(120, 100%, 40%);">+ /* ???? */</span><br><span style="color: hsl(120, 100%, 40%);">+// { 0x62, 0x00},</span><br><span style="color: hsl(120, 100%, 40%);">+ /* start PWM */</span><br><span style="color: hsl(120, 100%, 40%);">+ { 0x63, 0x27},</span><br><span style="color: hsl(120, 100%, 40%);">+ /* smooth and slope PWM */</span><br><span style="color: hsl(120, 100%, 40%);">+ { 0x64, 0x90},</span><br><span style="color: hsl(120, 100%, 40%);">+ /* direct-down and interval */</span><br><span style="color: hsl(120, 100%, 40%);">+ { 0x65, 0x03},</span><br><span style="color: hsl(120, 100%, 40%);">+ /* temperature limit of fan stop for fan3 (automatic) */</span><br><span style="color: hsl(120, 100%, 40%);">+ { 0x70, 0xff},</span><br><span style="color: hsl(120, 100%, 40%);">+ /* temperature limit of fan start for fan3 (automatic) */</span><br><span style="color: hsl(120, 100%, 40%);">+ { 0x71, 0x14},</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Set PWM start & slope for fan3 */</span><br><span style="color: hsl(120, 100%, 40%);">+ { 0x73, 0x20},</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Initialize PWM automatic mode slope values for fan3 */</span><br><span style="color: hsl(120, 100%, 40%);">+ { 0x74, 0x90},</span><br><span style="color: hsl(120, 100%, 40%);">+ /* set smartguardian temperature interval for fan3 */</span><br><span style="color: hsl(120, 100%, 40%);">+ { 0x75, 0x03},</span><br><span style="color: hsl(120, 100%, 40%);">+ /* fan1 auto controlled by temp3 */</span><br><span style="color: hsl(120, 100%, 40%);">+ { 0x15, 0x82},</span><br><span style="color: hsl(120, 100%, 40%);">+ /* fan2 auto controlled by temp3 */</span><br><span style="color: hsl(120, 100%, 40%);">+ { 0x16, 0x82},</span><br><span style="color: hsl(120, 100%, 40%);">+ /* fan3 auto controlled by temp3 */</span><br><span style="color: hsl(120, 100%, 40%);">+ { 0x17, 0x82},</span><br><span style="color: hsl(120, 100%, 40%);">+ /* all fans enable, fan1 ctl smart */</span><br><span style="color: hsl(120, 100%, 40%);">+ { 0x13, 0x77}</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * Called from superio.c</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+void init_ec(uint16_t base)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ int i;</span><br><span style="color: hsl(120, 100%, 40%);">+ for (i = 0; i < ARRAY_SIZE(sequence); i++) {</span><br><span style="color: hsl(120, 100%, 40%);">+ write_index(base, sequence[i].index, sequence[i].value);</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span>diff --git a/src/mainboard/gigabyte/m57sli/get_bus_conf.c b/src/mainboard/gigabyte/m57sli/get_bus_conf.c</span><br><span>new file mode 100644</span><br><span>index 0000000..75ab89b</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/gigabyte/m57sli/get_bus_conf.c</span><br><span>@@ -0,0 +1,123 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2007 AMD</span><br><span style="color: hsl(120, 100%, 40%);">+ * Written by Yinghai Lu <yinghailu@amd.com> for AMD.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; either version 2 of the License, or</span><br><span style="color: hsl(120, 100%, 40%);">+ * (at your option) any later version.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <console/console.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <device/pci.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <device/pci_ids.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <string.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <stdint.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <cpu/amd/multicore.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <cpu/amd/amdfam10_sysconf.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <stdlib.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// Global variables for MB layouts and these will be shared by irqtable mptable and acpi_tables</span><br><span style="color: hsl(120, 100%, 40%);">+//busnum is default</span><br><span style="color: hsl(120, 100%, 40%);">+unsigned char bus_mcp55[8]; //1</span><br><span style="color: hsl(120, 100%, 40%);">+unsigned apicid_mcp55;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+unsigned pci1234x[] = { //Here you only need to set value in pci1234 for HT-IO that could be installed or not</span><br><span style="color: hsl(120, 100%, 40%);">+ //You may need to preset pci1234 for HTIO board, please refer to src/northbridge/amd/amdk8/get_sblk_pci1234.c for detail</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x0000ff0,</span><br><span style="color: hsl(120, 100%, 40%);">+// 0x0000ff0,</span><br><span style="color: hsl(120, 100%, 40%);">+// 0x0000ff0,</span><br><span style="color: hsl(120, 100%, 40%);">+// 0x0000ff0,</span><br><span style="color: hsl(120, 100%, 40%);">+// 0x0000ff0,</span><br><span style="color: hsl(120, 100%, 40%);">+// 0x0000ff0,</span><br><span style="color: hsl(120, 100%, 40%);">+// 0x0000ff0,</span><br><span style="color: hsl(120, 100%, 40%);">+// 0x0000ff0</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+unsigned hcdnx[] = { //HT Chain device num, actually it is unit id base of every ht device in chain, assume every chain only have 4 ht device at most</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x20202020,</span><br><span style="color: hsl(120, 100%, 40%);">+// 0x20202020,</span><br><span style="color: hsl(120, 100%, 40%);">+// 0x20202020,</span><br><span style="color: hsl(120, 100%, 40%);">+// 0x20202020,</span><br><span style="color: hsl(120, 100%, 40%);">+// 0x20202020,</span><br><span style="color: hsl(120, 100%, 40%);">+// 0x20202020,</span><br><span style="color: hsl(120, 100%, 40%);">+// 0x20202020,</span><br><span style="color: hsl(120, 100%, 40%);">+// 0x20202020,</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+extern void get_pci1234(void);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static unsigned get_bus_conf_done = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+void get_bus_conf(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ unsigned apicid_base;</span><br><span style="color: hsl(120, 100%, 40%);">+ unsigned sbdn;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ device_t dev;</span><br><span style="color: hsl(120, 100%, 40%);">+ int i;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ if (get_bus_conf_done == 1)</span><br><span style="color: hsl(120, 100%, 40%);">+ return; //do it only once</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ get_bus_conf_done = 1;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ sysconf.hc_possible_num = ARRAY_SIZE(pci1234x);</span><br><span style="color: hsl(120, 100%, 40%);">+ for (i = 0; i < sysconf.hc_possible_num; i++) {</span><br><span style="color: hsl(120, 100%, 40%);">+ sysconf.pci1234[i] = pci1234x[i];</span><br><span style="color: hsl(120, 100%, 40%);">+ sysconf.hcdn[i] = hcdnx[i];</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ get_pci1234();</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ sysconf.sbdn = (sysconf.hcdn[0] & 0xff); // first byte of first chain</span><br><span style="color: hsl(120, 100%, 40%);">+ sbdn = sysconf.sbdn;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ for (i = 0; i < 8; i++) {</span><br><span style="color: hsl(120, 100%, 40%);">+ bus_mcp55[i] = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ bus_mcp55[0] = (sysconf.pci1234[0] >> 16) & 0xff;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* MCP55 */</span><br><span style="color: hsl(120, 100%, 40%);">+ dev = dev_find_slot(bus_mcp55[0], PCI_DEVFN(sbdn + 0x06, 0));</span><br><span style="color: hsl(120, 100%, 40%);">+ if (dev) {</span><br><span style="color: hsl(120, 100%, 40%);">+ bus_mcp55[1] = pci_read_config8(dev, PCI_SECONDARY_BUS);</span><br><span style="color: hsl(120, 100%, 40%);">+ bus_mcp55[2] = pci_read_config8(dev, PCI_SUBORDINATE_BUS);</span><br><span style="color: hsl(120, 100%, 40%);">+ bus_mcp55[2]++;</span><br><span style="color: hsl(120, 100%, 40%);">+ } else {</span><br><span style="color: hsl(120, 100%, 40%);">+ printk(BIOS_DEBUG,</span><br><span style="color: hsl(120, 100%, 40%);">+ "ERROR - could not find PCI 1:%02x.0, using defaults\n",</span><br><span style="color: hsl(120, 100%, 40%);">+ sbdn + 0x06);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ bus_mcp55[1] = 2;</span><br><span style="color: hsl(120, 100%, 40%);">+ bus_mcp55[2] = 3;</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ for (i = 2; i < 8; i++) {</span><br><span style="color: hsl(120, 100%, 40%);">+ dev =</span><br><span style="color: hsl(120, 100%, 40%);">+ dev_find_slot(bus_mcp55[0],</span><br><span style="color: hsl(120, 100%, 40%);">+ PCI_DEVFN(sbdn + 0x0a + i - 2, 0));</span><br><span style="color: hsl(120, 100%, 40%);">+ if (dev) {</span><br><span style="color: hsl(120, 100%, 40%);">+ bus_mcp55[i] = pci_read_config8(dev, PCI_SECONDARY_BUS);</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/*I/O APICs: APIC ID Version State Address*/</span><br><span style="color: hsl(120, 100%, 40%);">+ if (IS_ENABLED(CONFIG_LOGICAL_CPUS))</span><br><span style="color: hsl(120, 100%, 40%);">+ apicid_base = get_apicid_base(1);</span><br><span style="color: hsl(120, 100%, 40%);">+ else</span><br><span style="color: hsl(120, 100%, 40%);">+ apicid_base = CONFIG_MAX_PHYSICAL_CPUS;</span><br><span style="color: hsl(120, 100%, 40%);">+ apicid_mcp55 = apicid_base + 0;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span>diff --git a/src/mainboard/gigabyte/m57sli/hda_verb.c b/src/mainboard/gigabyte/m57sli/hda_verb.c</span><br><span>new file mode 100644</span><br><span>index 0000000..072a306</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/gigabyte/m57sli/hda_verb.c</span><br><span>@@ -0,0 +1,7 @@</span><br><span style="color: hsl(120, 100%, 40%);">+#include <device/azalia_device.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+const u32 cim_verb_data[0] = {};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+const u32 pc_beep_verbs[0] = {};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+AZALIA_ARRAY_SIZES;</span><br><span>diff --git a/src/mainboard/gigabyte/m57sli/irq_tables.c b/src/mainboard/gigabyte/m57sli/irq_tables.c</span><br><span>new file mode 100644</span><br><span>index 0000000..5156848</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/gigabyte/m57sli/irq_tables.c</span><br><span>@@ -0,0 +1,111 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2007 AMD</span><br><span style="color: hsl(120, 100%, 40%);">+ * Written by Yinghai Lu <yinghailu@amd.com> for AMD.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; either version 2 of the License, or</span><br><span style="color: hsl(120, 100%, 40%);">+ * (at your option) any later version.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <console/console.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <device/pci.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <string.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <stdint.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <arch/pirq_routing.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <cpu/amd/amdfam10_sysconf.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static void write_pirq_info(struct irq_info *pirq_info, uint8_t bus,</span><br><span style="color: hsl(120, 100%, 40%);">+ uint8_t devfn, uint8_t link0, uint16_t bitmap0,</span><br><span style="color: hsl(120, 100%, 40%);">+ uint8_t link1, uint16_t bitmap1, uint8_t link2,</span><br><span style="color: hsl(120, 100%, 40%);">+ uint16_t bitmap2, uint8_t link3, uint16_t bitmap3,</span><br><span style="color: hsl(120, 100%, 40%);">+ uint8_t slot, uint8_t rfu)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ pirq_info->bus = bus;</span><br><span style="color: hsl(120, 100%, 40%);">+ pirq_info->devfn = devfn;</span><br><span style="color: hsl(120, 100%, 40%);">+ pirq_info->irq[0].link = link0;</span><br><span style="color: hsl(120, 100%, 40%);">+ pirq_info->irq[0].bitmap = bitmap0;</span><br><span style="color: hsl(120, 100%, 40%);">+ pirq_info->irq[1].link = link1;</span><br><span style="color: hsl(120, 100%, 40%);">+ pirq_info->irq[1].bitmap = bitmap1;</span><br><span style="color: hsl(120, 100%, 40%);">+ pirq_info->irq[2].link = link2;</span><br><span style="color: hsl(120, 100%, 40%);">+ pirq_info->irq[2].bitmap = bitmap2;</span><br><span style="color: hsl(120, 100%, 40%);">+ pirq_info->irq[3].link = link3;</span><br><span style="color: hsl(120, 100%, 40%);">+ pirq_info->irq[3].bitmap = bitmap3;</span><br><span style="color: hsl(120, 100%, 40%);">+ pirq_info->slot = slot;</span><br><span style="color: hsl(120, 100%, 40%);">+ pirq_info->rfu = rfu;</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+extern unsigned char bus_mcp55[8]; //1</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+unsigned long write_pirq_routing_table(unsigned long addr)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ struct irq_routing_table *pirq;</span><br><span style="color: hsl(120, 100%, 40%);">+ struct irq_info *pirq_info;</span><br><span style="color: hsl(120, 100%, 40%);">+ unsigned slot_num;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint8_t *v;</span><br><span style="color: hsl(120, 100%, 40%);">+ unsigned sbdn;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ uint8_t sum = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+ int i;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ get_bus_conf(); // it will find out all bus num and apic that share with mptable.c and mptable.c and acpi_tables.c</span><br><span style="color: hsl(120, 100%, 40%);">+ sbdn = sysconf.sbdn;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Align the table to be 16 byte aligned. */</span><br><span style="color: hsl(120, 100%, 40%);">+ addr += 15;</span><br><span style="color: hsl(120, 100%, 40%);">+ addr &= ~15;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* This table must be between 0xf0000 & 0x100000 */</span><br><span style="color: hsl(120, 100%, 40%);">+ printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ pirq = (void *)(addr);</span><br><span style="color: hsl(120, 100%, 40%);">+ v = (uint8_t *) (addr);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ pirq->signature = PIRQ_SIGNATURE;</span><br><span style="color: hsl(120, 100%, 40%);">+ pirq->version = PIRQ_VERSION;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ pirq->rtr_bus = bus_mcp55[0];</span><br><span style="color: hsl(120, 100%, 40%);">+ pirq->rtr_devfn = ((sbdn + 6) << 3) | 0;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ pirq->exclusive_irqs = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ pirq->rtr_vendor = 0x10de;</span><br><span style="color: hsl(120, 100%, 40%);">+ pirq->rtr_device = 0x0370;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ pirq->miniport_data = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ memset(pirq->rfu, 0, sizeof(pirq->rfu));</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ pirq_info = (void *)(&pirq->checksum + 1);</span><br><span style="color: hsl(120, 100%, 40%);">+ slot_num = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+//pci bridge</span><br><span style="color: hsl(120, 100%, 40%);">+ write_pirq_info(pirq_info, bus_mcp55[0], ((sbdn + 6) << 3) | 0, 0x1,</span><br><span style="color: hsl(120, 100%, 40%);">+ 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0);</span><br><span style="color: hsl(120, 100%, 40%);">+ pirq_info++;</span><br><span style="color: hsl(120, 100%, 40%);">+ slot_num++;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ pirq->size = 32 + 16 * slot_num;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ for (i = 0; i < pirq->size; i++)</span><br><span style="color: hsl(120, 100%, 40%);">+ sum += v[i];</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ sum = pirq->checksum - sum;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ if (sum != pirq->checksum) {</span><br><span style="color: hsl(120, 100%, 40%);">+ pirq->checksum = sum;</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ printk(BIOS_INFO, "done.\n");</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ return (unsigned long)pirq_info;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span>diff --git a/src/mainboard/gigabyte/m57sli/mptable.c b/src/mainboard/gigabyte/m57sli/mptable.c</span><br><span>new file mode 100644</span><br><span>index 0000000..d776551</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/gigabyte/m57sli/mptable.c</span><br><span>@@ -0,0 +1,122 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2007 AMD</span><br><span style="color: hsl(120, 100%, 40%);">+ * Written by Yinghai Lu <yinghailu@amd.com> for AMD.</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2009 Harald Gutmann <harald.gutmann@gmx.net></span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; either version 2 of the License, or</span><br><span style="color: hsl(120, 100%, 40%);">+ * (at your option) any later version.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <console/console.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <arch/smp/mpspec.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <device/pci.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <string.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <stdint.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <cpu/amd/amdfam10_sysconf.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+extern unsigned char bus_mcp55[8]; //1</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+extern unsigned apicid_mcp55;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static void *smp_write_config_table(void *v)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ struct mp_config_table *mc;</span><br><span style="color: hsl(120, 100%, 40%);">+ unsigned sbdn;</span><br><span style="color: hsl(120, 100%, 40%);">+ int i, j, k, bus_isa;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ mptable_init(mc, LOCAL_APIC_ADDR);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ smp_write_processors(mc);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ get_bus_conf();</span><br><span style="color: hsl(120, 100%, 40%);">+ sbdn = sysconf.sbdn;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ mptable_write_buses(mc, NULL, &bus_isa);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/*I/O APICs: APIC ID Version State Address*/</span><br><span style="color: hsl(120, 100%, 40%);">+ {</span><br><span style="color: hsl(120, 100%, 40%);">+ device_t dev;</span><br><span style="color: hsl(120, 100%, 40%);">+ struct resource *res;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ dev = dev_find_slot(bus_mcp55[0], PCI_DEVFN(sbdn+ 0x1,0));</span><br><span style="color: hsl(120, 100%, 40%);">+ if (dev) {</span><br><span style="color: hsl(120, 100%, 40%);">+ res = find_resource(dev, PCI_BASE_ADDRESS_1);</span><br><span style="color: hsl(120, 100%, 40%);">+ if (res) {</span><br><span style="color: hsl(120, 100%, 40%);">+ smp_write_ioapic(mc, apicid_mcp55, 0x11,</span><br><span style="color: hsl(120, 100%, 40%);">+ res2mmio(res, 0, 0));</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ /* set up the interrupt registers of mcp55 */</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_write_config32(dev, 0x7c, 0xc643c643);</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_write_config32(dev, 0x80, 0x8da01009);</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_write_config32(dev, 0x84, 0x200018d2);</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ mptable_add_isa_interrupts(mc, bus_isa, apicid_mcp55, 0);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* PCI interrupts are level triggered, and are</span><br><span style="color: hsl(120, 100%, 40%);">+ * associated with a specific bus/device/function tuple.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCI_INT(bus, dev, fn, pin) \</span><br><span style="color: hsl(120, 100%, 40%);">+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,\</span><br><span style="color: hsl(120, 100%, 40%);">+ bus_mcp55[bus], (((dev)<<2)|(fn)), apicid_mcp55, (pin))</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ PCI_INT(0,sbdn+1,1, 10); /* SMBus */</span><br><span style="color: hsl(120, 100%, 40%);">+ PCI_INT(0,sbdn+2,0, 22); /* USB */</span><br><span style="color: hsl(120, 100%, 40%);">+ PCI_INT(0,sbdn+2,1, 23); /* USB */</span><br><span style="color: hsl(120, 100%, 40%);">+ PCI_INT(0,sbdn+4,0, 21); /* IDE */</span><br><span style="color: hsl(120, 100%, 40%);">+ PCI_INT(0,sbdn+5,0, 20); /* SATA */</span><br><span style="color: hsl(120, 100%, 40%);">+ PCI_INT(0,sbdn+5,1, 21); /* SATA */</span><br><span style="color: hsl(120, 100%, 40%);">+ PCI_INT(0,sbdn+5,2, 22); /* SATA */</span><br><span style="color: hsl(120, 100%, 40%);">+ PCI_INT(0,sbdn+6,1, 23); /* HD Audio */</span><br><span style="color: hsl(120, 100%, 40%);">+ PCI_INT(0,sbdn+8,0, 20); /* GBit Ethernet */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* The PCIe slots, each on its own bus */</span><br><span style="color: hsl(120, 100%, 40%);">+ k = 1;</span><br><span style="color: hsl(120, 100%, 40%);">+ for(i = 0; i < 4; i++){</span><br><span style="color: hsl(120, 100%, 40%);">+ for(j = 7; j > 1; j--){</span><br><span style="color: hsl(120, 100%, 40%);">+ if(k > 3) k = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+ PCI_INT(j,0,i, 16+k);</span><br><span style="color: hsl(120, 100%, 40%);">+ k++;</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ k--;</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* On bus 1: the PCI bus slots...</span><br><span style="color: hsl(120, 100%, 40%);">+ * physical PCI slots are j = 7,8</span><br><span style="color: hsl(120, 100%, 40%);">+ * FireWire is j = 10</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+ k = 2;</span><br><span style="color: hsl(120, 100%, 40%);">+ for(i = 0; i < 4; i++){</span><br><span style="color: hsl(120, 100%, 40%);">+ for(j = 6; j < 11; j++){</span><br><span style="color: hsl(120, 100%, 40%);">+ if(k > 3) k = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+ PCI_INT(1,j,i, 16+k);</span><br><span style="color: hsl(120, 100%, 40%);">+ k++;</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/</span><br><span style="color: hsl(120, 100%, 40%);">+ mptable_lintsrc(mc, bus_isa);</span><br><span style="color: hsl(120, 100%, 40%);">+ /* There is no extension information... */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Compute the checksums */</span><br><span style="color: hsl(120, 100%, 40%);">+ return mptable_finalize(mc);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+unsigned long write_smp_table(unsigned long addr)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ void *v;</span><br><span style="color: hsl(120, 100%, 40%);">+ v = smp_write_floating_table(addr, 0);</span><br><span style="color: hsl(120, 100%, 40%);">+ return (unsigned long)smp_write_config_table(v);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span>diff --git a/src/mainboard/gigabyte/m57sli/resourcemap.c b/src/mainboard/gigabyte/m57sli/resourcemap.c</span><br><span>new file mode 100644</span><br><span>index 0000000..4b1f495</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/gigabyte/m57sli/resourcemap.c</span><br><span>@@ -0,0 +1,278 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2007 AMD</span><br><span style="color: hsl(120, 100%, 40%);">+ * Written by Yinghai Lu <yinghailu@amd.com> for AMD.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; either version 2 of the License, or</span><br><span style="color: hsl(120, 100%, 40%);">+ * (at your option) any later version.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static void setup_mb_resource_map(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ static const unsigned int register_values[] = {</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Careful set limit registers before base registers which contain the enables */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* DRAM Limit i Registers</span><br><span style="color: hsl(120, 100%, 40%);">+ * F1:0x44 i = 0</span><br><span style="color: hsl(120, 100%, 40%);">+ * F1:0x4C i = 1</span><br><span style="color: hsl(120, 100%, 40%);">+ * F1:0x54 i = 2</span><br><span style="color: hsl(120, 100%, 40%);">+ * F1:0x5C i = 3</span><br><span style="color: hsl(120, 100%, 40%);">+ * F1:0x64 i = 4</span><br><span style="color: hsl(120, 100%, 40%);">+ * F1:0x6C i = 5</span><br><span style="color: hsl(120, 100%, 40%);">+ * F1:0x74 i = 6</span><br><span style="color: hsl(120, 100%, 40%);">+ * F1:0x7C i = 7</span><br><span style="color: hsl(120, 100%, 40%);">+ * [ 2: 0] Destination Node ID</span><br><span style="color: hsl(120, 100%, 40%);">+ * 000 = Node 0</span><br><span style="color: hsl(120, 100%, 40%);">+ * 001 = Node 1</span><br><span style="color: hsl(120, 100%, 40%);">+ * 010 = Node 2</span><br><span style="color: hsl(120, 100%, 40%);">+ * 011 = Node 3</span><br><span style="color: hsl(120, 100%, 40%);">+ * 100 = Node 4</span><br><span style="color: hsl(120, 100%, 40%);">+ * 101 = Node 5</span><br><span style="color: hsl(120, 100%, 40%);">+ * 110 = Node 6</span><br><span style="color: hsl(120, 100%, 40%);">+ * 111 = Node 7</span><br><span style="color: hsl(120, 100%, 40%);">+ * [ 7: 3] Reserved</span><br><span style="color: hsl(120, 100%, 40%);">+ * [10: 8] Interleave select</span><br><span style="color: hsl(120, 100%, 40%);">+ * specifies the values of A[14:12] to use with interleave enable.</span><br><span style="color: hsl(120, 100%, 40%);">+ * [15:11] Reserved</span><br><span style="color: hsl(120, 100%, 40%);">+ * [31:16] DRAM Limit Address i Bits 39-24</span><br><span style="color: hsl(120, 100%, 40%);">+ * This field defines the upper address bits of a 40 bit address</span><br><span style="color: hsl(120, 100%, 40%);">+ * that define the end of the DRAM region.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+// PCI_ADDR(0, 0x18, 1, 0x44), 0x0000f8f8, 0x00000000, Need for CAR with FAM10</span><br><span style="color: hsl(120, 100%, 40%);">+ PCI_ADDR(0, 0x18, 1, 0x4C), 0x0000f8f8, 0x00000001,</span><br><span style="color: hsl(120, 100%, 40%);">+ PCI_ADDR(0, 0x18, 1, 0x54), 0x0000f8f8, 0x00000002,</span><br><span style="color: hsl(120, 100%, 40%);">+ PCI_ADDR(0, 0x18, 1, 0x5C), 0x0000f8f8, 0x00000003,</span><br><span style="color: hsl(120, 100%, 40%);">+ PCI_ADDR(0, 0x18, 1, 0x64), 0x0000f8f8, 0x00000004,</span><br><span style="color: hsl(120, 100%, 40%);">+ PCI_ADDR(0, 0x18, 1, 0x6C), 0x0000f8f8, 0x00000005,</span><br><span style="color: hsl(120, 100%, 40%);">+ PCI_ADDR(0, 0x18, 1, 0x74), 0x0000f8f8, 0x00000006,</span><br><span style="color: hsl(120, 100%, 40%);">+ PCI_ADDR(0, 0x18, 1, 0x7C), 0x0000f8f8, 0x00000007,</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* DRAM Base i Registers</span><br><span style="color: hsl(120, 100%, 40%);">+ * F1:0x40 i = 0</span><br><span style="color: hsl(120, 100%, 40%);">+ * F1:0x48 i = 1</span><br><span style="color: hsl(120, 100%, 40%);">+ * F1:0x50 i = 2</span><br><span style="color: hsl(120, 100%, 40%);">+ * F1:0x58 i = 3</span><br><span style="color: hsl(120, 100%, 40%);">+ * F1:0x60 i = 4</span><br><span style="color: hsl(120, 100%, 40%);">+ * F1:0x68 i = 5</span><br><span style="color: hsl(120, 100%, 40%);">+ * F1:0x70 i = 6</span><br><span style="color: hsl(120, 100%, 40%);">+ * F1:0x78 i = 7</span><br><span style="color: hsl(120, 100%, 40%);">+ * [ 0: 0] Read Enable</span><br><span style="color: hsl(120, 100%, 40%);">+ * 0 = Reads Disabled</span><br><span style="color: hsl(120, 100%, 40%);">+ * 1 = Reads Enabled</span><br><span style="color: hsl(120, 100%, 40%);">+ * [ 1: 1] Write Enable</span><br><span style="color: hsl(120, 100%, 40%);">+ * 0 = Writes Disabled</span><br><span style="color: hsl(120, 100%, 40%);">+ * 1 = Writes Enabled</span><br><span style="color: hsl(120, 100%, 40%);">+ * [ 7: 2] Reserved</span><br><span style="color: hsl(120, 100%, 40%);">+ * [10: 8] Interleave Enable</span><br><span style="color: hsl(120, 100%, 40%);">+ * 000 = No interleave</span><br><span style="color: hsl(120, 100%, 40%);">+ * 001 = Interleave on A[12] (2 nodes)</span><br><span style="color: hsl(120, 100%, 40%);">+ * 010 = reserved</span><br><span style="color: hsl(120, 100%, 40%);">+ * 011 = Interleave on A[12] and A[14] (4 nodes)</span><br><span style="color: hsl(120, 100%, 40%);">+ * 100 = reserved</span><br><span style="color: hsl(120, 100%, 40%);">+ * 101 = reserved</span><br><span style="color: hsl(120, 100%, 40%);">+ * 110 = reserved</span><br><span style="color: hsl(120, 100%, 40%);">+ * 111 = Interleve on A[12] and A[13] and A[14] (8 nodes)</span><br><span style="color: hsl(120, 100%, 40%);">+ * [15:11] Reserved</span><br><span style="color: hsl(120, 100%, 40%);">+ * [13:16] DRAM Base Address i Bits 39-24</span><br><span style="color: hsl(120, 100%, 40%);">+ * This field defines the upper address bits of a 40-bit address</span><br><span style="color: hsl(120, 100%, 40%);">+ * that define the start of the DRAM region.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+// PCI_ADDR(0, 0x18, 1, 0x40), 0x0000f8fc, 0x00000000, need for CAR with FAM10</span><br><span style="color: hsl(120, 100%, 40%);">+ PCI_ADDR(0, 0x18, 1, 0x48), 0x0000f8fc, 0x00000000,</span><br><span style="color: hsl(120, 100%, 40%);">+ PCI_ADDR(0, 0x18, 1, 0x50), 0x0000f8fc, 0x00000000,</span><br><span style="color: hsl(120, 100%, 40%);">+ PCI_ADDR(0, 0x18, 1, 0x58), 0x0000f8fc, 0x00000000,</span><br><span style="color: hsl(120, 100%, 40%);">+ PCI_ADDR(0, 0x18, 1, 0x60), 0x0000f8fc, 0x00000000,</span><br><span style="color: hsl(120, 100%, 40%);">+ PCI_ADDR(0, 0x18, 1, 0x68), 0x0000f8fc, 0x00000000,</span><br><span style="color: hsl(120, 100%, 40%);">+ PCI_ADDR(0, 0x18, 1, 0x70), 0x0000f8fc, 0x00000000,</span><br><span style="color: hsl(120, 100%, 40%);">+ PCI_ADDR(0, 0x18, 1, 0x78), 0x0000f8fc, 0x00000000,</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Memory-Mapped I/O Limit i Registers</span><br><span style="color: hsl(120, 100%, 40%);">+ * F1:0x84 i = 0</span><br><span style="color: hsl(120, 100%, 40%);">+ * F1:0x8C i = 1</span><br><span style="color: hsl(120, 100%, 40%);">+ * F1:0x94 i = 2</span><br><span style="color: hsl(120, 100%, 40%);">+ * F1:0x9C i = 3</span><br><span style="color: hsl(120, 100%, 40%);">+ * F1:0xA4 i = 4</span><br><span style="color: hsl(120, 100%, 40%);">+ * F1:0xAC i = 5</span><br><span style="color: hsl(120, 100%, 40%);">+ * F1:0xB4 i = 6</span><br><span style="color: hsl(120, 100%, 40%);">+ * F1:0xBC i = 7</span><br><span style="color: hsl(120, 100%, 40%);">+ * [ 2: 0] Destination Node ID</span><br><span style="color: hsl(120, 100%, 40%);">+ * 000 = Node 0</span><br><span style="color: hsl(120, 100%, 40%);">+ * 001 = Node 1</span><br><span style="color: hsl(120, 100%, 40%);">+ * 010 = Node 2</span><br><span style="color: hsl(120, 100%, 40%);">+ * 011 = Node 3</span><br><span style="color: hsl(120, 100%, 40%);">+ * 100 = Node 4</span><br><span style="color: hsl(120, 100%, 40%);">+ * 101 = Node 5</span><br><span style="color: hsl(120, 100%, 40%);">+ * 110 = Node 6</span><br><span style="color: hsl(120, 100%, 40%);">+ * 111 = Node 7</span><br><span style="color: hsl(120, 100%, 40%);">+ * [ 3: 3] Reserved</span><br><span style="color: hsl(120, 100%, 40%);">+ * [ 5: 4] Destination Link ID</span><br><span style="color: hsl(120, 100%, 40%);">+ * 00 = Link 0</span><br><span style="color: hsl(120, 100%, 40%);">+ * 01 = Link 1</span><br><span style="color: hsl(120, 100%, 40%);">+ * 10 = Link 2</span><br><span style="color: hsl(120, 100%, 40%);">+ * 11 = Reserved</span><br><span style="color: hsl(120, 100%, 40%);">+ * [ 6: 6] Reserved</span><br><span style="color: hsl(120, 100%, 40%);">+ * [ 7: 7] Non-Posted</span><br><span style="color: hsl(120, 100%, 40%);">+ * 0 = CPU writes may be posted</span><br><span style="color: hsl(120, 100%, 40%);">+ * 1 = CPU writes must be non-posted</span><br><span style="color: hsl(120, 100%, 40%);">+ * [31: 8] Memory-Mapped I/O Limit Address i (39-16)</span><br><span style="color: hsl(120, 100%, 40%);">+ * This field defines the upp adddress bits of a 40-bit address that</span><br><span style="color: hsl(120, 100%, 40%);">+ * defines the end of a memory-mapped I/O region n</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+ PCI_ADDR(0, 0x18, 1, 0x84), 0x00000048, 0x00000000,</span><br><span style="color: hsl(120, 100%, 40%);">+ PCI_ADDR(0, 0x18, 1, 0x8C), 0x00000048, 0x00000000,</span><br><span style="color: hsl(120, 100%, 40%);">+ PCI_ADDR(0, 0x18, 1, 0x94), 0x00000048, 0x00000000,</span><br><span style="color: hsl(120, 100%, 40%);">+ PCI_ADDR(0, 0x18, 1, 0x9C), 0x00000048, 0x00000000,</span><br><span style="color: hsl(120, 100%, 40%);">+ PCI_ADDR(0, 0x18, 1, 0xA4), 0x00000048, 0x00000000,</span><br><span style="color: hsl(120, 100%, 40%);">+ PCI_ADDR(0, 0x18, 1, 0xAC), 0x00000048, 0x00000000,</span><br><span style="color: hsl(120, 100%, 40%);">+ PCI_ADDR(0, 0x18, 1, 0xB4), 0x00000048, 0x00000000,</span><br><span style="color: hsl(120, 100%, 40%);">+// PCI_ADDR(0, 0x18, 1, 0xBC), 0x00000048, 0x00ffff00,</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Memory-Mapped I/O Base i Registers</span><br><span style="color: hsl(120, 100%, 40%);">+ * F1:0x80 i = 0</span><br><span style="color: hsl(120, 100%, 40%);">+ * F1:0x88 i = 1</span><br><span style="color: hsl(120, 100%, 40%);">+ * F1:0x90 i = 2</span><br><span style="color: hsl(120, 100%, 40%);">+ * F1:0x98 i = 3</span><br><span style="color: hsl(120, 100%, 40%);">+ * F1:0xA0 i = 4</span><br><span style="color: hsl(120, 100%, 40%);">+ * F1:0xA8 i = 5</span><br><span style="color: hsl(120, 100%, 40%);">+ * F1:0xB0 i = 6</span><br><span style="color: hsl(120, 100%, 40%);">+ * F1:0xB8 i = 7</span><br><span style="color: hsl(120, 100%, 40%);">+ * [ 0: 0] Read Enable</span><br><span style="color: hsl(120, 100%, 40%);">+ * 0 = Reads disabled</span><br><span style="color: hsl(120, 100%, 40%);">+ * 1 = Reads Enabled</span><br><span style="color: hsl(120, 100%, 40%);">+ * [ 1: 1] Write Enable</span><br><span style="color: hsl(120, 100%, 40%);">+ * 0 = Writes disabled</span><br><span style="color: hsl(120, 100%, 40%);">+ * 1 = Writes Enabled</span><br><span style="color: hsl(120, 100%, 40%);">+ * [ 2: 2] Cpu Disable</span><br><span style="color: hsl(120, 100%, 40%);">+ * 0 = Cpu can use this I/O range</span><br><span style="color: hsl(120, 100%, 40%);">+ * 1 = Cpu requests do not use this I/O range</span><br><span style="color: hsl(120, 100%, 40%);">+ * [ 3: 3] Lock</span><br><span style="color: hsl(120, 100%, 40%);">+ * 0 = base/limit registers i are read/write</span><br><span style="color: hsl(120, 100%, 40%);">+ * 1 = base/limit registers i are read-only</span><br><span style="color: hsl(120, 100%, 40%);">+ * [ 7: 4] Reserved</span><br><span style="color: hsl(120, 100%, 40%);">+ * [31: 8] Memory-Mapped I/O Base Address i (39-16)</span><br><span style="color: hsl(120, 100%, 40%);">+ * This field defines the upper address bits of a 40bit address</span><br><span style="color: hsl(120, 100%, 40%);">+ * that defines the start of memory-mapped I/O region i</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+ PCI_ADDR(0, 0x18, 1, 0x80), 0x000000f0, 0x00000000,</span><br><span style="color: hsl(120, 100%, 40%);">+ PCI_ADDR(0, 0x18, 1, 0x88), 0x000000f0, 0x00000000,</span><br><span style="color: hsl(120, 100%, 40%);">+ PCI_ADDR(0, 0x18, 1, 0x90), 0x000000f0, 0x00000000,</span><br><span style="color: hsl(120, 100%, 40%);">+ PCI_ADDR(0, 0x18, 1, 0x98), 0x000000f0, 0x00000000,</span><br><span style="color: hsl(120, 100%, 40%);">+ PCI_ADDR(0, 0x18, 1, 0xA0), 0x000000f0, 0x00000000,</span><br><span style="color: hsl(120, 100%, 40%);">+ PCI_ADDR(0, 0x18, 1, 0xA8), 0x000000f0, 0x00000000,</span><br><span style="color: hsl(120, 100%, 40%);">+ PCI_ADDR(0, 0x18, 1, 0xB0), 0x000000f0, 0x00000000,</span><br><span style="color: hsl(120, 100%, 40%);">+// PCI_ADDR(0, 0x18, 1, 0xB8), 0x000000f0, 0x00fc0003,</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* PCI I/O Limit i Registers</span><br><span style="color: hsl(120, 100%, 40%);">+ * F1:0xC4 i = 0</span><br><span style="color: hsl(120, 100%, 40%);">+ * F1:0xCC i = 1</span><br><span style="color: hsl(120, 100%, 40%);">+ * F1:0xD4 i = 2</span><br><span style="color: hsl(120, 100%, 40%);">+ * F1:0xDC i = 3</span><br><span style="color: hsl(120, 100%, 40%);">+ * [ 2: 0] Destination Node ID</span><br><span style="color: hsl(120, 100%, 40%);">+ * 000 = Node 0</span><br><span style="color: hsl(120, 100%, 40%);">+ * 001 = Node 1</span><br><span style="color: hsl(120, 100%, 40%);">+ * 010 = Node 2</span><br><span style="color: hsl(120, 100%, 40%);">+ * 011 = Node 3</span><br><span style="color: hsl(120, 100%, 40%);">+ * 100 = Node 4</span><br><span style="color: hsl(120, 100%, 40%);">+ * 101 = Node 5</span><br><span style="color: hsl(120, 100%, 40%);">+ * 110 = Node 6</span><br><span style="color: hsl(120, 100%, 40%);">+ * 111 = Node 7</span><br><span style="color: hsl(120, 100%, 40%);">+ * [ 3: 3] Reserved</span><br><span style="color: hsl(120, 100%, 40%);">+ * [ 5: 4] Destination Link ID</span><br><span style="color: hsl(120, 100%, 40%);">+ * 00 = Link 0</span><br><span style="color: hsl(120, 100%, 40%);">+ * 01 = Link 1</span><br><span style="color: hsl(120, 100%, 40%);">+ * 10 = Link 2</span><br><span style="color: hsl(120, 100%, 40%);">+ * 11 = reserved</span><br><span style="color: hsl(120, 100%, 40%);">+ * [11: 6] Reserved</span><br><span style="color: hsl(120, 100%, 40%);">+ * [24:12] PCI I/O Limit Address i</span><br><span style="color: hsl(120, 100%, 40%);">+ * This field defines the end of PCI I/O region n</span><br><span style="color: hsl(120, 100%, 40%);">+ * [31:25] Reserved</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+// PCI_ADDR(0, 0x18, 1, 0xC4), 0xFE000FC8, 0x00007000,</span><br><span style="color: hsl(120, 100%, 40%);">+ PCI_ADDR(0, 0x18, 1, 0xCC), 0xFE000FC8, 0x00000000,</span><br><span style="color: hsl(120, 100%, 40%);">+ PCI_ADDR(0, 0x18, 1, 0xD4), 0xFE000FC8, 0x00000000,</span><br><span style="color: hsl(120, 100%, 40%);">+ PCI_ADDR(0, 0x18, 1, 0xDC), 0xFE000FC8, 0x00000000,</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* PCI I/O Base i Registers</span><br><span style="color: hsl(120, 100%, 40%);">+ * F1:0xC0 i = 0</span><br><span style="color: hsl(120, 100%, 40%);">+ * F1:0xC8 i = 1</span><br><span style="color: hsl(120, 100%, 40%);">+ * F1:0xD0 i = 2</span><br><span style="color: hsl(120, 100%, 40%);">+ * F1:0xD8 i = 3</span><br><span style="color: hsl(120, 100%, 40%);">+ * [ 0: 0] Read Enable</span><br><span style="color: hsl(120, 100%, 40%);">+ * 0 = Reads Disabled</span><br><span style="color: hsl(120, 100%, 40%);">+ * 1 = Reads Enabled</span><br><span style="color: hsl(120, 100%, 40%);">+ * [ 1: 1] Write Enable</span><br><span style="color: hsl(120, 100%, 40%);">+ * 0 = Writes Disabled</span><br><span style="color: hsl(120, 100%, 40%);">+ * 1 = Writes Enabled</span><br><span style="color: hsl(120, 100%, 40%);">+ * [ 3: 2] Reserved</span><br><span style="color: hsl(120, 100%, 40%);">+ * [ 4: 4] VGA Enable</span><br><span style="color: hsl(120, 100%, 40%);">+ * 0 = VGA matches Disabled</span><br><span style="color: hsl(120, 100%, 40%);">+ * 1 = matches all address < 64K and where A[9:0] is in the</span><br><span style="color: hsl(120, 100%, 40%);">+ * range 3B0-3BB or 3C0-3DF independen of the base & limit registers</span><br><span style="color: hsl(120, 100%, 40%);">+ * [ 5: 5] ISA Enable</span><br><span style="color: hsl(120, 100%, 40%);">+ * 0 = ISA matches Disabled</span><br><span style="color: hsl(120, 100%, 40%);">+ * 1 = Blocks address < 64K and in the last 768 bytes of eack 1K block</span><br><span style="color: hsl(120, 100%, 40%);">+ * from matching agains this base/limit pair</span><br><span style="color: hsl(120, 100%, 40%);">+ * [11: 6] Reserved</span><br><span style="color: hsl(120, 100%, 40%);">+ * [24:12] PCI I/O Base i</span><br><span style="color: hsl(120, 100%, 40%);">+ * This field defines the start of PCI I/O region n</span><br><span style="color: hsl(120, 100%, 40%);">+ * [31:25] Reserved</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+// PCI_ADDR(0, 0x18, 1, 0xC0), 0xFE000FCC, 0x00000033,</span><br><span style="color: hsl(120, 100%, 40%);">+ PCI_ADDR(0, 0x18, 1, 0xC8), 0xFE000FCC, 0x00000000,</span><br><span style="color: hsl(120, 100%, 40%);">+ PCI_ADDR(0, 0x18, 1, 0xD0), 0xFE000FCC, 0x00000000,</span><br><span style="color: hsl(120, 100%, 40%);">+ PCI_ADDR(0, 0x18, 1, 0xD8), 0xFE000FCC, 0x00000000,</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Config Base and Limit i Registers</span><br><span style="color: hsl(120, 100%, 40%);">+ * F1:0xE0 i = 0</span><br><span style="color: hsl(120, 100%, 40%);">+ * F1:0xE4 i = 1</span><br><span style="color: hsl(120, 100%, 40%);">+ * F1:0xE8 i = 2</span><br><span style="color: hsl(120, 100%, 40%);">+ * F1:0xEC i = 3</span><br><span style="color: hsl(120, 100%, 40%);">+ * [ 0: 0] Read Enable</span><br><span style="color: hsl(120, 100%, 40%);">+ * 0 = Reads Disabled</span><br><span style="color: hsl(120, 100%, 40%);">+ * 1 = Reads Enabled</span><br><span style="color: hsl(120, 100%, 40%);">+ * [ 1: 1] Write Enable</span><br><span style="color: hsl(120, 100%, 40%);">+ * 0 = Writes Disabled</span><br><span style="color: hsl(120, 100%, 40%);">+ * 1 = Writes Enabled</span><br><span style="color: hsl(120, 100%, 40%);">+ * [ 2: 2] Device Number Compare Enable</span><br><span style="color: hsl(120, 100%, 40%);">+ * 0 = The ranges are based on bus number</span><br><span style="color: hsl(120, 100%, 40%);">+ * 1 = The ranges are ranges of devices on bus 0</span><br><span style="color: hsl(120, 100%, 40%);">+ * [ 3: 3] Reserved</span><br><span style="color: hsl(120, 100%, 40%);">+ * [ 6: 4] Destination Node</span><br><span style="color: hsl(120, 100%, 40%);">+ * 000 = Node 0</span><br><span style="color: hsl(120, 100%, 40%);">+ * 001 = Node 1</span><br><span style="color: hsl(120, 100%, 40%);">+ * 010 = Node 2</span><br><span style="color: hsl(120, 100%, 40%);">+ * 011 = Node 3</span><br><span style="color: hsl(120, 100%, 40%);">+ * 100 = Node 4</span><br><span style="color: hsl(120, 100%, 40%);">+ * 101 = Node 5</span><br><span style="color: hsl(120, 100%, 40%);">+ * 110 = Node 6</span><br><span style="color: hsl(120, 100%, 40%);">+ * 111 = Node 7</span><br><span style="color: hsl(120, 100%, 40%);">+ * [ 7: 7] Reserved</span><br><span style="color: hsl(120, 100%, 40%);">+ * [ 9: 8] Destination Link</span><br><span style="color: hsl(120, 100%, 40%);">+ * 00 = Link 0</span><br><span style="color: hsl(120, 100%, 40%);">+ * 01 = Link 1</span><br><span style="color: hsl(120, 100%, 40%);">+ * 10 = Link 2</span><br><span style="color: hsl(120, 100%, 40%);">+ * 11 - Reserved</span><br><span style="color: hsl(120, 100%, 40%);">+ * [15:10] Reserved</span><br><span style="color: hsl(120, 100%, 40%);">+ * [23:16] Bus Number Base i</span><br><span style="color: hsl(120, 100%, 40%);">+ * This field defines the lowest bus number in configuration region i</span><br><span style="color: hsl(120, 100%, 40%);">+ * [31:24] Bus Number Limit i</span><br><span style="color: hsl(120, 100%, 40%);">+ * This field defines the highest bus number in configuration region i</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+// PCI_ADDR(0, 0x18, 1, 0xE0), 0x0000FC88, 0xff000003, /* link 0 of CPU 0 --> Nvidia MCP55 */</span><br><span style="color: hsl(120, 100%, 40%);">+ PCI_ADDR(0, 0x18, 1, 0xE4), 0x0000FC88, 0x00000000,</span><br><span style="color: hsl(120, 100%, 40%);">+ PCI_ADDR(0, 0x18, 1, 0xE8), 0x0000FC88, 0x00000000,</span><br><span style="color: hsl(120, 100%, 40%);">+ PCI_ADDR(0, 0x18, 1, 0xEC), 0x0000FC88, 0x00000000,</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ };</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ int max;</span><br><span style="color: hsl(120, 100%, 40%);">+ max = ARRAY_SIZE(register_values);</span><br><span style="color: hsl(120, 100%, 40%);">+ setup_resource_map(register_values, max);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span>diff --git a/src/mainboard/gigabyte/m57sli/romstage.c b/src/mainboard/gigabyte/m57sli/romstage.c</span><br><span>new file mode 100644</span><br><span>index 0000000..080697d</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/gigabyte/m57sli/romstage.c</span><br><span>@@ -0,0 +1,262 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2007 AMD</span><br><span style="color: hsl(120, 100%, 40%);">+ * Written by Yinghai Lu <yinghailu@amd.com> for AMD.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; either version 2 of the License, or</span><br><span style="color: hsl(120, 100%, 40%);">+ * (at your option) any later version.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <stdint.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <string.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <device/pci_def.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <device/pci_ids.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <arch/io.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <device/pnp_def.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <cpu/x86/lapic.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <pc80/mc146818rtc.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <console/console.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <timestamp.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <spd.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <cbmem.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <cpu/amd/model_10xxx_rev.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <southbridge/nvidia/mcp55/mcp55.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <northbridge/amd/amdfam10/raminit.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <delay.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <cpu/x86/lapic.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <superio/ite/common/ite.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <superio/ite/it8716f/it8716f.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <cpu/amd/car.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <cpu/x86/bist.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <northbridge/amd/amdht/ht_wrapper.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <cpu/amd/family_10h-family_15h/init_cpus.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include "resourcemap.c"</span><br><span style="color: hsl(120, 100%, 40%);">+#include "cpu/amd/quadcore/quadcore.c"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define SERIAL_DEV PNP_DEV(0x2e, IT8716F_SP1)</span><br><span style="color: hsl(120, 100%, 40%);">+#define CLKIN_DEV PNP_DEV(0x2e, IT8716F_GPIO)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+extern struct sys_info sysinfo_car;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+unsigned get_sbdn(unsigned bus)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_devfn_t dev;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Find the device. */</span><br><span style="color: hsl(120, 100%, 40%);">+ dev = pci_locate_device_on_bus(PCI_ID(PCI_VENDOR_ID_NVIDIA,</span><br><span style="color: hsl(120, 100%, 40%);">+ PCI_DEVICE_ID_NVIDIA_MCP55_HT), bus);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ return (dev >> 15) & 0x1f;</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+void activate_spd_rom(const struct mem_controller *ctrl);</span><br><span style="color: hsl(120, 100%, 40%);">+void activate_spd_rom(const struct mem_controller *ctrl) { }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+int spd_read_byte(unsigned device, unsigned address);</span><br><span style="color: hsl(120, 100%, 40%);">+int spd_read_byte(unsigned device, unsigned address)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ return smbus_read_byte(device, address);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define MCP55_MB_SETUP \</span><br><span style="color: hsl(120, 100%, 40%);">+ RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+37, 0x00, 0x68,/* GPIO38 PCI_REQ3 */ \</span><br><span style="color: hsl(120, 100%, 40%);">+ RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+38, 0x00, 0x68,/* GPIO39 PCI_GNT3 */ \</span><br><span style="color: hsl(120, 100%, 40%);">+ RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+39, 0x00, 0x68,/* GPIO40 PCI_GNT2 */ \</span><br><span style="color: hsl(120, 100%, 40%);">+ RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+40, 0x00, 0x68,/* GPIO41 PCI_REQ2 */ \</span><br><span style="color: hsl(120, 100%, 40%);">+ RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+59, 0x00, 0x60,/* GPIP60 FANCTL0 */ \</span><br><span style="color: hsl(120, 100%, 40%);">+ RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+60, 0x00, 0x60,/* GPIO61 FANCTL1 */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <southbridge/nvidia/mcp55/early_setup_ss.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include "southbridge/nvidia/mcp55/early_setup_car.c"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static void sio_setup(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t dword;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint8_t byte;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ byte = pci_read_config8(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0x7b);</span><br><span style="color: hsl(120, 100%, 40%);">+ byte |= 0x20;</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_write_config8(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0x7b, byte);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0);</span><br><span style="color: hsl(120, 100%, 40%);">+ dword |= (1 << 0);</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0, dword);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa4);</span><br><span style="color: hsl(120, 100%, 40%);">+ dword |= (1 << 16);</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa4, dword);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 val;</span><br><span style="color: hsl(120, 100%, 40%);">+ msr_t msr;</span><br><span style="color: hsl(120, 100%, 40%);">+ static const u8 spd_addr[] = {RC00, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, };</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ struct sys_info *sysinfo = &sysinfo_car;</span><br><span style="color: hsl(120, 100%, 40%);">+ int wants_reset = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+ unsigned bsp_apicid = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ sysinfo->ht_link_cfg.ht_speed_limit = 1000;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ timestamp_init(timestamp_get());</span><br><span style="color: hsl(120, 100%, 40%);">+ timestamp_add_now(TS_START_ROMSTAGE);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ if (!cpu_init_detectedx && boot_cpu()) {</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Nothing special needs to be done to find bus 0 */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Allow the HT devices to be found */</span><br><span style="color: hsl(120, 100%, 40%);">+ set_bsp_node_CHtExtNodeCfgEn();</span><br><span style="color: hsl(120, 100%, 40%);">+ enumerate_ht_chain();</span><br><span style="color: hsl(120, 100%, 40%);">+ sio_setup();</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ if (bist == 0)</span><br><span style="color: hsl(120, 100%, 40%);">+ bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#if 0</span><br><span style="color: hsl(120, 100%, 40%);">+ uint8_t tmp = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+ pnp_enter_ext_func_mode(SERIAL_DEV);</span><br><span style="color: hsl(120, 100%, 40%);">+ /* The following line will set CLKIN to 24 MHz, external */</span><br><span style="color: hsl(120, 100%, 40%);">+ pnp_write_config(SERIAL_DEV, IT8716F_CONFIG_REG_CLOCKSEL, 0x11);</span><br><span style="color: hsl(120, 100%, 40%);">+ tmp = pnp_read_config(SERIAL_DEV, IT8716F_CONFIG_REG_SWSUSP);</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Is serial flash enabled? Then enable writing to serial flash. */</span><br><span style="color: hsl(120, 100%, 40%);">+ if (tmp & 0x0e) {</span><br><span style="color: hsl(120, 100%, 40%);">+ pnp_write_config(SERIAL_DEV, IT8716F_CONFIG_REG_SWSUSP, tmp | 0x10);</span><br><span style="color: hsl(120, 100%, 40%);">+ pnp_set_logical_device(GPIO_DEV);</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Set Serial Flash interface to 0x0820 */</span><br><span style="color: hsl(120, 100%, 40%);">+ pnp_write_config(GPIO_DEV, 0x64, 0x08);</span><br><span style="color: hsl(120, 100%, 40%);">+ pnp_write_config(GPIO_DEV, 0x65, 0x20);</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ it8716f_enable_dev(SERIAL_DEV, CONFIG_TTYS0_BASE);</span><br><span style="color: hsl(120, 100%, 40%);">+ pnp_exit_ext_func_mode(SERIAL_DEV);</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+ ite_conf_clkin(CLKIN_DEV, ITE_UART_CLK_PREDIVIDE_24);</span><br><span style="color: hsl(120, 100%, 40%);">+ ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ console_init();</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Halt if there was a built in self test failure */</span><br><span style="color: hsl(120, 100%, 40%);">+ report_bist_failure(bist);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ val = cpuid_eax(1);</span><br><span style="color: hsl(120, 100%, 40%);">+ printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val);</span><br><span style="color: hsl(120, 100%, 40%);">+ printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1);</span><br><span style="color: hsl(120, 100%, 40%);">+ printk(BIOS_DEBUG, "bsp_apicid = %02x\n", bsp_apicid);</span><br><span style="color: hsl(120, 100%, 40%);">+ printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ update_microcode(val);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ cpuSetAMDMSR(0);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ amd_ht_init(sysinfo);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ finalize_node_setup(sysinfo);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Setup any mainboard PCI settings etc. */</span><br><span style="color: hsl(120, 100%, 40%);">+ setup_mb_resource_map();</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ wait_all_core0_started();</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ if (IS_ENABLED(CONFIG_LOGICAL_CPUS)) {</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Core0 on each node is configured. Now setup any additional cores. */</span><br><span style="color: hsl(120, 100%, 40%);">+ printk(BIOS_DEBUG, "start_other_cores()\n");</span><br><span style="color: hsl(120, 100%, 40%);">+ start_other_cores(bsp_apicid);</span><br><span style="color: hsl(120, 100%, 40%);">+ post_code(0x37);</span><br><span style="color: hsl(120, 100%, 40%);">+ wait_all_other_cores_started(bsp_apicid);</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ if (IS_ENABLED(CONFIG_SET_FIDVID)) {</span><br><span style="color: hsl(120, 100%, 40%);">+ msr = rdmsr(0xc0010071);</span><br><span style="color: hsl(120, 100%, 40%);">+ printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ post_code(0x39);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ if (!warm_reset_detect(0)) { // BSP is node 0</span><br><span style="color: hsl(120, 100%, 40%);">+ init_fidvid_bsp(bsp_apicid, sysinfo->nodes);</span><br><span style="color: hsl(120, 100%, 40%);">+ } else {</span><br><span style="color: hsl(120, 100%, 40%);">+ init_fidvid_stage2(bsp_apicid, 0); // BSP is node 0</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ post_code(0x3A);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* show final fid and vid */</span><br><span style="color: hsl(120, 100%, 40%);">+ msr = rdmsr(0xc0010071);</span><br><span style="color: hsl(120, 100%, 40%);">+ printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo);</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ init_timer(); // Need to use TMICT to synchronize FID/VID</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ wants_reset = mcp55_early_setup_x();</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Reset for HT, FIDVID, PLL and errata changes to take affect. */</span><br><span style="color: hsl(120, 100%, 40%);">+ if (!warm_reset_detect(0)) {</span><br><span style="color: hsl(120, 100%, 40%);">+ printk(BIOS_INFO, "...WARM RESET...\n\n\n");</span><br><span style="color: hsl(120, 100%, 40%);">+ soft_reset();</span><br><span style="color: hsl(120, 100%, 40%);">+ die("After soft_reset - shouldn't see this message!!!\n");</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ if (wants_reset)</span><br><span style="color: hsl(120, 100%, 40%);">+ printk(BIOS_DEBUG, "mcp55_early_setup_x wanted additional reset!\n");</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ //It's the time to set ctrl in sysinfo now;</span><br><span style="color: hsl(120, 100%, 40%);">+ printk(BIOS_DEBUG, "fill_mem_ctrl()\n");</span><br><span style="color: hsl(120, 100%, 40%);">+ fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ enable_smbus();</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* all ap stopped? */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ timestamp_add_now(TS_BEFORE_INITRAM);</span><br><span style="color: hsl(120, 100%, 40%);">+ printk(BIOS_DEBUG, "raminit_amdmct()\n");</span><br><span style="color: hsl(120, 100%, 40%);">+ raminit_amdmct(sysinfo);</span><br><span style="color: hsl(120, 100%, 40%);">+ timestamp_add_now(TS_AFTER_INITRAM);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ cbmem_initialize_empty();</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ amdmct_cbmem_store_info(sysinfo);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/**</span><br><span style="color: hsl(120, 100%, 40%);">+ * BOOL AMD_CB_ManualBUIDSwapList(u8 Node, u8 Link, u8 **List)</span><br><span style="color: hsl(120, 100%, 40%);">+ * Description:</span><br><span style="color: hsl(120, 100%, 40%);">+ * This routine is called every time a non-coherent chain is processed.</span><br><span style="color: hsl(120, 100%, 40%);">+ * BUID assignment may be controlled explicitly on a non-coherent chain. Provide a</span><br><span style="color: hsl(120, 100%, 40%);">+ * swap list. The first part of the list controls the BUID assignment and the</span><br><span style="color: hsl(120, 100%, 40%);">+ * second part of the list provides the device to device linking. Device orientation</span><br><span style="color: hsl(120, 100%, 40%);">+ * can be detected automatically, or explicitly. See documentation for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Automatic non-coherent init assigns BUIDs starting at 1 and incrementing sequentially</span><br><span style="color: hsl(120, 100%, 40%);">+ * based on each device's unit count.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Parameters:</span><br><span style="color: hsl(120, 100%, 40%);">+ * @param[in] node = The node on which this chain is located</span><br><span style="color: hsl(120, 100%, 40%);">+ * @param[in] link = The link on the host for this chain</span><br><span style="color: hsl(120, 100%, 40%);">+ * @param[out] List = supply a pointer to a list</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+BOOL AMD_CB_ManualBUIDSwapList (u8 node, u8 link, const u8 **List)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ static const u8 swaplist[] = { 0xFF, CONFIG_HT_CHAIN_UNITID_BASE, CONFIG_HT_CHAIN_END_UNITID_BASE, 0xFF };</span><br><span style="color: hsl(120, 100%, 40%);">+ /* If the BUID was adjusted in early_ht we need to do the manual override */</span><br><span style="color: hsl(120, 100%, 40%);">+ if ((CONFIG_HT_CHAIN_UNITID_BASE != 0) && (CONFIG_HT_CHAIN_END_UNITID_BASE != 0)) {</span><br><span style="color: hsl(120, 100%, 40%);">+ printk(BIOS_DEBUG, "AMD_CB_ManualBUIDSwapList()\n");</span><br><span style="color: hsl(120, 100%, 40%);">+ if ((node == 0) && (link == 0)) { /* BSP SB link */</span><br><span style="color: hsl(120, 100%, 40%);">+ *List = swaplist;</span><br><span style="color: hsl(120, 100%, 40%);">+ return 1;</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ return 0;</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span>diff --git a/src/mainboard/gigabyte/ma78gm/romstage.c b/src/mainboard/gigabyte/ma78gm/romstage.c</span><br><span>index 9f4dd44..0c67516 100644</span><br><span>--- a/src/mainboard/gigabyte/ma78gm/romstage.c</span><br><span>+++ b/src/mainboard/gigabyte/ma78gm/romstage.c</span><br><span>@@ -238,15 +238,5 @@</span><br><span> */</span><br><span> BOOL AMD_CB_ManualBUIDSwapList (u8 node, u8 link, const u8 **List)</span><br><span> {</span><br><span style="color: hsl(0, 100%, 40%);">- static const u8 swaplist[] = { 0xFF, CONFIG_HT_CHAIN_UNITID_BASE, CONFIG_HT_CHAIN_END_UNITID_BASE, 0xFF };</span><br><span style="color: hsl(0, 100%, 40%);">- /* If the BUID was adjusted in early_ht we need to do the manual override */</span><br><span style="color: hsl(0, 100%, 40%);">- if ((CONFIG_HT_CHAIN_UNITID_BASE != 0) && (CONFIG_HT_CHAIN_END_UNITID_BASE != 0)) {</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, "AMD_CB_ManualBUIDSwapList()\n");</span><br><span style="color: hsl(0, 100%, 40%);">- if ((node == 0) && (link == 0)) { /* BSP SB link */</span><br><span style="color: hsl(0, 100%, 40%);">- *List = swaplist;</span><br><span style="color: hsl(0, 100%, 40%);">- return 1;</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span> return 0;</span><br><span> }</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/27618">change 27618</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/27618"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I20a437f6952d9f919ad186d4862ca00853d9ebca </div>
<div style="display:none"> Gerrit-Change-Number: 27618 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Arthur Heymans <arthur@aheymans.xyz> </div>