<p>Charles Marslett would like Charles Marslett to <strong>review</strong> this change.</p><p><a href="https://review.coreboot.org/27619">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">Add header file: psp.h, and modify code in psp.c to use internal functions<br>rather than functions from PspBaseLib.<br><br>Change-Id: I2740ceb945736c6e413f7d0bd0c41a19e19c7d5a<br>Signed-off-by: Charles Marslett <charles.marslett@silverbackltd.com><br>---<br>M src/soc/amd/common/block/psp/psp.c<br>A src/soc/amd/common/block/psp/psp.h<br>2 files changed, 175 insertions(+), 13 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/27619/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/soc/amd/common/block/psp/psp.c b/src/soc/amd/common/block/psp/psp.c</span><br><span>index a1a0e5b..dbb0267 100644</span><br><span>--- a/src/soc/amd/common/block/psp/psp.c</span><br><span>+++ b/src/soc/amd/common/block/psp/psp.c</span><br><span>@@ -9,7 +9,7 @@</span><br><span> *</span><br><span> * This program is distributed in the hope that it will be useful,</span><br><span> * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(0, 100%, 40%);">- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span> * GNU General Public License for more details.</span><br><span> */</span><br><span> </span><br><span>@@ -20,7 +20,11 @@</span><br><span> #include <device/pci_def.h></span><br><span> #include <bootstate.h></span><br><span> #include <console/console.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <device/pci_ops.h></span><br><span> #include <amdblocks/psp.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/iomap.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include "psp.h"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> </span><br><span> static const char *psp_status_nobase = "error: PSP BAR3 not assigned";</span><br><span> static const char *psp_status_halted = "error: PSP in halted state";</span><br><span>@@ -30,6 +34,124 @@</span><br><span> static const char *psp_status_cmd_timeout = "error: PSP command timeout";</span><br><span> static const char *psp_status_noerror = "";</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+static BOOLEAN psp_bar_init_early(VOID);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/**</span><br><span style="color: hsl(120, 100%, 40%);">+ Attempt to perform a very early initialization of the PSP device</span><br><span style="color: hsl(120, 100%, 40%);">+ BAR3 register.</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ @retval BOOLEAN 0: Error, 1 Success</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+static BOOLEAN</span><br><span style="color: hsl(120, 100%, 40%);">+psp_bar_init_early(VOID)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 PspMmioSize;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 Value32;</span><br><span style="color: hsl(120, 100%, 40%);">+ PCI_ADDR PciAddr;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ printk(BIOS_DEBUG, "PSP: %s() called...\n", __func__);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ Value32 = pci_read_config32(SOC_PSP_DEV, PSP_PCI_DEVID_REG);</span><br><span style="color: hsl(120, 100%, 40%);">+ if (Value32 == 0xffffffff) {</span><br><span style="color: hsl(120, 100%, 40%);">+ printk(BIOS_DEBUG, "PSP: No device at PSP Seg/Bus/Dev/FUNC...\n");</span><br><span style="color: hsl(120, 100%, 40%);">+ return FALSE;</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ // Check if PSP BAR has been assigned,</span><br><span style="color: hsl(120, 100%, 40%);">+ // if not do the PSP BAR initialization</span><br><span style="color: hsl(120, 100%, 40%);">+ Value32 = pci_read_config32(SOC_PSP_DEV, PSP_PCI_BAR3_REG);</span><br><span style="color: hsl(120, 100%, 40%);">+ if ((Value32 & ~0x0F) == 0) {</span><br><span style="color: hsl(120, 100%, 40%);">+ printk(BIOS_DEBUG, "PSP: BAR3 value is zero...\n");</span><br><span style="color: hsl(120, 100%, 40%);">+ /// Get PSP BAR3 Size</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_write_config32(SOC_PSP_DEV, PSP_PCI_BAR3_REG,</span><br><span style="color: hsl(120, 100%, 40%);">+ (u32)0xFFFFFFFF);</span><br><span style="color: hsl(120, 100%, 40%);">+ PspMmioSize = ~pci_read_config32(SOC_PSP_DEV, PSP_PCI_BAR3_REG)</span><br><span style="color: hsl(120, 100%, 40%);">+ + 1;</span><br><span style="color: hsl(120, 100%, 40%);">+ printk(BIOS_DEBUG, "PSP: BAR3 size is 0x%x...\n", PspMmioSize);</span><br><span style="color: hsl(120, 100%, 40%);">+ /// Assign BAR3 Temporary Address</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_write_config32(SOC_PSP_DEV, PSP_PCI_BAR3_REG,</span><br><span style="color: hsl(120, 100%, 40%);">+ PSP_MAILBOX_BAR3_BASE);</span><br><span style="color: hsl(120, 100%, 40%);">+ /// Enable Access</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_write_config32(SOC_PSP_DEV, PSP_PCI_CMD_REG, 0x06);</span><br><span style="color: hsl(120, 100%, 40%);">+ printk(BIOS_DEBUG, "PSP: BAR3 set to 0x%x, CMD=0x%x zero...\n",</span><br><span style="color: hsl(120, 100%, 40%);">+ (unsigned int)pci_read_config32(SOC_PSP_DEV,</span><br><span style="color: hsl(120, 100%, 40%);">+ PSP_PCI_BAR3_REG),</span><br><span style="color: hsl(120, 100%, 40%);">+ (unsigned int)pci_read_config32(SOC_PSP_DEV,</span><br><span style="color: hsl(120, 100%, 40%);">+ PSP_PCI_CMD_REG));</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /// Enable GNB redirection to this space</span><br><span style="color: hsl(120, 100%, 40%);">+ /// @todo use equate & also find proper fix</span><br><span style="color: hsl(120, 100%, 40%);">+ PciAddr.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0xBC);</span><br><span style="color: hsl(120, 100%, 40%);">+ Value32 = ((PSP_MAILBOX_BAR3_BASE + PspMmioSize - 1) >> 8)</span><br><span style="color: hsl(120, 100%, 40%);">+ & ~0xFF;</span><br><span style="color: hsl(120, 100%, 40%);">+ LibAmdPciWrite(AccessWidth32, PciAddr, &Value32, NULL);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ PciAddr.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0xB8);</span><br><span style="color: hsl(120, 100%, 40%);">+ Value32 = (PSP_MAILBOX_BAR3_BASE >> 8) | 3;</span><br><span style="color: hsl(120, 100%, 40%);">+ LibAmdPciWrite(AccessWidth32, PciAddr, &Value32, NULL);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /// Enable MsixBarEn, Bar1En, Bar3En</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_write_config32(SOC_PSP_DEV, PSP_PCI_EXTRAPCIHDR_REG,</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x34);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /// Capability chain update</span><br><span style="color: hsl(120, 100%, 40%);">+ Value32 = pci_read_config32(SOC_PSP_DEV,</span><br><span style="color: hsl(120, 100%, 40%);">+ PSP_PCI_MIRRORCTRL1_REG);</span><br><span style="color: hsl(120, 100%, 40%);">+ Value32 &= ~D8F0x44_PmNxtPtrW_MASK;</span><br><span style="color: hsl(120, 100%, 40%);">+ Value32 |= 0xA4;</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_write_config32(SOC_PSP_DEV, PSP_PCI_MIRRORCTRL1_REG,</span><br><span style="color: hsl(120, 100%, 40%);">+ Value32);</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ return TRUE;</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/**</span><br><span style="color: hsl(120, 100%, 40%);">+ Return the PspMMIO MMIO location</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ @param[in] PspMmio Pointer to Psp MMIO address</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ @retval BOOLEAN 0: Error, 1 Success</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+static BOOLEAN</span><br><span style="color: hsl(120, 100%, 40%);">+get_psp_bar3_addr(</span><br><span style="color: hsl(120, 100%, 40%);">+ IN OUT u32 *PspMmio</span><br><span style="color: hsl(120, 100%, 40%);">+ )</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 Value;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_write_config32(SOC_PSP_DEV, PCI_CONFIG_SMU_INDIRECT_INDEX,</span><br><span style="color: hsl(120, 100%, 40%);">+ SMU_CC_PSP_FUSES_STATUS);</span><br><span style="color: hsl(120, 100%, 40%);">+ Value = pci_read_config32(SOC_PSP_DEV, PCI_CONFIG_SMU_INDIRECT_DATA);</span><br><span style="color: hsl(120, 100%, 40%);">+ if ((Value & SMU_CC_PSP_FUSES_PROTO) != 0) {</span><br><span style="color: hsl(120, 100%, 40%);">+ printk(BIOS_DEBUG, "PSP: %s(): SMU_CC_PSP_FUSES_PROTO = 0 - FALSE...\n",</span><br><span style="color: hsl(120, 100%, 40%);">+ __func__);</span><br><span style="color: hsl(120, 100%, 40%);">+ return FALSE;</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ // D8F0x48[12] Bar3Hide</span><br><span style="color: hsl(120, 100%, 40%);">+ if (pci_read_config32(SOC_PSP_DEV, PSP_PCI_EXTRAPCIHDR_REG) & BIT12) {</span><br><span style="color: hsl(120, 100%, 40%);">+ printk(BIOS_DEBUG, "PSP: %s(): D8F0x48[12]/Bar3Hidden...\n",</span><br><span style="color: hsl(120, 100%, 40%);">+ __func__);</span><br><span style="color: hsl(120, 100%, 40%);">+ *PspMmio = (u32)__readmsr(MSR_CU_CBBCFG)) == 0xFFFFFFFF;</span><br><span style="color: hsl(120, 100%, 40%);">+ if (*PspMmio) {</span><br><span style="color: hsl(120, 100%, 40%);">+ printk(BIOS_DEBUG, "PSP: %s(): Msr PspMmio = 0xFFFFFFFF - FALSE...\n",</span><br><span style="color: hsl(120, 100%, 40%);">+ __func__);</span><br><span style="color: hsl(120, 100%, 40%);">+ return FALSE;</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ printk(BIOS_DEBUG, "PSP: %s(): BAR3 = 0x%x ...\n",</span><br><span style="color: hsl(120, 100%, 40%);">+ __func__, *PspMmio);</span><br><span style="color: hsl(120, 100%, 40%);">+ } else {</span><br><span style="color: hsl(120, 100%, 40%);">+ *PspMmio = pci_read_config32(SOC_PSP_DEV, PSP_PCI_BAR3_REG) &</span><br><span style="color: hsl(120, 100%, 40%);">+ 0xFFF00000;</span><br><span style="color: hsl(120, 100%, 40%);">+ printk(BIOS_DEBUG, "PSP: %s(): Read BAR3 = 0x%x ...\n",</span><br><span style="color: hsl(120, 100%, 40%);">+ __func__, *PspMmio);</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ return TRUE;</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> static const char *status_to_string(int err)</span><br><span> {</span><br><span> switch (err) {</span><br><span>@@ -52,20 +174,25 @@</span><br><span> </span><br><span> static struct psp_mbox *get_mbox_address(void)</span><br><span> {</span><br><span style="color: hsl(0, 100%, 40%);">- UINT32 base; /* UINT32 for compatibility with PspBaseLib */</span><br><span style="color: hsl(0, 100%, 40%);">- BOOLEAN bar3_status;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 base; /* u32 for compatibility with PspBaseLib */</span><br><span> uintptr_t baseptr;</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- bar3_status = GetPspBar3Addr(&base);</span><br><span style="color: hsl(0, 100%, 40%);">- if (!bar3_status) {</span><br><span style="color: hsl(0, 100%, 40%);">- PspBarInitEarly();</span><br><span style="color: hsl(0, 100%, 40%);">- bar3_status = GetPspBar3Addr(&base);</span><br><span style="color: hsl(120, 100%, 40%);">+ if (!get_psp_bar3_addr(&base)) {</span><br><span style="color: hsl(120, 100%, 40%);">+ printk(BIOS_DEBUG,</span><br><span style="color: hsl(120, 100%, 40%);">+ "PSP: %s(), get_psp_bar3_addr() returned FALSE, base=0x%x...\n",</span><br><span style="color: hsl(120, 100%, 40%);">+ __func__, base);</span><br><span style="color: hsl(120, 100%, 40%);">+ psp_bar_init_early();</span><br><span style="color: hsl(120, 100%, 40%);">+ if (!get_psp_bar3_addr(&base)) {</span><br><span style="color: hsl(120, 100%, 40%);">+ printk(BIOS_DEBUG,</span><br><span style="color: hsl(120, 100%, 40%);">+ "PSP: %s(), get_psp_bar3_addr returned FALSE, base=0x%x...\n",</span><br><span style="color: hsl(120, 100%, 40%);">+ __func__, base);</span><br><span style="color: hsl(120, 100%, 40%);">+ return NULL;</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span> }</span><br><span style="color: hsl(0, 100%, 40%);">- if (!bar3_status)</span><br><span style="color: hsl(0, 100%, 40%);">- return NULL;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- baseptr = base;</span><br><span style="color: hsl(0, 100%, 40%);">- return (struct psp_mbox *)(baseptr + PSP_MAILBOX_BASE);</span><br><span style="color: hsl(120, 100%, 40%);">+ baseptr = (uintptr_t)base + PSP_MAILBOX_BASE;</span><br><span style="color: hsl(120, 100%, 40%);">+ printk(BIOS_DEBUG, "PSP: %s() = 0x%p...\n",</span><br><span style="color: hsl(120, 100%, 40%);">+ __func__, (struct psp_mbox *)baseptr);</span><br><span style="color: hsl(120, 100%, 40%);">+ return ((struct psp_mbox *)baseptr);</span><br><span> }</span><br><span> </span><br><span> static u32 rd_mbox_sts(struct psp_mbox *mbox)</span><br><span>@@ -157,7 +284,7 @@</span><br><span> }</span><br><span> </span><br><span> /*</span><br><span style="color: hsl(0, 100%, 40%);">- * Notify the PSP that DRAM is present. Upon receiving this command, the PSP</span><br><span style="color: hsl(120, 100%, 40%);">+ * Notify the PSP that DRAM is present. Upon receiving this command, the PSP</span><br><span> * will load its OS into fenced DRAM that is not accessible to the x86 cores.</span><br><span> */</span><br><span> int psp_notify_dram(void)</span><br><span>diff --git a/src/soc/amd/common/block/psp/psp.h b/src/soc/amd/common/block/psp/psp.h</span><br><span>new file mode 100644</span><br><span>index 0000000..dd6159b</span><br><span>--- /dev/null</span><br><span>+++ b/src/soc/amd/common/block/psp/psp.h</span><br><span>@@ -0,0 +1,35 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2017 Advanced Micro Devices, Inc.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// Registers in the PSP PCI Config Space</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define PSP_PCI_DEVID_REG 0x00 ///< Standard Pci Device ID</span><br><span style="color: hsl(120, 100%, 40%);">+#define PSP_PCI_CMD_REG 0x04 ///< CmdReg</span><br><span style="color: hsl(120, 100%, 40%);">+#define PSP_PCI_BAR3_REG 0x20 ///< Pci Bar3</span><br><span style="color: hsl(120, 100%, 40%);">+#define PSP_PCI_MIRRORCTRL1_REG 0x44 ///< PSP Mirror Reg Ctrl</span><br><span style="color: hsl(120, 100%, 40%);">+#define PSP_PCI_EXTRAPCIHDR_REG 0x48 ///< Extra PCI Header Ctr</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCI_CONFIG_SMU_INDIRECT_INDEX 0xB8 ///< Gnb index for SMU mbox</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCI_CONFIG_SMU_INDIRECT_DATA 0xBC ///< Gnb data for SMU mbox</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// GNB related offsets and bit specifications</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define SMU_CC_PSP_FUSES_STATUS 0xC0018000ul ///< GNB offset to find PSP fusing</span><br><span style="color: hsl(120, 100%, 40%);">+#define SMU_CC_PSP_FUSES_PROTO BIT2 ///< BIT2</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// PSP Mailbox definitions</span><br><span style="color: hsl(120, 100%, 40%);">+#define PSP_MAILBOX_BASE 0x70 ///< Mailbox offset from PCIe BAR</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define MSR_CU_CBBCFG 0xC00110A2ul ///< PSP Private Blk Base Addr</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/27619">change 27619</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/27619"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I2740ceb945736c6e413f7d0bd0c41a19e19c7d5a </div>
<div style="display:none"> Gerrit-Change-Number: 27619 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Charles Marslett <charles.marslett@amd.corp-partner.google.com> </div>
<div style="display:none"> Gerrit-Reviewer: Charles Marslett <charles.marslett@silverbackltd.com> </div>