<p><a href="https://review.coreboot.org/15164">View Change</a></p><p>102 comments:</p><ul style="list-style: none; padding: 0;"><li style="margin: 0; padding: 0;"><p><a href="https://review.coreboot.org/#/c/15164/16/src/northbridge/amd/pi/00730F01/northbridge.c">File src/northbridge/amd/pi/00730F01/northbridge.c:</a></p><ul style="list-style: none; padding: 0;"><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/15164/16/src/northbridge/amd/pi/00730F01/northbridge.c@441">Patch Set #16, Line 441:</a> <code style="font-family:monospace,monospace">static void add_ivrs_device_entries(struct device *parent, struct device *dev, int depth, int linknum, int8_t *root_level, unsigned long *current, uint16_t *length)</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/15164/16/src/northbridge/amd/pi/00730F01/northbridge.c@453">Patch Set #16, Line 453:</a> <code style="font-family:monospace,monospace"> if ((dev->bus->secondary == 0x0) && (dev->path.pci.devfn == 0x0))</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/15164/16/src/northbridge/amd/pi/00730F01/northbridge.c@460">Patch Set #16, Line 460:</a> <code style="font-family:monospace,monospace"> if (dev->path.pci.devfn == 0x2) {</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/15164/16/src/northbridge/amd/pi/00730F01/northbridge.c@460">Patch Set #16, Line 460:</a> <code style="font-family:monospace,monospace"> if (dev->path.pci.devfn == 0x2) {</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">Too many leading tabs - consider code refactoring</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/15164/16/src/northbridge/amd/pi/00730F01/northbridge.c@462">Patch Set #16, Line 462:</a> <code style="font-family:monospace,monospace"> p = (uint8_t *) *current;</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/15164/16/src/northbridge/amd/pi/00730F01/northbridge.c@463">Patch Set #16, Line 463:</a> <code style="font-family:monospace,monospace"> p[0] = 0x2; /* Entry type */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/15164/16/src/northbridge/amd/pi/00730F01/northbridge.c@464">Patch Set #16, Line 464:</a> <code style="font-family:monospace,monospace"> p[1] = dev->path.pci.devfn; /* Device */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/15164/16/src/northbridge/amd/pi/00730F01/northbridge.c@465">Patch Set #16, Line 465:</a> <code style="font-family:monospace,monospace"> p[2] = dev->bus->secondary; /* Bus */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/15164/16/src/northbridge/amd/pi/00730F01/northbridge.c@466">Patch Set #16, Line 466:</a> <code style="font-family:monospace,monospace"> p[3] = 0x0; /* Data */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/15164/16/src/northbridge/amd/pi/00730F01/northbridge.c@467">Patch Set #16, Line 467:</a> <code style="font-family:monospace,monospace"> p[4] = 0x0; /* Padding */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/15164/16/src/northbridge/amd/pi/00730F01/northbridge.c@468">Patch Set #16, Line 468:</a> <code style="font-family:monospace,monospace"> p[5] = 0x0; /* Padding */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/15164/16/src/northbridge/amd/pi/00730F01/northbridge.c@469">Patch Set #16, Line 469:</a> <code style="font-family:monospace,monospace"> p[6] = 0x0; /* Padding */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/15164/16/src/northbridge/amd/pi/00730F01/northbridge.c@470">Patch Set #16, Line 470:</a> <code style="font-family:monospace,monospace"> p[7] = 0x0; /* Padding */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/15164/16/src/northbridge/amd/pi/00730F01/northbridge.c@473">Patch Set #16, Line 473:</a> <code style="font-family:monospace,monospace"> } else if (dev->path.pci.devfn < (0x2 << 3)) {</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/15164/16/src/northbridge/amd/pi/00730F01/northbridge.c@473">Patch Set #16, Line 473:</a> <code style="font-family:monospace,monospace"> } else if (dev->path.pci.devfn < (0x2 << 3)) {</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">Too many leading tabs - consider code refactoring</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/15164/16/src/northbridge/amd/pi/00730F01/northbridge.c@475">Patch Set #16, Line 475:</a> <code style="font-family:monospace,monospace"> } else if ((dev->path.pci.devfn >= (0x2 << 3)) && (dev->path.pci.devfn < (0x3 << 3))) {</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/15164/16/src/northbridge/amd/pi/00730F01/northbridge.c@475">Patch Set #16, Line 475:</a> <code style="font-family:monospace,monospace"> } else if ((dev->path.pci.devfn >= (0x2 << 3)) && (dev->path.pci.devfn < (0x3 << 3))) {</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">Too many leading tabs - consider code refactoring</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/15164/16/src/northbridge/amd/pi/00730F01/northbridge.c@476">Patch Set #16, Line 476:</a> <code style="font-family:monospace,monospace"> /* FCH PCIe bridge device */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/15164/16/src/northbridge/amd/pi/00730F01/northbridge.c@477">Patch Set #16, Line 477:</a> <code style="font-family:monospace,monospace"> p = (uint8_t *) *current;</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/15164/16/src/northbridge/amd/pi/00730F01/northbridge.c@478">Patch Set #16, Line 478:</a> <code style="font-family:monospace,monospace"> p[0] = 0x2; /* Entry type */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/15164/16/src/northbridge/amd/pi/00730F01/northbridge.c@479">Patch Set #16, Line 479:</a> <code style="font-family:monospace,monospace"> p[1] = dev->path.pci.devfn; /* Device */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/15164/16/src/northbridge/amd/pi/00730F01/northbridge.c@480">Patch Set #16, Line 480:</a> <code style="font-family:monospace,monospace"> p[2] = dev->bus->secondary; /* Bus */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/15164/16/src/northbridge/amd/pi/00730F01/northbridge.c@481">Patch Set #16, Line 481:</a> <code style="font-family:monospace,monospace"> p[3] = 0x0; /* Data */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/15164/16/src/northbridge/amd/pi/00730F01/northbridge.c@482">Patch Set #16, Line 482:</a> <code style="font-family:monospace,monospace"> p[4] = 0x0; /* Padding */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/15164/16/src/northbridge/amd/pi/00730F01/northbridge.c@483">Patch Set #16, Line 483:</a> <code style="font-family:monospace,monospace"> p[5] = 0x0; /* Padding */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/15164/16/src/northbridge/amd/pi/00730F01/northbridge.c@484">Patch Set #16, Line 484:</a> <code style="font-family:monospace,monospace"> p[6] = 0x0; /* Padding */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/15164/16/src/northbridge/amd/pi/00730F01/northbridge.c@485">Patch Set #16, Line 485:</a> <code style="font-family:monospace,monospace"> p[7] = 0x0; /* Padding */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/15164/16/src/northbridge/amd/pi/00730F01/northbridge.c@488">Patch Set #16, Line 488:</a> <code style="font-family:monospace,monospace"> } else {</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">Too many leading tabs - consider code refactoring</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/15164/16/src/northbridge/amd/pi/00730F01/northbridge.c@489">Patch Set #16, Line 489:</a> <code style="font-family:monospace,monospace"> if (dev->path.pci.devfn == (0x14 << 3)) {</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/15164/16/src/northbridge/amd/pi/00730F01/northbridge.c@489">Patch Set #16, Line 489:</a> <code style="font-family:monospace,monospace"> if (dev->path.pci.devfn == (0x14 << 3)) {</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">Too many leading tabs - consider code refactoring</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/15164/16/src/northbridge/amd/pi/00730F01/northbridge.c@490">Patch Set #16, Line 490:</a> <code style="font-family:monospace,monospace"> /* SMBUS controller */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/15164/16/src/northbridge/amd/pi/00730F01/northbridge.c@491">Patch Set #16, Line 491:</a> <code style="font-family:monospace,monospace"> p = (uint8_t *) *current;</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/15164/16/src/northbridge/amd/pi/00730F01/northbridge.c@492">Patch Set #16, Line 492:</a> <code style="font-family:monospace,monospace"> p[0] = 0x2; /* Entry type */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/15164/16/src/northbridge/amd/pi/00730F01/northbridge.c@493">Patch Set #16, Line 493:</a> <code style="font-family:monospace,monospace"> p[1] = dev->path.pci.devfn; /* Device */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/15164/16/src/northbridge/amd/pi/00730F01/northbridge.c@494">Patch Set #16, Line 494:</a> <code style="font-family:monospace,monospace"> p[2] = dev->bus->secondary; /* Bus */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/15164/16/src/northbridge/amd/pi/00730F01/northbridge.c@495">Patch Set #16, Line 495:</a> <code style="font-family:monospace,monospace"> p[3] = 0x97; /* Data */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/15164/16/src/northbridge/amd/pi/00730F01/northbridge.c@496">Patch Set #16, Line 496:</a> <code style="font-family:monospace,monospace"> p[4] = 0x0; /* Padding */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/15164/16/src/northbridge/amd/pi/00730F01/northbridge.c@497">Patch Set #16, Line 497:</a> <code style="font-family:monospace,monospace"> p[5] = 0x0; /* Padding */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/15164/16/src/northbridge/amd/pi/00730F01/northbridge.c@498">Patch Set #16, Line 498:</a> <code style="font-family:monospace,monospace"> p[6] = 0x0; /* Padding */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/15164/16/src/northbridge/amd/pi/00730F01/northbridge.c@499">Patch Set #16, Line 499:</a> <code style="font-family:monospace,monospace"> p[7] = 0x0; /* Padding */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/15164/16/src/northbridge/amd/pi/00730F01/northbridge.c@502">Patch Set #16, Line 502:</a> <code style="font-family:monospace,monospace"> } else {</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">Too many leading tabs - consider code refactoring</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/15164/16/src/northbridge/amd/pi/00730F01/northbridge.c@503">Patch Set #16, Line 503:</a> <code style="font-family:monospace,monospace"> /* Other southbridge device */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/15164/16/src/northbridge/amd/pi/00730F01/northbridge.c@504">Patch Set #16, Line 504:</a> <code style="font-family:monospace,monospace"> p = (uint8_t *) *current;</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/15164/16/src/northbridge/amd/pi/00730F01/northbridge.c@505">Patch Set #16, Line 505:</a> <code style="font-family:monospace,monospace"> p[0] = 0x2; /* Entry type */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/15164/16/src/northbridge/amd/pi/00730F01/northbridge.c@506">Patch Set #16, Line 506:</a> <code style="font-family:monospace,monospace"> p[1] = dev->path.pci.devfn; /* Device */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/15164/16/src/northbridge/amd/pi/00730F01/northbridge.c@507">Patch Set #16, Line 507:</a> <code style="font-family:monospace,monospace"> p[2] = dev->bus->secondary; /* Bus */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/15164/16/src/northbridge/amd/pi/00730F01/northbridge.c@508">Patch Set #16, Line 508:</a> <code style="font-family:monospace,monospace"> p[3] = 0x0; /* Data */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/15164/16/src/northbridge/amd/pi/00730F01/northbridge.c@509">Patch Set #16, Line 509:</a> <code style="font-family:monospace,monospace"> p[4] = 0x0; /* Padding */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/15164/16/src/northbridge/amd/pi/00730F01/northbridge.c@510">Patch Set #16, Line 510:</a> <code style="font-family:monospace,monospace"> p[5] = 0x0; /* Padding */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/15164/16/src/northbridge/amd/pi/00730F01/northbridge.c@511">Patch Set #16, Line 511:</a> <code style="font-family:monospace,monospace"> p[6] = 0x0; /* Padding */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/15164/16/src/northbridge/amd/pi/00730F01/northbridge.c@512">Patch Set #16, Line 512:</a> <code style="font-family:monospace,monospace"> p[7] = 0x0; /* Padding */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/15164/16/src/northbridge/amd/pi/00730F01/northbridge.c@518">Patch Set #16, Line 518:</a> <code style="font-family:monospace,monospace"> if ((dev->hdr_type & 0x7f) == PCI_HEADER_TYPE_NORMAL) {</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/15164/16/src/northbridge/amd/pi/00730F01/northbridge.c@518">Patch Set #16, Line 518:</a> <code style="font-family:monospace,monospace"> if ((dev->hdr_type & 0x7f) == PCI_HEADER_TYPE_NORMAL) {</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">Too many leading tabs - consider code refactoring</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/15164/16/src/northbridge/amd/pi/00730F01/northbridge.c@519">Patch Set #16, Line 519:</a> <code style="font-family:monospace,monospace"> /* Device behind bridge */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/15164/16/src/northbridge/amd/pi/00730F01/northbridge.c@520">Patch Set #16, Line 520:</a> <code style="font-family:monospace,monospace"> if (pci_find_capability(dev, PCI_CAP_ID_PCIE)) {</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/15164/16/src/northbridge/amd/pi/00730F01/northbridge.c@520">Patch Set #16, Line 520:</a> <code style="font-family:monospace,monospace"> if (pci_find_capability(dev, PCI_CAP_ID_PCIE)) {</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">Too many leading tabs - consider code refactoring</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/15164/16/src/northbridge/amd/pi/00730F01/northbridge.c@521">Patch Set #16, Line 521:</a> <code style="font-family:monospace,monospace"> /* Device is PCIe */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/15164/16/src/northbridge/amd/pi/00730F01/northbridge.c@522">Patch Set #16, Line 522:</a> <code style="font-family:monospace,monospace"> p = (uint8_t *) *current;</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/15164/16/src/northbridge/amd/pi/00730F01/northbridge.c@523">Patch Set #16, Line 523:</a> <code style="font-family:monospace,monospace"> p[0] = 0x2; /* Entry type */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/15164/16/src/northbridge/amd/pi/00730F01/northbridge.c@524">Patch Set #16, Line 524:</a> <code style="font-family:monospace,monospace"> p[1] = dev->path.pci.devfn; /* Device */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/15164/16/src/northbridge/amd/pi/00730F01/northbridge.c@525">Patch Set #16, Line 525:</a> <code style="font-family:monospace,monospace"> p[2] = dev->bus->secondary; /* Bus */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/15164/16/src/northbridge/amd/pi/00730F01/northbridge.c@526">Patch Set #16, Line 526:</a> <code style="font-family:monospace,monospace"> p[3] = 0x0; /* Data */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/15164/16/src/northbridge/amd/pi/00730F01/northbridge.c@527">Patch Set #16, Line 527:</a> <code style="font-family:monospace,monospace"> p[4] = 0x0; /* Padding */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/15164/16/src/northbridge/amd/pi/00730F01/northbridge.c@528">Patch Set #16, Line 528:</a> <code style="font-family:monospace,monospace"> p[5] = 0x0; /* Padding */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/15164/16/src/northbridge/amd/pi/00730F01/northbridge.c@529">Patch Set #16, Line 529:</a> <code style="font-family:monospace,monospace"> p[6] = 0x0; /* Padding */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/15164/16/src/northbridge/amd/pi/00730F01/northbridge.c@530">Patch Set #16, Line 530:</a> <code style="font-family:monospace,monospace"> p[7] = 0x0; /* Padding */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/15164/16/src/northbridge/amd/pi/00730F01/northbridge.c@533">Patch Set #16, Line 533:</a> <code style="font-family:monospace,monospace"> } else {</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">Too many leading tabs - consider code refactoring</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/15164/16/src/northbridge/amd/pi/00730F01/northbridge.c@534">Patch Set #16, Line 534:</a> <code style="font-family:monospace,monospace"> /* Device is legacy PCI or PCI-X */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/15164/16/src/northbridge/amd/pi/00730F01/northbridge.c@535">Patch Set #16, Line 535:</a> <code style="font-family:monospace,monospace"> p = (uint8_t *) *current;</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/15164/16/src/northbridge/amd/pi/00730F01/northbridge.c@536">Patch Set #16, Line 536:</a> <code style="font-family:monospace,monospace"> p[0] = 0x42; /* Entry type */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/15164/16/src/northbridge/amd/pi/00730F01/northbridge.c@537">Patch Set #16, Line 537:</a> <code style="font-family:monospace,monospace"> p[1] = dev->path.pci.devfn; /* Device */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/15164/16/src/northbridge/amd/pi/00730F01/northbridge.c@538">Patch Set #16, Line 538:</a> <code style="font-family:monospace,monospace"> p[2] = dev->bus->secondary; /* Bus */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/15164/16/src/northbridge/amd/pi/00730F01/northbridge.c@539">Patch Set #16, Line 539:</a> <code style="font-family:monospace,monospace"> p[3] = 0x0; /* Data */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/15164/16/src/northbridge/amd/pi/00730F01/northbridge.c@540">Patch Set #16, Line 540:</a> <code style="font-family:monospace,monospace"> p[4] = 0x0; /* Reserved */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/15164/16/src/northbridge/amd/pi/00730F01/northbridge.c@541">Patch Set #16, Line 541:</a> <code style="font-family:monospace,monospace"> p[5] = parent->path.pci.devfn; /* Device */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/15164/16/src/northbridge/amd/pi/00730F01/northbridge.c@542">Patch Set #16, Line 542:</a> <code style="font-family:monospace,monospace"> p[6] = parent->bus->secondary; /* Bus */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/15164/16/src/northbridge/amd/pi/00730F01/northbridge.c@543">Patch Set #16, Line 543:</a> <code style="font-family:monospace,monospace"> p[7] = 0x0; /* Reserved */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/15164/16/src/northbridge/amd/pi/00730F01/northbridge.c@547">Patch Set #16, Line 547:</a> <code style="font-family:monospace,monospace"> } else if ((dev->hdr_type & 0x7f) == PCI_HEADER_TYPE_BRIDGE) {</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/15164/16/src/northbridge/amd/pi/00730F01/northbridge.c@547">Patch Set #16, Line 547:</a> <code style="font-family:monospace,monospace"> } else if ((dev->hdr_type & 0x7f) == PCI_HEADER_TYPE_BRIDGE) {</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">Too many leading tabs - consider code refactoring</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/15164/16/src/northbridge/amd/pi/00730F01/northbridge.c@548">Patch Set #16, Line 548:</a> <code style="font-family:monospace,monospace"> if (pci_find_capability(dev, PCI_CAP_ID_PCIE)) {</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/15164/16/src/northbridge/amd/pi/00730F01/northbridge.c@548">Patch Set #16, Line 548:</a> <code style="font-family:monospace,monospace"> if (pci_find_capability(dev, PCI_CAP_ID_PCIE)) {</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">Too many leading tabs - consider code refactoring</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/15164/16/src/northbridge/amd/pi/00730F01/northbridge.c@549">Patch Set #16, Line 549:</a> <code style="font-family:monospace,monospace"> /* Bridge is PCIe */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/15164/16/src/northbridge/amd/pi/00730F01/northbridge.c@550">Patch Set #16, Line 550:</a> <code style="font-family:monospace,monospace"> p = (uint8_t *) *current;</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/15164/16/src/northbridge/amd/pi/00730F01/northbridge.c@551">Patch Set #16, Line 551:</a> <code style="font-family:monospace,monospace"> p[0] = 0x2; /* Entry type */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/15164/16/src/northbridge/amd/pi/00730F01/northbridge.c@552">Patch Set #16, Line 552:</a> <code style="font-family:monospace,monospace"> p[1] = dev->path.pci.devfn; /* Device */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/15164/16/src/northbridge/amd/pi/00730F01/northbridge.c@553">Patch Set #16, Line 553:</a> <code style="font-family:monospace,monospace"> p[2] = dev->bus->secondary; /* Bus */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/15164/16/src/northbridge/amd/pi/00730F01/northbridge.c@554">Patch Set #16, Line 554:</a> <code style="font-family:monospace,monospace"> p[3] = 0x0; /* Data */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/15164/16/src/northbridge/amd/pi/00730F01/northbridge.c@555">Patch Set #16, Line 555:</a> <code style="font-family:monospace,monospace"> p[4] = 0x0; /* Padding */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/15164/16/src/northbridge/amd/pi/00730F01/northbridge.c@556">Patch Set #16, Line 556:</a> <code style="font-family:monospace,monospace"> p[5] = 0x0; /* Padding */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/15164/16/src/northbridge/amd/pi/00730F01/northbridge.c@557">Patch Set #16, Line 557:</a> <code style="font-family:monospace,monospace"> p[6] = 0x0; /* Padding */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/15164/16/src/northbridge/amd/pi/00730F01/northbridge.c@558">Patch Set #16, Line 558:</a> <code style="font-family:monospace,monospace"> p[7] = 0x0; /* Padding */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/15164/16/src/northbridge/amd/pi/00730F01/northbridge.c@570">Patch Set #16, Line 570:</a> <code style="font-family:monospace,monospace"> for (sibling = link->children; sibling; sibling = sibling->sibling)</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/15164/16/src/northbridge/amd/pi/00730F01/northbridge.c@571">Patch Set #16, Line 571:</a> <code style="font-family:monospace,monospace"> add_ivrs_device_entries(dev, sibling, depth + 1, depth, root_level, current, length);</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/15164/16/src/northbridge/amd/pi/00730F01/northbridge.c@576">Patch Set #16, Line 576:</a> <code style="font-family:monospace,monospace">unsigned long acpi_fill_ivrs_ioapic(acpi_ivrs_t* ivrs, unsigned long current)</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">"foo* bar" should be "foo *bar"</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/15164/16/src/northbridge/amd/pi/00730F01/northbridge.c@613">Patch Set #16, Line 613:</a> <code style="font-family:monospace,monospace">static unsigned long acpi_fill_ivrs(acpi_ivrs_t* ivrs, unsigned long current)</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">"foo* bar" should be "foo *bar"</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/15164/16/src/northbridge/amd/pi/00730F01/northbridge.c@619">Patch Set #16, Line 619:</a> <code style="font-family:monospace,monospace"> printk(BIOS_WARNING, "acpi_fill_ivrs: Unable to locate G-series northbridge device! IVRS table not generated...\n");</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">Prefer using '"%s...", __func__' to using 'acpi_fill_ivrs', this function's name, in a string</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/15164/16/src/northbridge/amd/pi/00730F01/northbridge.c@624">Patch Set #16, Line 624:</a> <code style="font-family:monospace,monospace"> ivrs->iv_info |= (0x40 << 15); /* Maximum supported virtual address size */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/15164/16/src/northbridge/amd/pi/00730F01/northbridge.c@625">Patch Set #16, Line 625:</a> <code style="font-family:monospace,monospace"> ivrs->iv_info |= (0x30 << 8); /* Maximum supported physical address size */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/15164/16/src/northbridge/amd/pi/00730F01/northbridge.c@630">Patch Set #16, Line 630:</a> <code style="font-family:monospace,monospace"> ivrs->ivhd.flags |= 0x10; /* Enable ATS support */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/15164/16/src/northbridge/amd/pi/00730F01/northbridge.c@632">Patch Set #16, Line 632:</a> <code style="font-family:monospace,monospace"> ivrs->ivhd.device_id = 0x2 | (nb_dev->bus->secondary << 8); /* BDF <bus>:00.2 */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/15164/16/src/northbridge/amd/pi/00730F01/northbridge.c@633">Patch Set #16, Line 633:</a> <code style="font-family:monospace,monospace"> ivrs->ivhd.capability_offset = 0x40; /* Capability block 0x40 (type 0xf, "Secure device") */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/15164/16/src/northbridge/amd/pi/00730F01/northbridge.c@655">Patch Set #16, Line 655:</a> <code style="font-family:monospace,monospace"> add_ivrs_device_entries(NULL, all_devices, 0, -1, NULL, ¤t, &ivrs->ivhd.length);</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li></ul></li></ul><p>To view, visit <a href="https://review.coreboot.org/15164">change 15164</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/15164"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: comment </div>
<div style="display:none"> Gerrit-Change-Id: I1ae789f75363435accd14a1b556e1570f43f94c4 </div>
<div style="display:none"> Gerrit-Change-Number: 15164 </div>
<div style="display:none"> Gerrit-PatchSet: 16 </div>
<div style="display:none"> Gerrit-Owner: Timothy Pearson <tpearson@raptorengineering.com> </div>
<div style="display:none"> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki@gmail.com> </div>
<div style="display:none"> Gerrit-Reviewer: Martin Roth <martinroth@google.com> </div>
<div style="display:none"> Gerrit-Reviewer: Paul Menzel <paulepanter@users.sourceforge.net> </div>
<div style="display:none"> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki@gmail.com> </div>
<div style="display:none"> Gerrit-Reviewer: Timothy Pearson <tpearson@raptorengineering.com> </div>
<div style="display:none"> Gerrit-Reviewer: build bot (Jenkins) <no-reply@coreboot.org> </div>
<div style="display:none"> Gerrit-CC: Piotr Król <piotr.krol@3mdeb.com> </div>
<div style="display:none"> Gerrit-Comment-Date: Mon, 23 Jul 2018 13:50:17 +0000 </div>
<div style="display:none"> Gerrit-HasComments: Yes </div>
<div style="display:none"> Gerrit-HasLabels: No </div>