<p>Arthur Heymans has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/27584">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">cpu/x86/mtrr.h: Rename MSR SMRR_PHYS_x to IA32_SMRR_PHYSx<br><br>This is how these MSR's are referenced in Intel® 64 and IA-32 Architectures<br>Software Developer’s Manual.<br><br>The purpose is to differentiate with MSR_SMRR_PHYSx.<br><br>Change-Id: I54875f3a6d98a28004d5bd3197923862af8f7377<br>Signed-off-by: Arthur Heymans <arthur@aheymans.xyz><br>---<br>M src/cpu/intel/haswell/smmrelocate.c<br>M src/cpu/intel/smm/gen1/smmrelocate.c<br>M src/include/cpu/x86/mtrr.h<br>M src/soc/intel/apollolake/cpu.c<br>M src/soc/intel/baytrail/cpu.c<br>M src/soc/intel/braswell/cpu.c<br>M src/soc/intel/broadwell/smmrelocate.c<br>M src/soc/intel/cannonlake/smmrelocate.c<br>M src/soc/intel/denverton_ns/cpu.c<br>M src/soc/intel/fsp_baytrail/cpu.c<br>M src/soc/intel/fsp_broadwell_de/smmrelocate.c<br>M src/soc/intel/skylake/smmrelocate.c<br>12 files changed, 24 insertions(+), 24 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/27584/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/cpu/intel/haswell/smmrelocate.c b/src/cpu/intel/haswell/smmrelocate.c</span><br><span>index 9ff1e55..55d34a0 100644</span><br><span>--- a/src/cpu/intel/haswell/smmrelocate.c</span><br><span>+++ b/src/cpu/intel/haswell/smmrelocate.c</span><br><span>@@ -70,8 +70,8 @@</span><br><span> {</span><br><span> printk(BIOS_DEBUG, "Writing SMRR. base = 0x%08x, mask=0x%08x\n",</span><br><span> relo_params->smrr_base.lo, relo_params->smrr_mask.lo);</span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr(SMRR_PHYS_BASE, relo_params->smrr_base);</span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr(SMRR_PHYS_MASK, relo_params->smrr_mask);</span><br><span style="color: hsl(120, 100%, 40%);">+ wrmsr(IA32_SMRR_PHYSBASE, relo_params->smrr_base);</span><br><span style="color: hsl(120, 100%, 40%);">+ wrmsr(IA32_SMRR_PHYSMASK, relo_params->smrr_mask);</span><br><span> }</span><br><span> </span><br><span> static inline void write_emrr(struct smm_relocation_params *relo_params)</span><br><span>diff --git a/src/cpu/intel/smm/gen1/smmrelocate.c b/src/cpu/intel/smm/gen1/smmrelocate.c</span><br><span>index e80fa31..e3cb11b 100644</span><br><span>--- a/src/cpu/intel/smm/gen1/smmrelocate.c</span><br><span>+++ b/src/cpu/intel/smm/gen1/smmrelocate.c</span><br><span>@@ -61,8 +61,8 @@</span><br><span> {</span><br><span> printk(BIOS_DEBUG, "Writing SMRR. base = 0x%08x, mask=0x%08x\n",</span><br><span> relo_params->smrr_base.lo, relo_params->smrr_mask.lo);</span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr(SMRR_PHYS_BASE, relo_params->smrr_base);</span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr(SMRR_PHYS_MASK, relo_params->smrr_mask);</span><br><span style="color: hsl(120, 100%, 40%);">+ wrmsr(IA32_SMRR_PHYSBASE, relo_params->smrr_base);</span><br><span style="color: hsl(120, 100%, 40%);">+ wrmsr(IA32_SMRR_PHYSMASK, relo_params->smrr_mask);</span><br><span> }</span><br><span> </span><br><span> /* The relocation work is actually performed in SMM context, but the code</span><br><span>diff --git a/src/include/cpu/x86/mtrr.h b/src/include/cpu/x86/mtrr.h</span><br><span>index f52a77b..58a3ce5 100644</span><br><span>--- a/src/include/cpu/x86/mtrr.h</span><br><span>+++ b/src/include/cpu/x86/mtrr.h</span><br><span>@@ -28,8 +28,8 @@</span><br><span> #define MTRR_DEF_TYPE_FIX_EN (1 << 10)</span><br><span> </span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-#define SMRR_PHYS_BASE 0x1f2</span><br><span style="color: hsl(0, 100%, 40%);">-#define SMRR_PHYS_MASK 0x1f3</span><br><span style="color: hsl(120, 100%, 40%);">+#define IA32_SMRR_PHYSBASE 0x1f2</span><br><span style="color: hsl(120, 100%, 40%);">+#define IA32_SMRR_PHYSMASK 0x1f3</span><br><span> </span><br><span> #define MTRR_PHYS_BASE(reg) (0x200 + 2 * (reg))</span><br><span> #define MTRR_PHYS_MASK(reg) (MTRR_PHYS_BASE(reg) + 1)</span><br><span>diff --git a/src/soc/intel/apollolake/cpu.c b/src/soc/intel/apollolake/cpu.c</span><br><span>index 6905894..1367160 100644</span><br><span>--- a/src/soc/intel/apollolake/cpu.c</span><br><span>+++ b/src/soc/intel/apollolake/cpu.c</span><br><span>@@ -223,10 +223,10 @@</span><br><span> /* Set up SMRR. */</span><br><span> smrr.lo = relo_attrs.smrr_base;</span><br><span> smrr.hi = 0;</span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr(SMRR_PHYS_BASE, smrr);</span><br><span style="color: hsl(120, 100%, 40%);">+ wrmsr(IA32_SMRR_PHYSBASE, smrr);</span><br><span> smrr.lo = relo_attrs.smrr_mask;</span><br><span> smrr.hi = 0;</span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr(SMRR_PHYS_MASK, smrr);</span><br><span style="color: hsl(120, 100%, 40%);">+ wrmsr(IA32_SMRR_PHYSMASK, smrr);</span><br><span> smm_state = (void *)(SMM_EM64T100_SAVE_STATE_OFFSET + curr_smbase);</span><br><span> smm_state->smbase = staggered_smbase;</span><br><span> }</span><br><span>diff --git a/src/soc/intel/baytrail/cpu.c b/src/soc/intel/baytrail/cpu.c</span><br><span>index 77d2dda..ea299ce 100644</span><br><span>--- a/src/soc/intel/baytrail/cpu.c</span><br><span>+++ b/src/soc/intel/baytrail/cpu.c</span><br><span>@@ -179,10 +179,10 @@</span><br><span> /* Set up SMRR. */</span><br><span> smrr.lo = relo_attrs.smrr_base;</span><br><span> smrr.hi = 0;</span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr(SMRR_PHYS_BASE, smrr);</span><br><span style="color: hsl(120, 100%, 40%);">+ wrmsr(IA32_SMRR_PHYSBASE, smrr);</span><br><span> smrr.lo = relo_attrs.smrr_mask;</span><br><span> smrr.hi = 0;</span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr(SMRR_PHYS_MASK, smrr);</span><br><span style="color: hsl(120, 100%, 40%);">+ wrmsr(IA32_SMRR_PHYSMASK, smrr);</span><br><span> </span><br><span> smm_state = (void *)(SMM_EM64T100_SAVE_STATE_OFFSET + curr_smbase);</span><br><span> smm_state->smbase = staggered_smbase;</span><br><span>diff --git a/src/soc/intel/braswell/cpu.c b/src/soc/intel/braswell/cpu.c</span><br><span>index 31b1b78..17aa36a 100644</span><br><span>--- a/src/soc/intel/braswell/cpu.c</span><br><span>+++ b/src/soc/intel/braswell/cpu.c</span><br><span>@@ -195,10 +195,10 @@</span><br><span> /* Set up SMRR. */</span><br><span> smrr.lo = relo_attrs.smrr_base;</span><br><span> smrr.hi = 0;</span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr(SMRR_PHYS_BASE, smrr);</span><br><span style="color: hsl(120, 100%, 40%);">+ wrmsr(IA32_SMRR_PHYSBASE, smrr);</span><br><span> smrr.lo = relo_attrs.smrr_mask;</span><br><span> smrr.hi = 0;</span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr(SMRR_PHYS_MASK, smrr);</span><br><span style="color: hsl(120, 100%, 40%);">+ wrmsr(IA32_SMRR_PHYSMASK, smrr);</span><br><span> </span><br><span> smm_state = (void *)(SMM_EM64T100_SAVE_STATE_OFFSET + curr_smbase);</span><br><span> smm_state->smbase = staggered_smbase;</span><br><span>diff --git a/src/soc/intel/broadwell/smmrelocate.c b/src/soc/intel/broadwell/smmrelocate.c</span><br><span>index 2d90ebc..e9a215c 100644</span><br><span>--- a/src/soc/intel/broadwell/smmrelocate.c</span><br><span>+++ b/src/soc/intel/broadwell/smmrelocate.c</span><br><span>@@ -38,8 +38,8 @@</span><br><span> {</span><br><span> printk(BIOS_DEBUG, "Writing SMRR. base = 0x%08x, mask=0x%08x\n",</span><br><span> relo_params->smrr_base.lo, relo_params->smrr_mask.lo);</span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr(SMRR_PHYS_BASE, relo_params->smrr_base);</span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr(SMRR_PHYS_MASK, relo_params->smrr_mask);</span><br><span style="color: hsl(120, 100%, 40%);">+ wrmsr(IA32_SMRR_PHYSBASE, relo_params->smrr_base);</span><br><span style="color: hsl(120, 100%, 40%);">+ wrmsr(IA32_SMRR_PHYSMASK, relo_params->smrr_mask);</span><br><span> }</span><br><span> </span><br><span> static inline void write_emrr(struct smm_relocation_params *relo_params)</span><br><span>diff --git a/src/soc/intel/cannonlake/smmrelocate.c b/src/soc/intel/cannonlake/smmrelocate.c</span><br><span>index 3c60ef2..9e89265 100644</span><br><span>--- a/src/soc/intel/cannonlake/smmrelocate.c</span><br><span>+++ b/src/soc/intel/cannonlake/smmrelocate.c</span><br><span>@@ -41,8 +41,8 @@</span><br><span> {</span><br><span> printk(BIOS_DEBUG, "Writing SMRR. base = 0x%08x, mask=0x%08x\n",</span><br><span> relo_params->smrr_base.lo, relo_params->smrr_mask.lo);</span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr(SMRR_PHYS_BASE, relo_params->smrr_base);</span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr(SMRR_PHYS_MASK, relo_params->smrr_mask);</span><br><span style="color: hsl(120, 100%, 40%);">+ wrmsr(IA32_SMRR_PHYSBASE, relo_params->smrr_base);</span><br><span style="color: hsl(120, 100%, 40%);">+ wrmsr(IA32_SMRR_PHYSMASK, relo_params->smrr_mask);</span><br><span> }</span><br><span> </span><br><span> static void update_save_state(int cpu, uintptr_t curr_smbase,</span><br><span>diff --git a/src/soc/intel/denverton_ns/cpu.c b/src/soc/intel/denverton_ns/cpu.c</span><br><span>index d486435..815bd46 100644</span><br><span>--- a/src/soc/intel/denverton_ns/cpu.c</span><br><span>+++ b/src/soc/intel/denverton_ns/cpu.c</span><br><span>@@ -80,10 +80,10 @@</span><br><span> /* Set up SMRR. */</span><br><span> smrr.lo = relo_attrs.smrr_base;</span><br><span> smrr.hi = 0;</span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr(SMRR_PHYS_BASE, smrr);</span><br><span style="color: hsl(120, 100%, 40%);">+ wrmsr(IA32_SMRR_PHYSBASE, smrr);</span><br><span> smrr.lo = relo_attrs.smrr_mask;</span><br><span> smrr.hi = 0;</span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr(SMRR_PHYS_MASK, smrr);</span><br><span style="color: hsl(120, 100%, 40%);">+ wrmsr(IA32_SMRR_PHYSMASK, smrr);</span><br><span> smm_state = (void *)(SMM_EM64T100_SAVE_STATE_OFFSET + curr_smbase);</span><br><span> smm_state->smbase = staggered_smbase;</span><br><span> }</span><br><span>diff --git a/src/soc/intel/fsp_baytrail/cpu.c b/src/soc/intel/fsp_baytrail/cpu.c</span><br><span>index c7694b9..44cd403 100644</span><br><span>--- a/src/soc/intel/fsp_baytrail/cpu.c</span><br><span>+++ b/src/soc/intel/fsp_baytrail/cpu.c</span><br><span>@@ -139,10 +139,10 @@</span><br><span> /* Set up SMRR. */</span><br><span> smrr.lo = relo_attrs.smrr_base;</span><br><span> smrr.hi = 0;</span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr(SMRR_PHYS_BASE, smrr);</span><br><span style="color: hsl(120, 100%, 40%);">+ wrmsr(IA32_SMRR_PHYSBASE, smrr);</span><br><span> smrr.lo = relo_attrs.smrr_mask;</span><br><span> smrr.hi = 0;</span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr(SMRR_PHYS_MASK, smrr);</span><br><span style="color: hsl(120, 100%, 40%);">+ wrmsr(IA32_SMRR_PHYSMASK, smrr);</span><br><span> </span><br><span> smm_state = (void *)(SMM_EM64T100_SAVE_STATE_OFFSET + curr_smbase);</span><br><span> smm_state->smbase = staggered_smbase;</span><br><span>diff --git a/src/soc/intel/fsp_broadwell_de/smmrelocate.c b/src/soc/intel/fsp_broadwell_de/smmrelocate.c</span><br><span>index 28bc8c9..a0f3e5a 100644</span><br><span>--- a/src/soc/intel/fsp_broadwell_de/smmrelocate.c</span><br><span>+++ b/src/soc/intel/fsp_broadwell_de/smmrelocate.c</span><br><span>@@ -39,8 +39,8 @@</span><br><span> {</span><br><span> printk(BIOS_DEBUG, "Writing SMRR. base = 0x%08x, mask=0x%08x\n",</span><br><span> relo_params->smrr_base.lo, relo_params->smrr_mask.lo);</span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr(SMRR_PHYS_BASE, relo_params->smrr_base);</span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr(SMRR_PHYS_MASK, relo_params->smrr_mask);</span><br><span style="color: hsl(120, 100%, 40%);">+ wrmsr(IA32_SMRR_PHYSBASE, relo_params->smrr_base);</span><br><span style="color: hsl(120, 100%, 40%);">+ wrmsr(IA32_SMRR_PHYSMASK, relo_params->smrr_mask);</span><br><span> }</span><br><span> </span><br><span> static inline void write_prmrr(struct smm_relocation_params *relo_params)</span><br><span>diff --git a/src/soc/intel/skylake/smmrelocate.c b/src/soc/intel/skylake/smmrelocate.c</span><br><span>index 6a8e64b..800811a 100644</span><br><span>--- a/src/soc/intel/skylake/smmrelocate.c</span><br><span>+++ b/src/soc/intel/skylake/smmrelocate.c</span><br><span>@@ -41,8 +41,8 @@</span><br><span> {</span><br><span> printk(BIOS_DEBUG, "Writing SMRR. base = 0x%08x, mask=0x%08x\n",</span><br><span> relo_params->smrr_base.lo, relo_params->smrr_mask.lo);</span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr(SMRR_PHYS_BASE, relo_params->smrr_base);</span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr(SMRR_PHYS_MASK, relo_params->smrr_mask);</span><br><span style="color: hsl(120, 100%, 40%);">+ wrmsr(IA32_SMRR_PHYSBASE, relo_params->smrr_base);</span><br><span style="color: hsl(120, 100%, 40%);">+ wrmsr(IA32_SMRR_PHYSMASK, relo_params->smrr_mask);</span><br><span> }</span><br><span> </span><br><span> static inline void write_uncore_emrr(struct smm_relocation_params *relo_params)</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/27584">change 27584</a>. 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<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I54875f3a6d98a28004d5bd3197923862af8f7377 </div>
<div style="display:none"> Gerrit-Change-Number: 27584 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Arthur Heymans <arthur@aheymans.xyz> </div>