<p>Elyes HAOUAS has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/27558">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">cpu/intel/model_f6x: Add model F6x for i945 parallel MP init<br><br>Change-Id: I62eedf2e6f1fd79fa3bf4e173e5317a7c775cdef<br>Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr><br>---<br>M src/cpu/intel/model_f6x/Makefile.inc<br>M src/cpu/intel/model_f6x/model_f6x_init.c<br>2 files changed, 4 insertions(+), 2 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/27558/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/cpu/intel/model_f6x/Makefile.inc b/src/cpu/intel/model_f6x/Makefile.inc</span><br><span>index 855fc9e..8f4a282 100644</span><br><span>--- a/src/cpu/intel/model_f6x/Makefile.inc</span><br><span>+++ b/src/cpu/intel/model_f6x/Makefile.inc</span><br><span>@@ -1,4 +1,5 @@</span><br><span> ramstage-y += model_f6x_init.c</span><br><span> subdirs-$(CONFIG_SMM_TSEG) += ../smm/gen1</span><br><span style="color: hsl(120, 100%, 40%);">+ramstage-$(CONFIG_PARALLEL_MP) += ../model_1067x/mp_init.c</span><br><span> </span><br><span> cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_f6x/microcode.bin</span><br><span>diff --git a/src/cpu/intel/model_f6x/model_f6x_init.c b/src/cpu/intel/model_f6x/model_f6x_init.c</span><br><span>index 496f563..194a528 100644</span><br><span>--- a/src/cpu/intel/model_f6x/model_f6x_init.c</span><br><span>+++ b/src/cpu/intel/model_f6x/model_f6x_init.c</span><br><span>@@ -27,7 +27,7 @@</span><br><span>   /* Turn on caching if we haven't already */</span><br><span>      x86_enable_cache();</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- if (!intel_ht_sibling()) {</span><br><span style="color: hsl(120, 100%, 40%);">+    if (!IS_ENABLED(CONFIG_PARALLEL_MP) && !intel_ht_sibling()) {</span><br><span>                /* MTRRs are shared between threads */</span><br><span>               x86_setup_mtrrs();</span><br><span>           x86_mtrr_check();</span><br><span>@@ -40,7 +40,8 @@</span><br><span>        setup_lapic();</span><br><span> </span><br><span>   /* Start up my CPU siblings */</span><br><span style="color: hsl(0, 100%, 40%);">-  intel_sibling_init(cpu);</span><br><span style="color: hsl(120, 100%, 40%);">+      if (!IS_ENABLED(CONFIG_PARALLEL_MP))</span><br><span style="color: hsl(120, 100%, 40%);">+          intel_sibling_init(cpu);</span><br><span> };</span><br><span> </span><br><span> static struct device_operations cpu_dev_ops = {</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/27558">change 27558</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/27558"/><meta itemprop="name" content="View Change"/></div></div>

<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I62eedf2e6f1fd79fa3bf4e173e5317a7c775cdef </div>
<div style="display:none"> Gerrit-Change-Number: 27558 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Elyes HAOUAS <ehaouas@noos.fr> </div>