<p>Xiang Wang has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/27543">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">This fix issus(202e7d4f3c)<br><br>When I tried to compile the RISC-V code, I found some errors:<br>     is undefined<br>    src/arch/riscv/timestamp.c does not exist<br>Currently RISC-V does not have the implementation and use of timestamp, so I<br>temporarily deleted the code related to timestamp in the makefile.And defined<br>PRIu64.<br><br>Change-Id: I7f1a0793113bce7c1411e39f102cf20dbadda5d6<br>Signed-off-by: Xiang Wang <wxjstz@126.com><br>---<br>M src/arch/riscv/Makefile.inc<br>M src/arch/riscv/include/stdint.h<br>2 files changed, 4 insertions(+), 6 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/27543/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/arch/riscv/Makefile.inc b/src/arch/riscv/Makefile.inc</span><br><span>index dab661e..e00469b 100644</span><br><span>--- a/src/arch/riscv/Makefile.inc</span><br><span>+++ b/src/arch/riscv/Makefile.inc</span><br><span>@@ -82,8 +82,6 @@</span><br><span>       $(top)/src/lib/memmove.c \</span><br><span>   $(top)/src/lib/memset.c</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-romstage-$(CONFIG_COLLECT_TIMESTAMPS) += timestamp.c</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span> # Build the romstage</span><br><span> </span><br><span> $(objcbfs)/romstage.debug: $$(romstage-objs)</span><br><span>@@ -116,8 +114,6 @@</span><br><span> </span><br><span> $(eval $(call create_class_compiler,rmodules,riscv))</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-ramstage-$(CONFIG_COLLECT_TIMESTAMPS) += timestamp.c</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span> ramstage-srcs += src/mainboard/$(MAINBOARDDIR)/mainboard.c</span><br><span> </span><br><span> # Build the ramstage</span><br><span>diff --git a/src/arch/riscv/include/stdint.h b/src/arch/riscv/include/stdint.h</span><br><span>index 446a136..f8d1736 100644</span><br><span>--- a/src/arch/riscv/include/stdint.h</span><br><span>+++ b/src/arch/riscv/include/stdint.h</span><br><span>@@ -70,7 +70,9 @@</span><br><span> #define false   0</span><br><span> </span><br><span> /* Types for `void *' pointers.  */</span><br><span style="color: hsl(0, 100%, 40%);">-typedef s64             intptr_t;</span><br><span style="color: hsl(0, 100%, 40%);">-typedef u64            uintptr_t;</span><br><span style="color: hsl(120, 100%, 40%);">+typedef s64    intptr_t;</span><br><span style="color: hsl(120, 100%, 40%);">+typedef u64           uintptr_t;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define PRIu64  "llu"</span><br><span> </span><br><span> #endif /* RISCV_STDINT_H */</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/27543">change 27543</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/27543"/><meta itemprop="name" content="View Change"/></div></div>

<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I7f1a0793113bce7c1411e39f102cf20dbadda5d6 </div>
<div style="display:none"> Gerrit-Change-Number: 27543 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Xiang Wang <wxjstz@126.com> </div>