<p>Maulik V Vaghela has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/27522">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">src/soc/intel: Add new device IDs<br><br>Added new device IDs for SATA, GT and Northbridge to pci_ids.h<br>Added entry to identify CFL U GT into systemagent.c<br>Added CFL CPU D0 stepping ID to mp_init.h and mp_init.c<br><br>Change-Id: I47c97fb9eb813587cd655e2bce05a686091619ed<br>Signed-off-by: Maulik <maulik.v.vaghela@intel.com><br>---<br>M src/include/device/pci_ids.h<br>M src/soc/intel/common/block/cpu/mp_init.c<br>M src/soc/intel/common/block/include/intelblocks/mp_init.h<br>M src/soc/intel/common/block/systemagent/systemagent.c<br>4 files changed, 13 insertions(+), 0 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/22/27522/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h</span><br><span>index 40f2ea4..8e0c202 100644</span><br><span>--- a/src/include/device/pci_ids.h</span><br><span>+++ b/src/include/device/pci_ids.h</span><br><span>@@ -2774,6 +2774,8 @@</span><br><span> #define PCI_DEVICE_ID_INTEL_CNL_SATA 0x9dd5</span><br><span> #define PCI_DEVICE_ID_INTEL_CNL_PREMIUM_SATA 0x9dd7</span><br><span> #define PCI_DEVICE_ID_INTEL_CNL_COMPAT_SATA 0x282a</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCI_DEVICE_ID_INTEL_CNL_H_SATA 0xa352</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCI_DEVICE_ID_INTEL_CNL_L_SATA 0x9dd3</span><br><span> </span><br><span> /* Intel PMC device Ids */</span><br><span> #define PCI_DEVICE_ID_INTEL_SPT_LP_PMC 0x9d21</span><br><span>@@ -2881,6 +2883,7 @@</span><br><span> #define PCI_DEVICE_ID_INTEL_CNL_GT2_ULT_2 0x5A5A</span><br><span> #define PCI_DEVICE_ID_INTEL_CNL_GT2_ULT_3 0x5A42</span><br><span> #define PCI_DEVICE_ID_INTEL_CNL_GT2_ULT_4 0x5A4A</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCI_DEVICE_ID_INTEL_CFL_GT2_ULT 0x3EA5</span><br><span> </span><br><span> /* Intel Northbridge Ids */</span><br><span> #define PCI_DEVICE_ID_INTEL_APL_NB 0x5af0</span><br><span>@@ -2898,6 +2901,7 @@</span><br><span> #define PCI_DEVICE_ID_INTEL_KBL_ID_DT 0x591f</span><br><span> #define PCI_DEVICE_ID_INTEL_CNL_ID_U 0x5A04</span><br><span> #define PCI_DEVICE_ID_INTEL_CNL_ID_Y 0x5A02</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCI_DEVICE_ID_INTEL_CFL_ID_U 0x3ED0</span><br><span> </span><br><span> /* Intel SMBUS device Ids */</span><br><span> #define PCI_DEVICE_ID_INTEL_SPT_LP_SMBUS 0x9d23</span><br><span>diff --git a/src/soc/intel/common/block/cpu/mp_init.c b/src/soc/intel/common/block/cpu/mp_init.c</span><br><span>index fd0ac99..8235aaf 100644</span><br><span>--- a/src/soc/intel/common/block/cpu/mp_init.c</span><br><span>+++ b/src/soc/intel/common/block/cpu/mp_init.c</span><br><span>@@ -71,6 +71,10 @@</span><br><span> { X86_VENDOR_INTEL, CPUID_APOLLOLAKE_E0 },</span><br><span> { X86_VENDOR_INTEL, CPUID_GLK_A0 },</span><br><span> { X86_VENDOR_INTEL, CPUID_GLK_B0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ { X86_VENDOR_INTEL, CPUID_WHISKEYLAKE_B0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ { X86_VENDOR_INTEL, CPUID_COFFEELAKE_A0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ { X86_VENDOR_INTEL, CPUID_COFFEELAKE_U0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ { X86_VENDOR_INTEL, CPUID_COFFEELAKE_D0 },</span><br><span> { 0, 0 },</span><br><span> };</span><br><span> </span><br><span>diff --git a/src/soc/intel/common/block/include/intelblocks/mp_init.h b/src/soc/intel/common/block/include/intelblocks/mp_init.h</span><br><span>index 3057209..9680fbe 100644</span><br><span>--- a/src/soc/intel/common/block/include/intelblocks/mp_init.h</span><br><span>+++ b/src/soc/intel/common/block/include/intelblocks/mp_init.h</span><br><span>@@ -37,6 +37,10 @@</span><br><span> #define CPUID_APOLLOLAKE_E0 0x506ca</span><br><span> #define CPUID_GLK_A0 0x706a0</span><br><span> #define CPUID_GLK_B0 0x706a1</span><br><span style="color: hsl(120, 100%, 40%);">+#define CPUID_WHISKEYLAKE_B0 0x806eb</span><br><span style="color: hsl(120, 100%, 40%);">+#define CPUID_COFFEELAKE_A0 0x906ea</span><br><span style="color: hsl(120, 100%, 40%);">+#define CPUID_COFFEELAKE_U0 0x906ea</span><br><span style="color: hsl(120, 100%, 40%);">+#define CPUID_COFFEELAKE_D0 0x806ea</span><br><span> </span><br><span> /*</span><br><span> * MP Init callback function to Find CPU Topology. This function is common</span><br><span>diff --git a/src/soc/intel/common/block/systemagent/systemagent.c b/src/soc/intel/common/block/systemagent/systemagent.c</span><br><span>index 54646c9..3229632 100644</span><br><span>--- a/src/soc/intel/common/block/systemagent/systemagent.c</span><br><span>+++ b/src/soc/intel/common/block/systemagent/systemagent.c</span><br><span>@@ -301,6 +301,7 @@</span><br><span> PCI_DEVICE_ID_INTEL_KBL_ID_H,</span><br><span> PCI_DEVICE_ID_INTEL_KBL_U_R,</span><br><span> PCI_DEVICE_ID_INTEL_KBL_ID_DT,</span><br><span style="color: hsl(120, 100%, 40%);">+ PCI_DEVICE_ID_INTEL_CFL_ID_U,</span><br><span> 0</span><br><span> };</span><br><span> </span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/27522">change 27522</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/27522"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I47c97fb9eb813587cd655e2bce05a686091619ed </div>
<div style="display:none"> Gerrit-Change-Number: 27522 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Maulik V Vaghela <maulik.v.vaghela@intel.com> </div>