<p>Arthur Heymans has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/27515">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">nb/intel/nehalem: Remove the C native graphic init<br><br>Libgfxinit provides a better alternative to the native C init. While libgfxinit<br>mandates an ada compiler, we want to encourage use of it since it is in much<br>better shape and is actually maintained.<br><br>This way libgfxinit also gets build-tested by Jenkins.<br><br>Change-Id: I9228fa7eadfe2a827c1f4de9d6710b60d3f1b121<br>Signed-off-by: Arthur Heymans <arthur@aheymans.xyz><br>---<br>M src/northbridge/intel/nehalem/gma.c<br>1 file changed, 4 insertions(+), 459 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/27515/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/northbridge/intel/nehalem/gma.c b/src/northbridge/intel/nehalem/gma.c</span><br><span>index aeff69a..6e2d404 100644</span><br><span>--- a/src/northbridge/intel/nehalem/gma.c</span><br><span>+++ b/src/northbridge/intel/nehalem/gma.c</span><br><span>@@ -571,441 +571,6 @@</span><br><span> }</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void train_link(u8 *mmio)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- /* Clear interrupts. */</span><br><span style="color: hsl(0, 100%, 40%);">- write32(mmio + DEIIR, 0xffffffff);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- write32(mmio + 0x000f0018, 0x000000ff);</span><br><span style="color: hsl(0, 100%, 40%);">- write32(mmio + 0x000f1018, 0x000000ff);</span><br><span style="color: hsl(0, 100%, 40%);">- write32(mmio + 0x000f000c, 0x001a2050);</span><br><span style="color: hsl(0, 100%, 40%);">- write32(mmio + 0x00060100, 0x001c4000);</span><br><span style="color: hsl(0, 100%, 40%);">- write32(mmio + 0x00060100, 0x801c4000);</span><br><span style="color: hsl(0, 100%, 40%);">- write32(mmio + 0x000f000c, 0x801a2050);</span><br><span style="color: hsl(0, 100%, 40%);">- write32(mmio + 0x00060100, 0x801c4000);</span><br><span style="color: hsl(0, 100%, 40%);">- write32(mmio + 0x000f000c, 0x801a2050);</span><br><span style="color: hsl(0, 100%, 40%);">- mdelay(1);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- read32(mmio + 0x000f0014); // = 0x00000100</span><br><span style="color: hsl(0, 100%, 40%);">- write32(mmio + 0x000f0014, 0x00000100);</span><br><span style="color: hsl(0, 100%, 40%);">- write32(mmio + 0x00060100, 0x901c4000);</span><br><span style="color: hsl(0, 100%, 40%);">- write32(mmio + 0x000f000c, 0x901a2050);</span><br><span style="color: hsl(0, 100%, 40%);">- mdelay(1);</span><br><span style="color: hsl(0, 100%, 40%);">- read32(mmio + 0x000f0014); // = 0x00000600</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-static void power_port(u8 *mmio)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- read32(mmio + 0x000e1100); // = 0x00000000</span><br><span style="color: hsl(0, 100%, 40%);">- write32(mmio + 0x000e1100, 0x00000000);</span><br><span style="color: hsl(0, 100%, 40%);">- write32(mmio + 0x000e1100, 0x00010000);</span><br><span style="color: hsl(0, 100%, 40%);">- read32(mmio + 0x000e1100); // = 0x00010000</span><br><span style="color: hsl(0, 100%, 40%);">- read32(mmio + 0x000e1100); // = 0x00010000</span><br><span style="color: hsl(0, 100%, 40%);">- read32(mmio + 0x000e1100); // = 0x00000000</span><br><span style="color: hsl(0, 100%, 40%);">- write32(mmio + 0x000e1100, 0x00000000);</span><br><span style="color: hsl(0, 100%, 40%);">- read32(mmio + 0x000e1100); // = 0x00000000</span><br><span style="color: hsl(0, 100%, 40%);">- read32(mmio + 0x000e4200); // = 0x0000001c</span><br><span style="color: hsl(0, 100%, 40%);">- write32(mmio + 0x000e4210, 0x8004003e);</span><br><span style="color: hsl(0, 100%, 40%);">- write32(mmio + 0x000e4214, 0x80060002);</span><br><span style="color: hsl(0, 100%, 40%);">- write32(mmio + 0x000e4218, 0x01000000);</span><br><span style="color: hsl(0, 100%, 40%);">- read32(mmio + 0x000e4210); // = 0x5144003e</span><br><span style="color: hsl(0, 100%, 40%);">- write32(mmio + 0x000e4210, 0x5344003e);</span><br><span style="color: hsl(0, 100%, 40%);">- read32(mmio + 0x000e4210); // = 0x0144003e</span><br><span style="color: hsl(0, 100%, 40%);">- write32(mmio + 0x000e4210, 0x8074003e);</span><br><span style="color: hsl(0, 100%, 40%);">- read32(mmio + 0x000e4210); // = 0x5144003e</span><br><span style="color: hsl(0, 100%, 40%);">- read32(mmio + 0x000e4210); // = 0x5144003e</span><br><span style="color: hsl(0, 100%, 40%);">- write32(mmio + 0x000e4210, 0x5344003e);</span><br><span style="color: hsl(0, 100%, 40%);">- read32(mmio + 0x000e4210); // = 0x0144003e</span><br><span style="color: hsl(0, 100%, 40%);">- write32(mmio + 0x000e4210, 0x8074003e);</span><br><span style="color: hsl(0, 100%, 40%);">- read32(mmio + 0x000e4210); // = 0x5144003e</span><br><span style="color: hsl(0, 100%, 40%);">- read32(mmio + 0x000e4210); // = 0x5144003e</span><br><span style="color: hsl(0, 100%, 40%);">- write32(mmio + 0x000e4210, 0x5344003e);</span><br><span style="color: hsl(0, 100%, 40%);">- read32(mmio + 0x000e4210); // = 0x0144003e</span><br><span style="color: hsl(0, 100%, 40%);">- write32(mmio + 0x000e4210, 0x8074003e);</span><br><span style="color: hsl(0, 100%, 40%);">- read32(mmio + 0x000e4210); // = 0x5144003e</span><br><span style="color: hsl(0, 100%, 40%);">- read32(mmio + 0x000e4210); // = 0x5144003e</span><br><span style="color: hsl(0, 100%, 40%);">- write32(mmio + 0x000e4210, 0x5344003e);</span><br><span style="color: hsl(0, 100%, 40%);">- write32(mmio + 0x000e4f00, 0x0100030c);</span><br><span style="color: hsl(0, 100%, 40%);">- write32(mmio + 0x000e4f04, 0x00b8230c);</span><br><span style="color: hsl(0, 100%, 40%);">- write32(mmio + 0x000e4f08, 0x06f8930c);</span><br><span style="color: hsl(0, 100%, 40%);">- write32(mmio + 0x000e4f0c, 0x09f8e38e);</span><br><span style="color: hsl(0, 100%, 40%);">- write32(mmio + 0x000e4f10, 0x00b8030c);</span><br><span style="color: hsl(0, 100%, 40%);">- write32(mmio + 0x000e4f14, 0x0b78830c);</span><br><span style="color: hsl(0, 100%, 40%);">- write32(mmio + 0x000e4f18, 0x0ff8d3cf);</span><br><span style="color: hsl(0, 100%, 40%);">- write32(mmio + 0x000e4f1c, 0x01e8030c);</span><br><span style="color: hsl(0, 100%, 40%);">- write32(mmio + 0x000e4f20, 0x0ff863cf);</span><br><span style="color: hsl(0, 100%, 40%);">- write32(mmio + 0x000e4f24, 0x0ff803cf);</span><br><span style="color: hsl(0, 100%, 40%);">- write32(mmio + 0x000c4030, 0x00001000);</span><br><span style="color: hsl(0, 100%, 40%);">- read32(mmio + 0x000c4000); // = 0x00000000</span><br><span style="color: hsl(0, 100%, 40%);">- write32(mmio + 0x000c4030, 0x00001000);</span><br><span style="color: hsl(0, 100%, 40%);">- read32(mmio + 0x000e1150); // = 0x0000001c</span><br><span style="color: hsl(0, 100%, 40%);">- write32(mmio + 0x000e1150, 0x0000089c);</span><br><span style="color: hsl(0, 100%, 40%);">- write32(mmio + 0x000fcc00, 0x01986f00);</span><br><span style="color: hsl(0, 100%, 40%);">- write32(mmio + 0x000fcc0c, 0x01986f00);</span><br><span style="color: hsl(0, 100%, 40%);">- write32(mmio + 0x000fcc18, 0x01986f00);</span><br><span style="color: hsl(0, 100%, 40%);">- write32(mmio + 0x000fcc24, 0x01986f00);</span><br><span style="color: hsl(0, 100%, 40%);">- read32(mmio + 0x000c4000); // = 0x00000000</span><br><span style="color: hsl(0, 100%, 40%);">- read32(mmio + 0x000e1180); // = 0x40000002</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-static void intel_gma_init(const struct northbridge_intel_nehalem_config *info,</span><br><span style="color: hsl(0, 100%, 40%);">- u8 *mmio, u32 physbase, u16 piobase, u32 lfb)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- int i;</span><br><span style="color: hsl(0, 100%, 40%);">- u8 edid_data[128];</span><br><span style="color: hsl(0, 100%, 40%);">- struct edid edid;</span><br><span style="color: hsl(0, 100%, 40%);">- struct edid_mode *mode;</span><br><span style="color: hsl(0, 100%, 40%);">- u32 hactive, vactive, right_border, bottom_border;</span><br><span style="color: hsl(0, 100%, 40%);">- int hpolarity, vpolarity;</span><br><span style="color: hsl(0, 100%, 40%);">- u32 vsync, hsync, vblank, hblank, hfront_porch, vfront_porch;</span><br><span style="color: hsl(0, 100%, 40%);">- u32 candp1, candn;</span><br><span style="color: hsl(0, 100%, 40%);">- u32 best_delta = 0xffffffff;</span><br><span style="color: hsl(0, 100%, 40%);">- u32 target_frequency;</span><br><span style="color: hsl(0, 100%, 40%);">- u32 pixel_p1 = 1;</span><br><span style="color: hsl(0, 100%, 40%);">- u32 pixel_n = 1;</span><br><span style="color: hsl(0, 100%, 40%);">- u32 pixel_m1 = 1;</span><br><span style="color: hsl(0, 100%, 40%);">- u32 pixel_m2 = 1;</span><br><span style="color: hsl(0, 100%, 40%);">- u32 link_frequency = info->gfx.link_frequency_270_mhz ? 270000 : 162000;</span><br><span style="color: hsl(0, 100%, 40%);">- u32 data_m1;</span><br><span style="color: hsl(0, 100%, 40%);">- u32 data_n1 = 0x00800000;</span><br><span style="color: hsl(0, 100%, 40%);">- u32 link_m1;</span><br><span style="color: hsl(0, 100%, 40%);">- u32 link_n1 = 0x00080000;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- write32(mmio + 0x00070080, 0x00000000);</span><br><span style="color: hsl(0, 100%, 40%);">- write32(mmio + DSPCNTR(0), 0x00000000);</span><br><span style="color: hsl(0, 100%, 40%);">- write32(mmio + 0x00071180, 0x00000000);</span><br><span style="color: hsl(0, 100%, 40%);">- write32(mmio + CPU_VGACNTRL, 0x0000298e | VGA_DISP_DISABLE);</span><br><span style="color: hsl(0, 100%, 40%);">- write32(mmio + 0x0007019c, 0x00000000);</span><br><span style="color: hsl(0, 100%, 40%);">- write32(mmio + 0x0007119c, 0x00000000);</span><br><span style="color: hsl(0, 100%, 40%);">- write32(mmio + 0x000fc008, 0x2c010000);</span><br><span style="color: hsl(0, 100%, 40%);">- write32(mmio + 0x000fc020, 0x2c010000);</span><br><span style="color: hsl(0, 100%, 40%);">- write32(mmio + 0x000fc038, 0x2c010000);</span><br><span style="color: hsl(0, 100%, 40%);">- write32(mmio + 0x000fc050, 0x2c010000);</span><br><span style="color: hsl(0, 100%, 40%);">- write32(mmio + 0x000fc408, 0x2c010000);</span><br><span style="color: hsl(0, 100%, 40%);">- write32(mmio + 0x000fc420, 0x2c010000);</span><br><span style="color: hsl(0, 100%, 40%);">- write32(mmio + 0x000fc438, 0x2c010000);</span><br><span style="color: hsl(0, 100%, 40%);">- write32(mmio + 0x000fc450, 0x2c010000);</span><br><span style="color: hsl(0, 100%, 40%);">- vga_gr_write(0x18, 0);</span><br><span style="color: hsl(0, 100%, 40%);">- write32(mmio + 0x00042004, 0x02000000);</span><br><span style="color: hsl(0, 100%, 40%);">- write32(mmio + 0x000fd034, 0x8421ffe0);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Setup GTT. */</span><br><span style="color: hsl(0, 100%, 40%);">- for (i = 0; i < 0x2000; i++)</span><br><span style="color: hsl(0, 100%, 40%);">- {</span><br><span style="color: hsl(0, 100%, 40%);">- outl((i << 2) | 1, piobase);</span><br><span style="color: hsl(0, 100%, 40%);">- outl(physbase + (i << 12) + 1, piobase + 4);</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- vga_misc_write(0x67);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- const u8 cr[] = { 0x5f, 0x4f, 0x50, 0x82, 0x55, 0x81, 0xbf, 0x1f,</span><br><span style="color: hsl(0, 100%, 40%);">- 0x00, 0x4f, 0x0d, 0x0e, 0x00, 0x00, 0x00, 0x00,</span><br><span style="color: hsl(0, 100%, 40%);">- 0x9c, 0x8e, 0x8f, 0x28, 0x1f, 0x96, 0xb9, 0xa3,</span><br><span style="color: hsl(0, 100%, 40%);">- 0xff</span><br><span style="color: hsl(0, 100%, 40%);">- };</span><br><span style="color: hsl(0, 100%, 40%);">- vga_cr_write(0x11, 0);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- for (i = 0; i <= 0x18; i++)</span><br><span style="color: hsl(0, 100%, 40%);">- vga_cr_write(i, cr[i]);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- power_port(mmio);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- intel_gmbus_read_edid(mmio + PCH_GMBUS0, GMBUS_PORT_PANEL, 0x50,</span><br><span style="color: hsl(0, 100%, 40%);">- edid_data, sizeof(edid_data));</span><br><span style="color: hsl(0, 100%, 40%);">- intel_gmbus_stop(mmio + PCH_GMBUS0);</span><br><span style="color: hsl(0, 100%, 40%);">- decode_edid(edid_data,</span><br><span style="color: hsl(0, 100%, 40%);">- sizeof(edid_data), &edid);</span><br><span style="color: hsl(0, 100%, 40%);">- mode = &edid.mode;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Disable screen memory to prevent garbage from appearing. */</span><br><span style="color: hsl(0, 100%, 40%);">- vga_sr_write(1, vga_sr_read(1) | 0x20);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- hactive = edid.x_resolution;</span><br><span style="color: hsl(0, 100%, 40%);">- vactive = edid.y_resolution;</span><br><span style="color: hsl(0, 100%, 40%);">- right_border = mode->hborder;</span><br><span style="color: hsl(0, 100%, 40%);">- bottom_border = mode->vborder;</span><br><span style="color: hsl(0, 100%, 40%);">- hpolarity = (mode->phsync == '-');</span><br><span style="color: hsl(0, 100%, 40%);">- vpolarity = (mode->pvsync == '-');</span><br><span style="color: hsl(0, 100%, 40%);">- vsync = mode->vspw;</span><br><span style="color: hsl(0, 100%, 40%);">- hsync = mode->hspw;</span><br><span style="color: hsl(0, 100%, 40%);">- vblank = mode->vbl;</span><br><span style="color: hsl(0, 100%, 40%);">- hblank = mode->hbl;</span><br><span style="color: hsl(0, 100%, 40%);">- hfront_porch = mode->hso;</span><br><span style="color: hsl(0, 100%, 40%);">- vfront_porch = mode->vso;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- target_frequency = mode->lvds_dual_channel ? mode->pixel_clock</span><br><span style="color: hsl(0, 100%, 40%);">- : (2 * mode->pixel_clock);</span><br><span style="color: hsl(0, 100%, 40%);">- vga_textmode_init();</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- if (IS_ENABLED(CONFIG_LINEAR_FRAMEBUFFER)) {</span><br><span style="color: hsl(0, 100%, 40%);">- vga_sr_write(1, 1);</span><br><span style="color: hsl(0, 100%, 40%);">- vga_sr_write(0x2, 0xf);</span><br><span style="color: hsl(0, 100%, 40%);">- vga_sr_write(0x3, 0x0);</span><br><span style="color: hsl(0, 100%, 40%);">- vga_sr_write(0x4, 0xe);</span><br><span style="color: hsl(0, 100%, 40%);">- vga_gr_write(0, 0x0);</span><br><span style="color: hsl(0, 100%, 40%);">- vga_gr_write(1, 0x0);</span><br><span style="color: hsl(0, 100%, 40%);">- vga_gr_write(2, 0x0);</span><br><span style="color: hsl(0, 100%, 40%);">- vga_gr_write(3, 0x0);</span><br><span style="color: hsl(0, 100%, 40%);">- vga_gr_write(4, 0x0);</span><br><span style="color: hsl(0, 100%, 40%);">- vga_gr_write(5, 0x0);</span><br><span style="color: hsl(0, 100%, 40%);">- vga_gr_write(6, 0x5);</span><br><span style="color: hsl(0, 100%, 40%);">- vga_gr_write(7, 0xf);</span><br><span style="color: hsl(0, 100%, 40%);">- vga_gr_write(0x10, 0x1);</span><br><span style="color: hsl(0, 100%, 40%);">- vga_gr_write(0x11, 0);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- edid.bytes_per_line = (edid.bytes_per_line + 63) & ~63;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- write32(mmio + DSPCNTR(0), DISPPLANE_BGRX888);</span><br><span style="color: hsl(0, 100%, 40%);">- write32(mmio + DSPADDR(0), 0);</span><br><span style="color: hsl(0, 100%, 40%);">- write32(mmio + DSPSTRIDE(0), edid.bytes_per_line);</span><br><span style="color: hsl(0, 100%, 40%);">- write32(mmio + DSPSURF(0), 0);</span><br><span style="color: hsl(0, 100%, 40%);">- for (i = 0; i < 0x100; i++)</span><br><span style="color: hsl(0, 100%, 40%);">- write32(mmio + LGC_PALETTE(0) + 4 * i, i * 0x010101);</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Find suitable divisors. */</span><br><span style="color: hsl(0, 100%, 40%);">- for (candp1 = 1; candp1 <= 8; candp1++) {</span><br><span style="color: hsl(0, 100%, 40%);">- for (candn = 5; candn <= 10; candn++) {</span><br><span style="color: hsl(0, 100%, 40%);">- u32 cur_frequency;</span><br><span style="color: hsl(0, 100%, 40%);">- u32 m; /* 77 - 131. */</span><br><span style="color: hsl(0, 100%, 40%);">- u32 denom; /* 35 - 560. */</span><br><span style="color: hsl(0, 100%, 40%);">- u32 current_delta;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- denom = candn * candp1 * 7;</span><br><span style="color: hsl(0, 100%, 40%);">- /* Doesn't overflow for up to</span><br><span style="color: hsl(0, 100%, 40%);">- 5000000 kHz = 5 GHz. */</span><br><span style="color: hsl(0, 100%, 40%);">- m = (target_frequency * denom + 60000) / 120000;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- if (m < 77 || m > 131)</span><br><span style="color: hsl(0, 100%, 40%);">- continue;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- cur_frequency = (120000 * m) / denom;</span><br><span style="color: hsl(0, 100%, 40%);">- if (target_frequency > cur_frequency)</span><br><span style="color: hsl(0, 100%, 40%);">- current_delta = target_frequency - cur_frequency;</span><br><span style="color: hsl(0, 100%, 40%);">- else</span><br><span style="color: hsl(0, 100%, 40%);">- current_delta = cur_frequency - target_frequency;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- if (best_delta > current_delta) {</span><br><span style="color: hsl(0, 100%, 40%);">- best_delta = current_delta;</span><br><span style="color: hsl(0, 100%, 40%);">- pixel_n = candn;</span><br><span style="color: hsl(0, 100%, 40%);">- pixel_p1 = candp1;</span><br><span style="color: hsl(0, 100%, 40%);">- pixel_m2 = ((m + 3) % 5) + 7;</span><br><span style="color: hsl(0, 100%, 40%);">- pixel_m1 = (m - pixel_m2) / 5;</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- if (best_delta == 0xffffffff) {</span><br><span style="color: hsl(0, 100%, 40%);">- printk (BIOS_ERR, "Couldn't find GFX clock divisors\n");</span><br><span style="color: hsl(0, 100%, 40%);">- return;</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- link_m1 = ((uint64_t)link_n1 * mode->pixel_clock) / link_frequency;</span><br><span style="color: hsl(0, 100%, 40%);">- data_m1 = ((uint64_t)data_n1 * 18 * mode->pixel_clock)</span><br><span style="color: hsl(0, 100%, 40%);">- / (link_frequency * 8 * 4);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_INFO, "bringing up panel at resolution %d x %d\n",</span><br><span style="color: hsl(0, 100%, 40%);">- hactive, vactive);</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, "Borders %d x %d\n",</span><br><span style="color: hsl(0, 100%, 40%);">- right_border, bottom_border);</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, "Blank %d x %d\n",</span><br><span style="color: hsl(0, 100%, 40%);">- hblank, vblank);</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, "Sync %d x %d\n",</span><br><span style="color: hsl(0, 100%, 40%);">- hsync, vsync);</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, "Front porch %d x %d\n",</span><br><span style="color: hsl(0, 100%, 40%);">- hfront_porch, vfront_porch);</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, (info->gfx.use_spread_spectrum_clock</span><br><span style="color: hsl(0, 100%, 40%);">- ? "Spread spectrum clock\n" : "DREF clock\n"));</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG,</span><br><span style="color: hsl(0, 100%, 40%);">- mode->lvds_dual_channel ? "Dual channel\n" : "Single channel\n");</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, "Polarities %d, %d\n",</span><br><span style="color: hsl(0, 100%, 40%);">- hpolarity, vpolarity);</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, "Data M1=%d, N1=%d\n",</span><br><span style="color: hsl(0, 100%, 40%);">- data_m1, data_n1);</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, "Link frequency %d kHz\n",</span><br><span style="color: hsl(0, 100%, 40%);">- link_frequency);</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, "Link M1=%d, N1=%d\n",</span><br><span style="color: hsl(0, 100%, 40%);">- link_m1, link_n1);</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, "Pixel N=%d, M1=%d, M2=%d, P1=%d\n",</span><br><span style="color: hsl(0, 100%, 40%);">- pixel_n, pixel_m1, pixel_m2, pixel_p1);</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, "Pixel clock %d kHz\n",</span><br><span style="color: hsl(0, 100%, 40%);">- 120000 * (5 * pixel_m1 + pixel_m2) / pixel_n</span><br><span style="color: hsl(0, 100%, 40%);">- / (pixel_p1 * 7));</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- write32(mmio + PCH_LVDS,</span><br><span style="color: hsl(0, 100%, 40%);">- (hpolarity << 20) | (vpolarity << 21)</span><br><span style="color: hsl(0, 100%, 40%);">- | (mode->lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL</span><br><span style="color: hsl(0, 100%, 40%);">- | LVDS_CLOCK_BOTH_POWERUP_ALL : 0)</span><br><span style="color: hsl(0, 100%, 40%);">- | LVDS_BORDER_ENABLE | LVDS_CLOCK_A_POWERUP_ALL</span><br><span style="color: hsl(0, 100%, 40%);">- | LVDS_DETECTED);</span><br><span style="color: hsl(0, 100%, 40%);">- write32(mmio + BLC_PWM_CPU_CTL2, (1 << 31));</span><br><span style="color: hsl(0, 100%, 40%);">- write32(mmio + PCH_DREF_CONTROL, (info->gfx.use_spread_spectrum_clock</span><br><span style="color: hsl(0, 100%, 40%);">- ? 0x1002 : 0x400));</span><br><span style="color: hsl(0, 100%, 40%);">- mdelay(1);</span><br><span style="color: hsl(0, 100%, 40%);">- write32(mmio + PCH_PP_CONTROL, PANEL_UNLOCK_REGS</span><br><span style="color: hsl(0, 100%, 40%);">- | (read32(mmio + PCH_PP_CONTROL) & ~PANEL_UNLOCK_MASK));</span><br><span style="color: hsl(0, 100%, 40%);">- write32(mmio + _PCH_FP0(0),</span><br><span style="color: hsl(0, 100%, 40%);">- ((pixel_n - 2) << 16)</span><br><span style="color: hsl(0, 100%, 40%);">- | ((pixel_m1 - 2) << 8) | pixel_m2);</span><br><span style="color: hsl(0, 100%, 40%);">- write32(mmio + _PCH_DPLL(0),</span><br><span style="color: hsl(0, 100%, 40%);">- DPLL_VCO_ENABLE | DPLLB_MODE_LVDS</span><br><span style="color: hsl(0, 100%, 40%);">- | (mode->lvds_dual_channel ? DPLLB_LVDS_P2_CLOCK_DIV_7</span><br><span style="color: hsl(0, 100%, 40%);">- : DPLLB_LVDS_P2_CLOCK_DIV_14)</span><br><span style="color: hsl(0, 100%, 40%);">- | (0x10000 << (pixel_p1 - 1))</span><br><span style="color: hsl(0, 100%, 40%);">- | ((info->gfx.use_spread_spectrum_clock ? 3 : 0) << 13)</span><br><span style="color: hsl(0, 100%, 40%);">- | (0x1 << (pixel_p1 - 1)));</span><br><span style="color: hsl(0, 100%, 40%);">- mdelay(1);</span><br><span style="color: hsl(0, 100%, 40%);">- write32(mmio + _PCH_DPLL(0),</span><br><span style="color: hsl(0, 100%, 40%);">- DPLL_VCO_ENABLE | DPLLB_MODE_LVDS</span><br><span style="color: hsl(0, 100%, 40%);">- | (mode->lvds_dual_channel ? DPLLB_LVDS_P2_CLOCK_DIV_7</span><br><span style="color: hsl(0, 100%, 40%);">- : DPLLB_LVDS_P2_CLOCK_DIV_14)</span><br><span style="color: hsl(0, 100%, 40%);">- | (0x10000 << (pixel_p1 - 1))</span><br><span style="color: hsl(0, 100%, 40%);">- | ((info->gfx.use_spread_spectrum_clock ? 3 : 0) << 13)</span><br><span style="color: hsl(0, 100%, 40%);">- | (0x1 << (pixel_p1 - 1)));</span><br><span style="color: hsl(0, 100%, 40%);">- /* Re-lock the registers. */</span><br><span style="color: hsl(0, 100%, 40%);">- write32(mmio + PCH_PP_CONTROL,</span><br><span style="color: hsl(0, 100%, 40%);">- (read32(mmio + PCH_PP_CONTROL) & ~PANEL_UNLOCK_MASK));</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- write32(mmio + PCH_LVDS,</span><br><span style="color: hsl(0, 100%, 40%);">- (hpolarity << 20) | (vpolarity << 21)</span><br><span style="color: hsl(0, 100%, 40%);">- | (mode->lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL</span><br><span style="color: hsl(0, 100%, 40%);">- | LVDS_CLOCK_BOTH_POWERUP_ALL : 0)</span><br><span style="color: hsl(0, 100%, 40%);">- | LVDS_BORDER_ENABLE | LVDS_CLOCK_A_POWERUP_ALL</span><br><span style="color: hsl(0, 100%, 40%);">- | LVDS_DETECTED);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- write32(mmio + HTOTAL(0),</span><br><span style="color: hsl(0, 100%, 40%);">- ((hactive + right_border + hblank - 1) << 16)</span><br><span style="color: hsl(0, 100%, 40%);">- | (hactive - 1));</span><br><span style="color: hsl(0, 100%, 40%);">- write32(mmio + HBLANK(0),</span><br><span style="color: hsl(0, 100%, 40%);">- ((hactive + right_border + hblank - 1) << 16)</span><br><span style="color: hsl(0, 100%, 40%);">- | (hactive + right_border - 1));</span><br><span style="color: hsl(0, 100%, 40%);">- write32(mmio + HSYNC(0),</span><br><span style="color: hsl(0, 100%, 40%);">- ((hactive + right_border + hfront_porch + hsync - 1) << 16)</span><br><span style="color: hsl(0, 100%, 40%);">- | (hactive + right_border + hfront_porch - 1));</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- write32(mmio + VTOTAL(0), ((vactive + bottom_border + vblank - 1) << 16)</span><br><span style="color: hsl(0, 100%, 40%);">- | (vactive - 1));</span><br><span style="color: hsl(0, 100%, 40%);">- write32(mmio + VBLANK(0), ((vactive + bottom_border + vblank - 1) << 16)</span><br><span style="color: hsl(0, 100%, 40%);">- | (vactive + bottom_border - 1));</span><br><span style="color: hsl(0, 100%, 40%);">- write32(mmio + VSYNC(0),</span><br><span style="color: hsl(0, 100%, 40%);">- (vactive + bottom_border + vfront_porch + vsync - 1)</span><br><span style="color: hsl(0, 100%, 40%);">- | (vactive + bottom_border + vfront_porch - 1));</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- write32(mmio + PIPECONF(0), PIPECONF_DISABLE);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- write32(mmio + PF_WIN_POS(0), 0);</span><br><span style="color: hsl(0, 100%, 40%);">- if (IS_ENABLED(CONFIG_LINEAR_FRAMEBUFFER)) {</span><br><span style="color: hsl(0, 100%, 40%);">- write32(mmio + PIPESRC(0), (hactive - 1) << 16 | (vactive - 1));</span><br><span style="color: hsl(0, 100%, 40%);">- write32(mmio + PF_CTL(0), 0);</span><br><span style="color: hsl(0, 100%, 40%);">- write32(mmio + PF_WIN_SZ(0), 0);</span><br><span style="color: hsl(0, 100%, 40%);">- } else {</span><br><span style="color: hsl(0, 100%, 40%);">- write32(mmio + PIPESRC(0), (639 << 16) | 399);</span><br><span style="color: hsl(0, 100%, 40%);">- write32(mmio + PF_CTL(0), PF_ENABLE | PF_FILTER_MED_3x3);</span><br><span style="color: hsl(0, 100%, 40%);">- write32(mmio + PF_WIN_SZ(0), vactive | (hactive << 16));</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- mdelay(1);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- write32(mmio + PIPE_DATA_M1(0), 0x7e000000 | data_m1);</span><br><span style="color: hsl(0, 100%, 40%);">- write32(mmio + PIPE_DATA_N1(0), data_n1);</span><br><span style="color: hsl(0, 100%, 40%);">- write32(mmio + PIPE_LINK_M1(0), link_m1);</span><br><span style="color: hsl(0, 100%, 40%);">- write32(mmio + PIPE_LINK_N1(0), link_n1);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- write32(mmio + 0x000f000c, 0x00002040);</span><br><span style="color: hsl(0, 100%, 40%);">- mdelay(1);</span><br><span style="color: hsl(0, 100%, 40%);">- write32(mmio + 0x000f000c, 0x00002050);</span><br><span style="color: hsl(0, 100%, 40%);">- write32(mmio + 0x00060100, 0x00044000);</span><br><span style="color: hsl(0, 100%, 40%);">- mdelay(1);</span><br><span style="color: hsl(0, 100%, 40%);">- write32(mmio + PIPECONF(0), PIPECONF_BPP_6);</span><br><span style="color: hsl(0, 100%, 40%);">- write32(mmio + 0x000f0008, 0x00000040);</span><br><span style="color: hsl(0, 100%, 40%);">- write32(mmio + 0x000f000c, 0x00022050);</span><br><span style="color: hsl(0, 100%, 40%);">- write32(mmio + PIPECONF(0), PIPECONF_BPP_6 | PIPECONF_DITHER_EN);</span><br><span style="color: hsl(0, 100%, 40%);">- write32(mmio + PIPECONF(0), PIPECONF_ENABLE | PIPECONF_BPP_6 | PIPECONF_DITHER_EN);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- if (IS_ENABLED(CONFIG_LINEAR_FRAMEBUFFER))</span><br><span style="color: hsl(0, 100%, 40%);">- write32(mmio + CPU_VGACNTRL, 0x20298e | VGA_DISP_DISABLE);</span><br><span style="color: hsl(0, 100%, 40%);">- else</span><br><span style="color: hsl(0, 100%, 40%);">- write32(mmio + CPU_VGACNTRL, 0x20298e);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- train_link(mmio);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- if (IS_ENABLED(CONFIG_LINEAR_FRAMEBUFFER)) {</span><br><span style="color: hsl(0, 100%, 40%);">- write32(mmio + DSPCNTR(0),</span><br><span style="color: hsl(0, 100%, 40%);">- DISPLAY_PLANE_ENABLE | DISPPLANE_BGRX888);</span><br><span style="color: hsl(0, 100%, 40%);">- mdelay(1);</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- write32(mmio + TRANS_HTOTAL(0),</span><br><span style="color: hsl(0, 100%, 40%);">- ((hactive + right_border + hblank - 1) << 16)</span><br><span style="color: hsl(0, 100%, 40%);">- | (hactive - 1));</span><br><span style="color: hsl(0, 100%, 40%);">- write32(mmio + TRANS_HBLANK(0),</span><br><span style="color: hsl(0, 100%, 40%);">- ((hactive + right_border + hblank - 1) << 16)</span><br><span style="color: hsl(0, 100%, 40%);">- | (hactive + right_border - 1));</span><br><span style="color: hsl(0, 100%, 40%);">- write32(mmio + TRANS_HSYNC(0),</span><br><span style="color: hsl(0, 100%, 40%);">- ((hactive + right_border + hfront_porch + hsync - 1) << 16)</span><br><span style="color: hsl(0, 100%, 40%);">- | (hactive + right_border + hfront_porch - 1));</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- write32(mmio + TRANS_VTOTAL(0),</span><br><span style="color: hsl(0, 100%, 40%);">- ((vactive + bottom_border + vblank - 1) << 16)</span><br><span style="color: hsl(0, 100%, 40%);">- | (vactive - 1));</span><br><span style="color: hsl(0, 100%, 40%);">- write32(mmio + TRANS_VBLANK(0),</span><br><span style="color: hsl(0, 100%, 40%);">- ((vactive + bottom_border + vblank - 1) << 16)</span><br><span style="color: hsl(0, 100%, 40%);">- | (vactive + bottom_border - 1));</span><br><span style="color: hsl(0, 100%, 40%);">- write32(mmio + TRANS_VSYNC(0),</span><br><span style="color: hsl(0, 100%, 40%);">- (vactive + bottom_border + vfront_porch + vsync - 1)</span><br><span style="color: hsl(0, 100%, 40%);">- | (vactive + bottom_border + vfront_porch - 1));</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- write32(mmio + 0x00060100, 0xb01c4000);</span><br><span style="color: hsl(0, 100%, 40%);">- write32(mmio + 0x000f000c, 0xb01a2050);</span><br><span style="color: hsl(0, 100%, 40%);">- mdelay(1);</span><br><span style="color: hsl(0, 100%, 40%);">- write32(mmio + TRANSCONF(0), TRANS_ENABLE | TRANS_6BPC |</span><br><span style="color: hsl(0, 100%, 40%);">- (IS_ENABLED(CONFIG_LINEAR_FRAMEBUFFER) ? TRANS_STATE_MASK : 0));</span><br><span style="color: hsl(0, 100%, 40%);">- write32(mmio + PCH_LVDS,</span><br><span style="color: hsl(0, 100%, 40%);">- LVDS_PORT_ENABLE</span><br><span style="color: hsl(0, 100%, 40%);">- | (hpolarity << 20) | (vpolarity << 21)</span><br><span style="color: hsl(0, 100%, 40%);">- | (mode->lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL</span><br><span style="color: hsl(0, 100%, 40%);">- | LVDS_CLOCK_BOTH_POWERUP_ALL : 0)</span><br><span style="color: hsl(0, 100%, 40%);">- | LVDS_BORDER_ENABLE | LVDS_CLOCK_A_POWERUP_ALL</span><br><span style="color: hsl(0, 100%, 40%);">- | LVDS_DETECTED);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- write32(mmio + PCH_PP_CONTROL, PANEL_UNLOCK_REGS | PANEL_POWER_OFF);</span><br><span style="color: hsl(0, 100%, 40%);">- write32(mmio + PCH_PP_CONTROL, PANEL_UNLOCK_REGS | PANEL_POWER_RESET);</span><br><span style="color: hsl(0, 100%, 40%);">- mdelay(1);</span><br><span style="color: hsl(0, 100%, 40%);">- write32(mmio + PCH_PP_CONTROL, PANEL_UNLOCK_REGS</span><br><span style="color: hsl(0, 100%, 40%);">- | PANEL_POWER_ON | PANEL_POWER_RESET);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- printk (BIOS_DEBUG, "waiting for panel powerup\n");</span><br><span style="color: hsl(0, 100%, 40%);">- while (1) {</span><br><span style="color: hsl(0, 100%, 40%);">- u32 reg32;</span><br><span style="color: hsl(0, 100%, 40%);">- reg32 = read32(mmio + PCH_PP_STATUS);</span><br><span style="color: hsl(0, 100%, 40%);">- if (((reg32 >> 28) & 3) == 0)</span><br><span style="color: hsl(0, 100%, 40%);">- break;</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">- printk (BIOS_DEBUG, "panel powered up\n");</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- write32(mmio + PCH_PP_CONTROL, PANEL_POWER_ON | PANEL_POWER_RESET);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Enable screen memory. */</span><br><span style="color: hsl(0, 100%, 40%);">- vga_sr_write(1, vga_sr_read(1) & ~0x20);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Clear interrupts. */</span><br><span style="color: hsl(0, 100%, 40%);">- write32(mmio + DEIIR, 0xffffffff);</span><br><span style="color: hsl(0, 100%, 40%);">- write32(mmio + SDEIIR, 0xffffffff);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Doesn't change any hw behaviour but vga oprom expects it there. */</span><br><span style="color: hsl(0, 100%, 40%);">- write32(mmio + 0x0004f040, 0x01000008);</span><br><span style="color: hsl(0, 100%, 40%);">- write32(mmio + 0x0004f04c, 0x7f7f0000);</span><br><span style="color: hsl(0, 100%, 40%);">- write32(mmio + 0x0004f054, 0x0000020d);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- if (IS_ENABLED(CONFIG_LINEAR_FRAMEBUFFER)) {</span><br><span style="color: hsl(0, 100%, 40%);">- memset((void *)lfb, 0,</span><br><span style="color: hsl(0, 100%, 40%);">- edid.x_resolution * edid.y_resolution * 4);</span><br><span style="color: hsl(0, 100%, 40%);">- set_vbe_mode_info_valid(&edid, lfb);</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span> /* Enable SCI to ACPI _GPE._L06 */</span><br><span> static void gma_enable_swsci(void)</span><br><span> {</span><br><span>@@ -1037,32 +602,12 @@</span><br><span> /* Init graphics power management */</span><br><span> gma_pm_init_pre_vbios(dev);</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- if (IS_ENABLED(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT) ||</span><br><span style="color: hsl(0, 100%, 40%);">- IS_ENABLED(CONFIG_MAINBOARD_USE_LIBGFXINIT)) {</span><br><span style="color: hsl(0, 100%, 40%);">- u32 physbase;</span><br><span style="color: hsl(120, 100%, 40%);">+ if (IS_ENABLED(CONFIG_MAINBOARD_USE_LIBGFXINIT)) {</span><br><span> struct northbridge_intel_nehalem_config *conf = dev->chip_info;</span><br><span style="color: hsl(0, 100%, 40%);">- struct resource *lfb_res;</span><br><span style="color: hsl(0, 100%, 40%);">- struct resource *pio_res;</span><br><span style="color: hsl(120, 100%, 40%);">+ int lightup_ok;</span><br><span style="color: hsl(120, 100%, 40%);">+ printk(BIOS_SPEW, "Initializing VGA without OPROM.");</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- lfb_res = find_resource(dev, PCI_BASE_ADDRESS_2);</span><br><span style="color: hsl(0, 100%, 40%);">- pio_res = find_resource(dev, PCI_BASE_ADDRESS_4);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- physbase = pci_read_config32(dev, 0x5c) & ~0xf;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- if (gtt_res && gtt_res->base && physbase &&</span><br><span style="color: hsl(0, 100%, 40%);">- pio_res && pio_res->base && lfb_res && lfb_res->base) {</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_SPEW,</span><br><span style="color: hsl(0, 100%, 40%);">- "Initializing VGA without OPROM. MMIO 0x%llx\n",</span><br><span style="color: hsl(0, 100%, 40%);">- gtt_res->base);</span><br><span style="color: hsl(0, 100%, 40%);">- if (IS_ENABLED(CONFIG_MAINBOARD_USE_LIBGFXINIT)) {</span><br><span style="color: hsl(0, 100%, 40%);">- int lightup_ok;</span><br><span style="color: hsl(0, 100%, 40%);">- gma_gfxinit(&lightup_ok);</span><br><span style="color: hsl(0, 100%, 40%);">- } else {</span><br><span style="color: hsl(0, 100%, 40%);">- intel_gma_init(conf, res2mmio(gtt_res, 0, 0),</span><br><span style="color: hsl(0, 100%, 40%);">- physbase, pio_res->base, lfb_res->base);</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(120, 100%, 40%);">+ gma_gfxinit(&lightup_ok);</span><br><span> /* Linux relies on VBT for panel info. */</span><br><span> generate_fake_intel_oprom(&conf->gfx, dev,</span><br><span> "$VBT IRONLAKE-MOBILE");</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/27515">change 27515</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/27515"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I9228fa7eadfe2a827c1f4de9d6710b60d3f1b121 </div>
<div style="display:none"> Gerrit-Change-Number: 27515 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Arthur Heymans <arthur@aheymans.xyz> </div>