<p>Tristan Hsieh has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/27498">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">mediatek/mt8183: Add SPI support<br><br>This patch implements SOC-specific code of mt8183 and link the common<br>code to support SPI bus.<br><br>BUG=b:80501386<br>BRANCH=none<br>TEST=Boots correctly on Kukui<br><br>Signed-off-by: mengqi.zhang <mengqi.zhang@mediatek.com><br>Change-Id: I544e850299c74861313c2425721479fe5b91639e<br>---<br>M src/soc/mediatek/mt8183/Makefile.inc<br>M src/soc/mediatek/mt8183/include/soc/addressmap.h<br>M src/soc/mediatek/mt8183/include/soc/pll.h<br>A src/soc/mediatek/mt8183/include/soc/spi.h<br>M src/soc/mediatek/mt8183/spi.c<br>5 files changed, 176 insertions(+), 8 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/27498/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/soc/mediatek/mt8183/Makefile.inc b/src/soc/mediatek/mt8183/Makefile.inc</span><br><span>index 1ae534f..ca59d34 100644</span><br><span>--- a/src/soc/mediatek/mt8183/Makefile.inc</span><br><span>+++ b/src/soc/mediatek/mt8183/Makefile.inc</span><br><span>@@ -4,7 +4,7 @@</span><br><span> bootblock-y += ../common/gpio.c gpio.c</span><br><span> bootblock-y += ../common/mmu_operations.c mmu_operations.c</span><br><span> bootblock-y += ../common/pll.c pll.c</span><br><span style="color: hsl(0, 100%, 40%);">-bootblock-$(CONFIG_SPI_FLASH) += spi.c</span><br><span style="color: hsl(120, 100%, 40%);">+bootblock-$(CONFIG_SPI_FLASH) += ../common/spi.c spi.c</span><br><span> bootblock-y += ../common/timer.c</span><br><span> ifeq ($(CONFIG_BOOTBLOCK_CONSOLE),y)</span><br><span> bootblock-$(CONFIG_DRIVERS_UART) += ../common/uart.c</span><br><span>@@ -12,7 +12,7 @@</span><br><span> bootblock-y += ../common/wdt.c</span><br><span> </span><br><span> verstage-y += ../common/gpio.c gpio.c</span><br><span style="color: hsl(0, 100%, 40%);">-verstage-$(CONFIG_SPI_FLASH) += spi.c</span><br><span style="color: hsl(120, 100%, 40%);">+verstage-$(CONFIG_SPI_FLASH) += ../common/spi.c spi.c</span><br><span> verstage-y += ../common/timer.c</span><br><span> verstage-$(CONFIG_DRIVERS_UART) += ../common/uart.c</span><br><span> verstage-y += ../common/wdt.c</span><br><span>@@ -20,7 +20,7 @@</span><br><span> romstage-y += emi.c</span><br><span> romstage-y += ../common/gpio.c gpio.c</span><br><span> romstage-y += ../common/mmu_operations.c mmu_operations.c</span><br><span style="color: hsl(0, 100%, 40%);">-romstage-$(CONFIG_SPI_FLASH) += spi.c</span><br><span style="color: hsl(120, 100%, 40%);">+romstage-$(CONFIG_SPI_FLASH) += ../common/spi.c spi.c</span><br><span> romstage-y += ../common/timer.c</span><br><span> romstage-$(CONFIG_DRIVERS_UART) += ../common/uart.c</span><br><span> romstage-y += ../common/wdt.c</span><br><span>@@ -30,7 +30,7 @@</span><br><span> ramstage-y += ../common/mmu_operations.c mmu_operations.c</span><br><span> ramstage-y += ../common/mtcmos.c mtcmos.c</span><br><span> ramstage-y += soc.c</span><br><span style="color: hsl(0, 100%, 40%);">-ramstage-$(CONFIG_SPI_FLASH) += spi.c</span><br><span style="color: hsl(120, 100%, 40%);">+ramstage-$(CONFIG_SPI_FLASH) += ../common/spi.c spi.c</span><br><span> ramstage-y += ../common/timer.c</span><br><span> ramstage-$(CONFIG_DRIVERS_UART) += ../common/uart.c</span><br><span> ramstage-y += ../common/wdt.c</span><br><span>diff --git a/src/soc/mediatek/mt8183/include/soc/addressmap.h b/src/soc/mediatek/mt8183/include/soc/addressmap.h</span><br><span>index d6f54cf..de7eb1f 100644</span><br><span>--- a/src/soc/mediatek/mt8183/include/soc/addressmap.h</span><br><span>+++ b/src/soc/mediatek/mt8183/include/soc/addressmap.h</span><br><span>@@ -31,6 +31,12 @@</span><br><span> GPT_BASE = IO_PHYS + 0x00008000,</span><br><span> APMIXED_BASE = IO_PHYS + 0x0000C000,</span><br><span> UART0_BASE = IO_PHYS + 0x01002000,</span><br><span style="color: hsl(120, 100%, 40%);">+ SPI0_BASE = IO_PHYS + 0x0100A000,</span><br><span style="color: hsl(120, 100%, 40%);">+ SPI1_BASE = IO_PHYS + 0x01010000,</span><br><span style="color: hsl(120, 100%, 40%);">+ SPI2_BASE = IO_PHYS + 0x01012000,</span><br><span style="color: hsl(120, 100%, 40%);">+ SPI3_BASE = IO_PHYS + 0x01013000,</span><br><span style="color: hsl(120, 100%, 40%);">+ SPI4_BASE = IO_PHYS + 0x01014000,</span><br><span style="color: hsl(120, 100%, 40%);">+ SPI5_BASE = IO_PHYS + 0x01015000,</span><br><span> IOCFG_RT_BASE = IO_PHYS + 0x01C50000,</span><br><span> IOCFG_RM_BASE = IO_PHYS + 0x01D20000,</span><br><span> IOCFG_RB_BASE = IO_PHYS + 0x01D30000,</span><br><span>diff --git a/src/soc/mediatek/mt8183/include/soc/pll.h b/src/soc/mediatek/mt8183/include/soc/pll.h</span><br><span>index d1ceded..8c0d4e3 100644</span><br><span>--- a/src/soc/mediatek/mt8183/include/soc/pll.h</span><br><span>+++ b/src/soc/mediatek/mt8183/include/soc/pll.h</span><br><span>@@ -260,6 +260,13 @@</span><br><span> /* top_div rate */</span><br><span> enum {</span><br><span> CLK26M_HZ = 26 * MHz,</span><br><span style="color: hsl(120, 100%, 40%);">+ MAINPLL_D5_HZ = MAINPLL_HZ / 5,</span><br><span style="color: hsl(120, 100%, 40%);">+ MAINPLL_D5_D2_HZ = MAINPLL_D5_HZ / 2,</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* top_mux rate */</span><br><span style="color: hsl(120, 100%, 40%);">+enum {</span><br><span style="color: hsl(120, 100%, 40%);">+ SPI_HZ = MAINPLL_D5_D2_HZ,</span><br><span> };</span><br><span> </span><br><span> #endif /* SOC_MEDIATEK_MT8183_PLL_H */</span><br><span>diff --git a/src/soc/mediatek/mt8183/include/soc/spi.h b/src/soc/mediatek/mt8183/include/soc/spi.h</span><br><span>new file mode 100644</span><br><span>index 0000000..66f46d1</span><br><span>--- /dev/null</span><br><span>+++ b/src/soc/mediatek/mt8183/include/soc/spi.h</span><br><span>@@ -0,0 +1,55 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright 2018 MediaTek Inc.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef MTK_MT8183_SPI_H</span><br><span style="color: hsl(120, 100%, 40%);">+#define MTK_MT8183_SPI_H</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/spi_common.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define SPI_BUS_NUMBER 6</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* SPI peripheral register map. */</span><br><span style="color: hsl(120, 100%, 40%);">+typedef struct mtk_spi_regs {</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t spi_cfg0_reg;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t spi_cfg1_reg;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t spi_tx_src_reg;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t spi_rx_dst_reg;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t spi_tx_data_reg;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t spi_rx_data_reg;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t spi_cmd_reg;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t spi_status0_reg;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t spi_status1_reg;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t spi_pad_macro_sel_reg;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t spi_cfg2_reg;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t spi_tx_src_64_reg;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t spi_rx_dst_64_reg;</span><br><span style="color: hsl(120, 100%, 40%);">+} mtk_spi_regs;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(mtk_spi_regs, spi_pad_macro_sel_reg, 0x24);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* SPI_CFG0_REG */</span><br><span style="color: hsl(120, 100%, 40%);">+enum {</span><br><span style="color: hsl(120, 100%, 40%);">+ SPI_CFG0_CS_HOLD_SHIFT = 0,</span><br><span style="color: hsl(120, 100%, 40%);">+ SPI_CFG0_CS_SETUP_SHIFT = 16,</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/*SPI_CFG2_REG*/</span><br><span style="color: hsl(120, 100%, 40%);">+enum {</span><br><span style="color: hsl(120, 100%, 40%);">+ SPI_CFG2_SCK_LOW_SHIFT = 0,</span><br><span style="color: hsl(120, 100%, 40%);">+ SPI_CFG2_SCK_HIGH_SHIFT = 16,</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span>diff --git a/src/soc/mediatek/mt8183/spi.c b/src/soc/mediatek/mt8183/spi.c</span><br><span>index d85138c..9acc4d7 100644</span><br><span>--- a/src/soc/mediatek/mt8183/spi.c</span><br><span>+++ b/src/soc/mediatek/mt8183/spi.c</span><br><span>@@ -13,16 +13,116 @@</span><br><span> * GNU General Public License for more details.</span><br><span> */</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+#include <arch/io.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <assert.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <spi_flash.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/addressmap.h></span><br><span> #include <soc/flash_controller.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <spi-generic.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/gpio.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/spi.h></span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static const struct spi_ctrlr spi_flash_ctrlr = {</span><br><span style="color: hsl(0, 100%, 40%);">- .max_xfer_size = 65535,</span><br><span style="color: hsl(120, 100%, 40%);">+struct mtk_spi_bus spi_bus[SPI_BUS_NUMBER] = {</span><br><span style="color: hsl(120, 100%, 40%);">+ {</span><br><span style="color: hsl(120, 100%, 40%);">+ .regs = (void *)SPI0_BASE,</span><br><span style="color: hsl(120, 100%, 40%);">+ },</span><br><span style="color: hsl(120, 100%, 40%);">+ {</span><br><span style="color: hsl(120, 100%, 40%);">+ .regs = (void *)SPI1_BASE,</span><br><span style="color: hsl(120, 100%, 40%);">+ },</span><br><span style="color: hsl(120, 100%, 40%);">+ {</span><br><span style="color: hsl(120, 100%, 40%);">+ .regs = (void *)SPI2_BASE,</span><br><span style="color: hsl(120, 100%, 40%);">+ },</span><br><span style="color: hsl(120, 100%, 40%);">+ {</span><br><span style="color: hsl(120, 100%, 40%);">+ .regs = (void *)SPI3_BASE,</span><br><span style="color: hsl(120, 100%, 40%);">+ },</span><br><span style="color: hsl(120, 100%, 40%);">+ {</span><br><span style="color: hsl(120, 100%, 40%);">+ .regs = (void *)SPI4_BASE,</span><br><span style="color: hsl(120, 100%, 40%);">+ },</span><br><span style="color: hsl(120, 100%, 40%);">+ {</span><br><span style="color: hsl(120, 100%, 40%);">+ .regs = (void *)SPI5_BASE,</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span> };</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+void mtk_spi_set_gpio_pinmux(unsigned int bus,</span><br><span style="color: hsl(120, 100%, 40%);">+ enum spi_pad_mask pad_select)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ /* TODO: implement support for other pads when needed */</span><br><span style="color: hsl(120, 100%, 40%);">+ if (bus == 0) {</span><br><span style="color: hsl(120, 100%, 40%);">+ if (pad_select == SPI_PAD0_MASK) {</span><br><span style="color: hsl(120, 100%, 40%);">+ gpio_set_mode(PAD_SPI_MI, PAD_SPI_MI_FUNC_SPI0_MI);</span><br><span style="color: hsl(120, 100%, 40%);">+ gpio_set_mode(PAD_SPI_CSB, PAD_SPI_CSB_FUNC_SPI0_CSB);</span><br><span style="color: hsl(120, 100%, 40%);">+ gpio_set_mode(PAD_SPI_MO, PAD_SPI_MO_FUNC_SPI0_MO);</span><br><span style="color: hsl(120, 100%, 40%);">+ gpio_set_mode(PAD_SPI_CLK, PAD_SPI_CLK_FUNC_SPI0_CLK);</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ if (bus == 1) {</span><br><span style="color: hsl(120, 100%, 40%);">+ if (pad_select == SPI_PAD0_MASK) {</span><br><span style="color: hsl(120, 100%, 40%);">+ gpio_set_mode(PAD_SPI1_MI, PAD_SPI1_MI_FUNC_SPI1_A_MI);</span><br><span style="color: hsl(120, 100%, 40%);">+ gpio_set_mode(PAD_SPI1_CSB,</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_SPI1_CSB_FUNC_SPI1_A_CSB);</span><br><span style="color: hsl(120, 100%, 40%);">+ gpio_set_mode(PAD_SPI1_MO, PAD_SPI1_MO_FUNC_SPI1_A_MO);</span><br><span style="color: hsl(120, 100%, 40%);">+ gpio_set_mode(PAD_SPI1_CLK,</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_SPI1_CLK_FUNC_SPI1_A_CLK);</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ if (pad_select == SPI_PAD1_MASK) {</span><br><span style="color: hsl(120, 100%, 40%);">+ gpio_set_mode(PAD_EINT7, PAD_EINT7_FUNC_SPI1_B_MI);</span><br><span style="color: hsl(120, 100%, 40%);">+ gpio_set_mode(PAD_EINT8, PAD_EINT8_FUNC_SPI1_B_CSB);</span><br><span style="color: hsl(120, 100%, 40%);">+ gpio_set_mode(PAD_EINT9, PAD_EINT9_FUNC_SPI1_B_MO);</span><br><span style="color: hsl(120, 100%, 40%);">+ gpio_set_mode(PAD_EINT10, PAD_EINT10_FUNC_SPI1_B_CLK);</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ if (bus == 2) {</span><br><span style="color: hsl(120, 100%, 40%);">+ if (pad_select == SPI_PAD0_MASK) {</span><br><span style="color: hsl(120, 100%, 40%);">+ gpio_set_mode(PAD_KPCOL1, PAD_KPCOL1_FUNC_SPI2_MI);</span><br><span style="color: hsl(120, 100%, 40%);">+ gpio_set_mode(PAD_EINT0, PAD_EINT0_FUNC_SPI2_CSB);</span><br><span style="color: hsl(120, 100%, 40%);">+ gpio_set_mode(PAD_EINT1, PAD_EINT1_FUNC_SPI2_MO);</span><br><span style="color: hsl(120, 100%, 40%);">+ gpio_set_mode(PAD_EINT2, PAD_EINT2_FUNC_SPI2_CLK);</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ if (bus == 3) {</span><br><span style="color: hsl(120, 100%, 40%);">+ if (pad_select == SPI_PAD0_MASK) {</span><br><span style="color: hsl(120, 100%, 40%);">+ gpio_set_mode(PAD_DPI_D8, PAD_DPI_D8_FUNC_SPI3_MI);</span><br><span style="color: hsl(120, 100%, 40%);">+ gpio_set_mode(PAD_DPI_D9, PAD_DPI_D9_FUNC_SPI3_CSB);</span><br><span style="color: hsl(120, 100%, 40%);">+ gpio_set_mode(PAD_DPI_D10, PAD_DPI_D10_FUNC_SPI3_MO);</span><br><span style="color: hsl(120, 100%, 40%);">+ gpio_set_mode(PAD_DPI_D11, PAD_DPI_D11_FUNC_SPI3_CLK);</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ if (bus == 4) {</span><br><span style="color: hsl(120, 100%, 40%);">+ if (pad_select == SPI_PAD0_MASK) {</span><br><span style="color: hsl(120, 100%, 40%);">+ gpio_set_mode(PAD_DPI_D4, PAD_DPI_D4_FUNC_SPI4_MI);</span><br><span style="color: hsl(120, 100%, 40%);">+ gpio_set_mode(PAD_DPI_D5, PAD_DPI_D5_FUNC_SPI4_CSB);</span><br><span style="color: hsl(120, 100%, 40%);">+ gpio_set_mode(PAD_DPI_D6, PAD_DPI_D6_FUNC_SPI4_MO);</span><br><span style="color: hsl(120, 100%, 40%);">+ gpio_set_mode(PAD_DPI_D7, PAD_DPI_D7_FUNC_SPI4_CLK);</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ if (bus == 5) {</span><br><span style="color: hsl(120, 100%, 40%);">+ if (pad_select == SPI_PAD0_MASK) {</span><br><span style="color: hsl(120, 100%, 40%);">+ gpio_set_mode(PAD_DPI_D0, PAD_DPI_D0_FUNC_SPI5_MI);</span><br><span style="color: hsl(120, 100%, 40%);">+ gpio_set_mode(PAD_DPI_D1, PAD_DPI_D1_FUNC_SPI5_CSB);</span><br><span style="color: hsl(120, 100%, 40%);">+ gpio_set_mode(PAD_DPI_D2, PAD_DPI_D2_FUNC_SPI5_MO);</span><br><span style="color: hsl(120, 100%, 40%);">+ gpio_set_mode(PAD_DPI_D3, PAD_DPI_D3_FUNC_SPI5_CLK);</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+void mtk_spi_set_timing(struct mtk_spi_regs *regs, u32 sck_ticks, u32 cs_ticks)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ write32(®s->spi_cfg0_reg,</span><br><span style="color: hsl(120, 100%, 40%);">+ ((cs_ticks - 1) << SPI_CFG0_CS_HOLD_SHIFT) |</span><br><span style="color: hsl(120, 100%, 40%);">+ ((cs_ticks - 1) << SPI_CFG0_CS_SETUP_SHIFT));</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ write32(®s->spi_cfg2_reg,</span><br><span style="color: hsl(120, 100%, 40%);">+ ((sck_ticks - 1) << SPI_CFG2_SCK_HIGH_SHIFT) |</span><br><span style="color: hsl(120, 100%, 40%);">+ ((sck_ticks - 1) << SPI_CFG2_SCK_LOW_SHIFT));</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(®s->spi_cfg1_reg, SPI_CFG1_CS_IDLE_MASK,</span><br><span style="color: hsl(120, 100%, 40%);">+ ((cs_ticks - 1) << SPI_CFG1_CS_IDLE_SHIFT));</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> const struct spi_ctrlr_buses spi_ctrlr_bus_map[] = {</span><br><span> {</span><br><span style="color: hsl(0, 100%, 40%);">- .ctrlr = &spi_flash_ctrlr,</span><br><span style="color: hsl(120, 100%, 40%);">+ .ctrlr = &spi_ctrlr,</span><br><span style="color: hsl(120, 100%, 40%);">+ .bus_start = 0,</span><br><span style="color: hsl(120, 100%, 40%);">+ .bus_end = SPI_BUS_NUMBER - 1,</span><br><span> },</span><br><span> };</span><br><span> </span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/27498">change 27498</a>. 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<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I544e850299c74861313c2425721479fe5b91639e </div>
<div style="display:none"> Gerrit-Change-Number: 27498 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Tristan Hsieh <tristan.shieh@mediatek.com> </div>