<p>Xiang Wang has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/27441">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">riscv: exception handle support SMP<br><br>fix exception handle not support SMP for RISC-V.<br><br>Change-Id: I053138c6d778413d125e91689da330b1ac857027<br>Signed-off-by: Xiang Wang <wxjstz@126.com><br>---<br>M src/arch/riscv/trap_util.S<br>1 file changed, 98 insertions(+), 108 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/27441/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/arch/riscv/trap_util.S b/src/arch/riscv/trap_util.S</span><br><span>index 8aba48b..5e4b0e5 100644</span><br><span>--- a/src/arch/riscv/trap_util.S</span><br><span>+++ b/src/arch/riscv/trap_util.S</span><br><span>@@ -18,124 +18,114 @@</span><br><span> #include <mcall.h></span><br><span> </span><br><span> .macro restore_regs</span><br><span style="color: hsl(0, 100%, 40%);">- # restore x registers</span><br><span style="color: hsl(0, 100%, 40%);">- LOAD x1,1*REGBYTES(a0)</span><br><span style="color: hsl(0, 100%, 40%);">- LOAD x2,2*REGBYTES(a0)</span><br><span style="color: hsl(0, 100%, 40%);">- LOAD x3,3*REGBYTES(a0)</span><br><span style="color: hsl(0, 100%, 40%);">- LOAD x4,4*REGBYTES(a0)</span><br><span style="color: hsl(0, 100%, 40%);">- LOAD x5,5*REGBYTES(a0)</span><br><span style="color: hsl(0, 100%, 40%);">- LOAD x6,6*REGBYTES(a0)</span><br><span style="color: hsl(0, 100%, 40%);">- LOAD x7,7*REGBYTES(a0)</span><br><span style="color: hsl(0, 100%, 40%);">- LOAD x8,8*REGBYTES(a0)</span><br><span style="color: hsl(0, 100%, 40%);">- LOAD x9,9*REGBYTES(a0)</span><br><span style="color: hsl(0, 100%, 40%);">- LOAD x11,11*REGBYTES(a0)</span><br><span style="color: hsl(0, 100%, 40%);">- LOAD x12,12*REGBYTES(a0)</span><br><span style="color: hsl(0, 100%, 40%);">- LOAD x13,13*REGBYTES(a0)</span><br><span style="color: hsl(0, 100%, 40%);">- LOAD x14,14*REGBYTES(a0)</span><br><span style="color: hsl(0, 100%, 40%);">- LOAD x15,15*REGBYTES(a0)</span><br><span style="color: hsl(0, 100%, 40%);">- LOAD x16,16*REGBYTES(a0)</span><br><span style="color: hsl(0, 100%, 40%);">- LOAD x17,17*REGBYTES(a0)</span><br><span style="color: hsl(0, 100%, 40%);">- LOAD x18,18*REGBYTES(a0)</span><br><span style="color: hsl(0, 100%, 40%);">- LOAD x19,19*REGBYTES(a0)</span><br><span style="color: hsl(0, 100%, 40%);">- LOAD x20,20*REGBYTES(a0)</span><br><span style="color: hsl(0, 100%, 40%);">- LOAD x21,21*REGBYTES(a0)</span><br><span style="color: hsl(0, 100%, 40%);">- LOAD x22,22*REGBYTES(a0)</span><br><span style="color: hsl(0, 100%, 40%);">- LOAD x23,23*REGBYTES(a0)</span><br><span style="color: hsl(0, 100%, 40%);">- LOAD x24,24*REGBYTES(a0)</span><br><span style="color: hsl(0, 100%, 40%);">- LOAD x25,25*REGBYTES(a0)</span><br><span style="color: hsl(0, 100%, 40%);">- LOAD x26,26*REGBYTES(a0)</span><br><span style="color: hsl(0, 100%, 40%);">- LOAD x27,27*REGBYTES(a0)</span><br><span style="color: hsl(0, 100%, 40%);">- LOAD x28,28*REGBYTES(a0)</span><br><span style="color: hsl(0, 100%, 40%);">- LOAD x29,29*REGBYTES(a0)</span><br><span style="color: hsl(0, 100%, 40%);">- LOAD x30,30*REGBYTES(a0)</span><br><span style="color: hsl(0, 100%, 40%);">- LOAD x31,31*REGBYTES(a0)</span><br><span style="color: hsl(0, 100%, 40%);">- # restore a0 last</span><br><span style="color: hsl(0, 100%, 40%);">- LOAD x10,10*REGBYTES(a0)</span><br><span style="color: hsl(120, 100%, 40%);">+ # restore x registers</span><br><span style="color: hsl(120, 100%, 40%);">+ LOAD x1,1*REGBYTES(sp)</span><br><span style="color: hsl(120, 100%, 40%);">+ LOAD x3,3*REGBYTES(sp)</span><br><span style="color: hsl(120, 100%, 40%);">+ LOAD x4,4*REGBYTES(sp)</span><br><span style="color: hsl(120, 100%, 40%);">+ LOAD x5,5*REGBYTES(sp)</span><br><span style="color: hsl(120, 100%, 40%);">+ LOAD x6,6*REGBYTES(sp)</span><br><span style="color: hsl(120, 100%, 40%);">+ LOAD x7,7*REGBYTES(sp)</span><br><span style="color: hsl(120, 100%, 40%);">+ LOAD x8,8*REGBYTES(sp)</span><br><span style="color: hsl(120, 100%, 40%);">+ LOAD x9,9*REGBYTES(sp)</span><br><span style="color: hsl(120, 100%, 40%);">+ LOAD x10,10*REGBYTES(sp)</span><br><span style="color: hsl(120, 100%, 40%);">+ LOAD x11,11*REGBYTES(sp)</span><br><span style="color: hsl(120, 100%, 40%);">+ LOAD x12,12*REGBYTES(sp)</span><br><span style="color: hsl(120, 100%, 40%);">+ LOAD x13,13*REGBYTES(sp)</span><br><span style="color: hsl(120, 100%, 40%);">+ LOAD x14,14*REGBYTES(sp)</span><br><span style="color: hsl(120, 100%, 40%);">+ LOAD x15,15*REGBYTES(sp)</span><br><span style="color: hsl(120, 100%, 40%);">+ LOAD x16,16*REGBYTES(sp)</span><br><span style="color: hsl(120, 100%, 40%);">+ LOAD x17,17*REGBYTES(sp)</span><br><span style="color: hsl(120, 100%, 40%);">+ LOAD x18,18*REGBYTES(sp)</span><br><span style="color: hsl(120, 100%, 40%);">+ LOAD x19,19*REGBYTES(sp)</span><br><span style="color: hsl(120, 100%, 40%);">+ LOAD x20,20*REGBYTES(sp)</span><br><span style="color: hsl(120, 100%, 40%);">+ LOAD x21,21*REGBYTES(sp)</span><br><span style="color: hsl(120, 100%, 40%);">+ LOAD x22,22*REGBYTES(sp)</span><br><span style="color: hsl(120, 100%, 40%);">+ LOAD x23,23*REGBYTES(sp)</span><br><span style="color: hsl(120, 100%, 40%);">+ LOAD x24,24*REGBYTES(sp)</span><br><span style="color: hsl(120, 100%, 40%);">+ LOAD x25,25*REGBYTES(sp)</span><br><span style="color: hsl(120, 100%, 40%);">+ LOAD x26,26*REGBYTES(sp)</span><br><span style="color: hsl(120, 100%, 40%);">+ LOAD x27,27*REGBYTES(sp)</span><br><span style="color: hsl(120, 100%, 40%);">+ LOAD x28,28*REGBYTES(sp)</span><br><span style="color: hsl(120, 100%, 40%);">+ LOAD x29,29*REGBYTES(sp)</span><br><span style="color: hsl(120, 100%, 40%);">+ LOAD x30,30*REGBYTES(sp)</span><br><span style="color: hsl(120, 100%, 40%);">+ LOAD x31,31*REGBYTES(sp)</span><br><span style="color: hsl(120, 100%, 40%);">+ .endm</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- .endm</span><br><span> .macro save_tf</span><br><span style="color: hsl(0, 100%, 40%);">- # save gprs</span><br><span style="color: hsl(0, 100%, 40%);">- STORE x1,1*REGBYTES(x2)</span><br><span style="color: hsl(0, 100%, 40%);">- STORE x3,3*REGBYTES(x2)</span><br><span style="color: hsl(0, 100%, 40%);">- STORE x4,4*REGBYTES(x2)</span><br><span style="color: hsl(0, 100%, 40%);">- STORE x5,5*REGBYTES(x2)</span><br><span style="color: hsl(0, 100%, 40%);">- STORE x6,6*REGBYTES(x2)</span><br><span style="color: hsl(0, 100%, 40%);">- STORE x7,7*REGBYTES(x2)</span><br><span style="color: hsl(0, 100%, 40%);">- STORE x8,8*REGBYTES(x2)</span><br><span style="color: hsl(0, 100%, 40%);">- STORE x9,9*REGBYTES(x2)</span><br><span style="color: hsl(0, 100%, 40%);">- STORE x10,10*REGBYTES(x2)</span><br><span style="color: hsl(0, 100%, 40%);">- STORE x11,11*REGBYTES(x2)</span><br><span style="color: hsl(0, 100%, 40%);">- STORE x12,12*REGBYTES(x2)</span><br><span style="color: hsl(0, 100%, 40%);">- STORE x13,13*REGBYTES(x2)</span><br><span style="color: hsl(0, 100%, 40%);">- STORE x14,14*REGBYTES(x2)</span><br><span style="color: hsl(0, 100%, 40%);">- STORE x15,15*REGBYTES(x2)</span><br><span style="color: hsl(0, 100%, 40%);">- STORE x16,16*REGBYTES(x2)</span><br><span style="color: hsl(0, 100%, 40%);">- STORE x17,17*REGBYTES(x2)</span><br><span style="color: hsl(0, 100%, 40%);">- STORE x18,18*REGBYTES(x2)</span><br><span style="color: hsl(0, 100%, 40%);">- STORE x19,19*REGBYTES(x2)</span><br><span style="color: hsl(0, 100%, 40%);">- STORE x20,20*REGBYTES(x2)</span><br><span style="color: hsl(0, 100%, 40%);">- STORE x21,21*REGBYTES(x2)</span><br><span style="color: hsl(0, 100%, 40%);">- STORE x22,22*REGBYTES(x2)</span><br><span style="color: hsl(0, 100%, 40%);">- STORE x23,23*REGBYTES(x2)</span><br><span style="color: hsl(0, 100%, 40%);">- STORE x24,24*REGBYTES(x2)</span><br><span style="color: hsl(0, 100%, 40%);">- STORE x25,25*REGBYTES(x2)</span><br><span style="color: hsl(0, 100%, 40%);">- STORE x26,26*REGBYTES(x2)</span><br><span style="color: hsl(0, 100%, 40%);">- STORE x27,27*REGBYTES(x2)</span><br><span style="color: hsl(0, 100%, 40%);">- STORE x28,28*REGBYTES(x2)</span><br><span style="color: hsl(0, 100%, 40%);">- STORE x29,29*REGBYTES(x2)</span><br><span style="color: hsl(0, 100%, 40%);">- STORE x30,30*REGBYTES(x2)</span><br><span style="color: hsl(0, 100%, 40%);">- STORE x31,31*REGBYTES(x2)</span><br><span style="color: hsl(120, 100%, 40%);">+ # save gprs</span><br><span style="color: hsl(120, 100%, 40%);">+ STORE x1,1*REGBYTES(sp)</span><br><span style="color: hsl(120, 100%, 40%);">+ STORE x3,3*REGBYTES(sp)</span><br><span style="color: hsl(120, 100%, 40%);">+ STORE x4,4*REGBYTES(sp)</span><br><span style="color: hsl(120, 100%, 40%);">+ STORE x5,5*REGBYTES(sp)</span><br><span style="color: hsl(120, 100%, 40%);">+ STORE x6,6*REGBYTES(sp)</span><br><span style="color: hsl(120, 100%, 40%);">+ STORE x7,7*REGBYTES(sp)</span><br><span style="color: hsl(120, 100%, 40%);">+ STORE x8,8*REGBYTES(sp)</span><br><span style="color: hsl(120, 100%, 40%);">+ STORE x9,9*REGBYTES(sp)</span><br><span style="color: hsl(120, 100%, 40%);">+ STORE x10,10*REGBYTES(sp)</span><br><span style="color: hsl(120, 100%, 40%);">+ STORE x11,11*REGBYTES(sp)</span><br><span style="color: hsl(120, 100%, 40%);">+ STORE x12,12*REGBYTES(sp)</span><br><span style="color: hsl(120, 100%, 40%);">+ STORE x13,13*REGBYTES(sp)</span><br><span style="color: hsl(120, 100%, 40%);">+ STORE x14,14*REGBYTES(sp)</span><br><span style="color: hsl(120, 100%, 40%);">+ STORE x15,15*REGBYTES(sp)</span><br><span style="color: hsl(120, 100%, 40%);">+ STORE x16,16*REGBYTES(sp)</span><br><span style="color: hsl(120, 100%, 40%);">+ STORE x17,17*REGBYTES(sp)</span><br><span style="color: hsl(120, 100%, 40%);">+ STORE x18,18*REGBYTES(sp)</span><br><span style="color: hsl(120, 100%, 40%);">+ STORE x19,19*REGBYTES(sp)</span><br><span style="color: hsl(120, 100%, 40%);">+ STORE x20,20*REGBYTES(sp)</span><br><span style="color: hsl(120, 100%, 40%);">+ STORE x21,21*REGBYTES(sp)</span><br><span style="color: hsl(120, 100%, 40%);">+ STORE x22,22*REGBYTES(sp)</span><br><span style="color: hsl(120, 100%, 40%);">+ STORE x23,23*REGBYTES(sp)</span><br><span style="color: hsl(120, 100%, 40%);">+ STORE x24,24*REGBYTES(sp)</span><br><span style="color: hsl(120, 100%, 40%);">+ STORE x25,25*REGBYTES(sp)</span><br><span style="color: hsl(120, 100%, 40%);">+ STORE x26,26*REGBYTES(sp)</span><br><span style="color: hsl(120, 100%, 40%);">+ STORE x27,27*REGBYTES(sp)</span><br><span style="color: hsl(120, 100%, 40%);">+ STORE x28,28*REGBYTES(sp)</span><br><span style="color: hsl(120, 100%, 40%);">+ STORE x29,29*REGBYTES(sp)</span><br><span style="color: hsl(120, 100%, 40%);">+ STORE x30,30*REGBYTES(sp)</span><br><span style="color: hsl(120, 100%, 40%);">+ STORE x31,31*REGBYTES(sp)</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- # get sr, epc, badvaddr, cause</span><br><span style="color: hsl(0, 100%, 40%);">- csrrw t0,mscratch,x0</span><br><span style="color: hsl(0, 100%, 40%);">- csrr s0,mstatus</span><br><span style="color: hsl(0, 100%, 40%);">- csrr t1,mepc</span><br><span style="color: hsl(0, 100%, 40%);">- csrr t2,mbadaddr</span><br><span style="color: hsl(0, 100%, 40%);">- csrr t3,mcause</span><br><span style="color: hsl(0, 100%, 40%);">- STORE t0,2*REGBYTES(x2)</span><br><span style="color: hsl(0, 100%, 40%);">- STORE s0,32*REGBYTES(x2)</span><br><span style="color: hsl(0, 100%, 40%);">- STORE t1,33*REGBYTES(x2)</span><br><span style="color: hsl(0, 100%, 40%);">- STORE t2,34*REGBYTES(x2)</span><br><span style="color: hsl(0, 100%, 40%);">- STORE t3,35*REGBYTES(x2)</span><br><span style="color: hsl(120, 100%, 40%);">+ # get sr, epc, badvaddr, cause</span><br><span style="color: hsl(120, 100%, 40%);">+ csrrw t0,mscratch,x0</span><br><span style="color: hsl(120, 100%, 40%);">+ csrr s0,mstatus</span><br><span style="color: hsl(120, 100%, 40%);">+ csrr t1,mepc</span><br><span style="color: hsl(120, 100%, 40%);">+ csrr t2,mbadaddr</span><br><span style="color: hsl(120, 100%, 40%);">+ csrr t3,mcause</span><br><span style="color: hsl(120, 100%, 40%);">+ STORE t0,2*REGBYTES(sp)</span><br><span style="color: hsl(120, 100%, 40%);">+ STORE s0,32*REGBYTES(sp)</span><br><span style="color: hsl(120, 100%, 40%);">+ STORE t1,33*REGBYTES(sp)</span><br><span style="color: hsl(120, 100%, 40%);">+ STORE t2,34*REGBYTES(sp)</span><br><span style="color: hsl(120, 100%, 40%);">+ STORE t3,35*REGBYTES(sp)</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- # get faulting insn, if it wasn't a fetch-related trap</span><br><span style="color: hsl(0, 100%, 40%);">- li x5,-1</span><br><span style="color: hsl(0, 100%, 40%);">- STORE x5,36*REGBYTES(x2)</span><br><span style="color: hsl(120, 100%, 40%);">+ # get faulting insn, if it wasn't a fetch-related trap</span><br><span style="color: hsl(120, 100%, 40%);">+ li x5,-1</span><br><span style="color: hsl(120, 100%, 40%);">+ STORE x5,36*REGBYTES(sp)</span><br><span style="color: hsl(120, 100%, 40%);">+ .endm</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- .endm</span><br><span style="color: hsl(120, 100%, 40%);">+ .globl estack</span><br><span style="color: hsl(120, 100%, 40%);">+ .text</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-.globl estack</span><br><span style="color: hsl(0, 100%, 40%);">- .text</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- .global trap_entry</span><br><span style="color: hsl(0, 100%, 40%);">- .align 2 # four byte alignment, as required by mtvec</span><br><span style="color: hsl(120, 100%, 40%);">+ .global trap_entry</span><br><span style="color: hsl(120, 100%, 40%);">+ .align 2 # four byte alignment, as required by mtvec</span><br><span> trap_entry:</span><br><span style="color: hsl(0, 100%, 40%);">- csrw mscratch, sp</span><br><span style="color: hsl(120, 100%, 40%);">+ # switch stack pointer between m-mode and other mode</span><br><span style="color: hsl(120, 100%, 40%);">+ csrrw sp, mscratch, sp</span><br><span style="color: hsl(120, 100%, 40%);">+ bnez sp, 1f</span><br><span style="color: hsl(120, 100%, 40%);">+ # trap come from m-mode (mscratch initialize to zero)</span><br><span style="color: hsl(120, 100%, 40%);">+ csrr sp, mscratch</span><br><span style="color: hsl(120, 100%, 40%);">+1:</span><br><span style="color: hsl(120, 100%, 40%);">+ addi sp, sp, -MENTRY_FRAME_SIZE</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- # SMP isn't supported yet, to avoid overwriting the same stack with different</span><br><span style="color: hsl(0, 100%, 40%);">- # harts that handle traps at the same time.</span><br><span style="color: hsl(0, 100%, 40%);">- # someday this gets fixed.</span><br><span style="color: hsl(0, 100%, 40%);">- //csrr sp, mhartid</span><br><span style="color: hsl(0, 100%, 40%);">- csrr sp, 0xf14</span><br><span style="color: hsl(0, 100%, 40%);">-.Lsmp_hang:</span><br><span style="color: hsl(0, 100%, 40%);">- bnez sp, .Lsmp_hang</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- # Use a different stack than in the main context, to to avoid overwriting</span><br><span style="color: hsl(0, 100%, 40%);">- # stack data.</span><br><span style="color: hsl(0, 100%, 40%);">- # TODO: Maybe use the old stack pointer (plus an offset) instead. But only if</span><br><span style="color: hsl(0, 100%, 40%);">- # the previous mode was M, because it would be a very bad idea to use a stack</span><br><span style="color: hsl(0, 100%, 40%);">- # pointer provided by unprivileged code!</span><br><span style="color: hsl(0, 100%, 40%);">- la sp, _estack</span><br><span style="color: hsl(0, 100%, 40%);">- addi sp, sp, -2048 # 2 KiB is half of the stack space</span><br><span style="color: hsl(0, 100%, 40%);">- addi sp, sp, -MENTRY_FRAME_SIZE</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- save_tf</span><br><span style="color: hsl(0, 100%, 40%);">- move a0,sp</span><br><span style="color: hsl(0, 100%, 40%);">- jal trap_handler</span><br><span style="color: hsl(120, 100%, 40%);">+ save_tf</span><br><span style="color: hsl(120, 100%, 40%);">+ move a0, sp</span><br><span style="color: hsl(120, 100%, 40%);">+ call trap_handler</span><br><span> </span><br><span> trap_return:</span><br><span style="color: hsl(0, 100%, 40%);">- csrr a0, mscratch</span><br><span> restore_regs</span><br><span style="color: hsl(120, 100%, 40%);">+ addi sp, sp, MENTRY_FRAME_SIZE</span><br><span style="color: hsl(120, 100%, 40%);">+ csrrw sp, mscratch, sp</span><br><span style="color: hsl(120, 100%, 40%);">+ bnez sp, 1f</span><br><span style="color: hsl(120, 100%, 40%);">+ csrrw sp, mscratch, x0</span><br><span style="color: hsl(120, 100%, 40%);">+1:</span><br><span> # go back to the previous mode</span><br><span> mret</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/27441">change 27441</a>. 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<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I053138c6d778413d125e91689da330b1ac857027 </div>
<div style="display:none"> Gerrit-Change-Number: 27441 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Xiang Wang <wxjstz@126.com> </div>