<p>Philipp Hug has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/27439">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">sifive/fu540: PLL + clock initialization<br><br>Change-Id: Iba0669e08940e373aaf42cbba3a1ceffd68a4f52<br>---<br>A src/soc/sifive/fu540/clock.c<br>A src/soc/sifive/fu540/include/soc/clock.h<br>2 files changed, 198 insertions(+), 0 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/27439/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/soc/sifive/fu540/clock.c b/src/soc/sifive/fu540/clock.c</span><br><span>new file mode 100644</span><br><span>index 0000000..1fa850c</span><br><span>--- /dev/null</span><br><span>+++ b/src/soc/sifive/fu540/clock.c</span><br><span>@@ -0,0 +1,174 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright 2018 Philipp Hug <philipp@hug.cx></span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <arch/barrier.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <arch/io.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <console/console.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/clock.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/addressmap.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <stdlib.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <stdint.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+struct prci_ctlr {</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 hfxosccfg; /* offset 0x00 */</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 corepllcfg0; /* offset 0x04 */</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 reserved08; /* offset 0x08 */</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 ddrpllcfg0; /* offset 0x0c */</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 ddrpllcfg1; /* offset 0x10 */</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 reserved14; /* offset 0x14 */</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 reserved18; /* offset 0x18 */</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 gemgxlpllcfg0; /* offset 0x1c */</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 gemgxlpllcfg1; /* offset 0x20 */</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 coreclksel; /* offset 0x24 */</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 devicesresetreg; /* offset 0x28 */</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static struct prci_ctlr *prci = (void *)FU540_PRCI;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define PRCI_CORECLK_MASK 1</span><br><span style="color: hsl(120, 100%, 40%);">+#define PRCI_CORECLK_CORE_PLL 0</span><br><span style="color: hsl(120, 100%, 40%);">+#define PRCI_CORECLK_HFCLK 1</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define PRCI_COREPLLCFG0_LOCK (1u << 31)</span><br><span style="color: hsl(120, 100%, 40%);">+#define PRCI_COREPLLCFG0_DIVR_SHIFT 0</span><br><span style="color: hsl(120, 100%, 40%);">+#define PRCI_COREPLLCFG0_DIVF_SHIFT 6</span><br><span style="color: hsl(120, 100%, 40%);">+#define PRCI_COREPLLCFG0_DIVQ_SHIFT 15</span><br><span style="color: hsl(120, 100%, 40%);">+#define PRCI_COREPLLCFG0_RANGE_SHIFT 18</span><br><span style="color: hsl(120, 100%, 40%);">+#define PRCI_COREPLLCFG0_BYPASS_SHIFT 24</span><br><span style="color: hsl(120, 100%, 40%);">+#define PRCI_COREPLLCFG0_DIVR_MASK (0x03f << PRCI_COREPLLCFG0_DIVR_SHIFT)</span><br><span style="color: hsl(120, 100%, 40%);">+#define PRCI_COREPLLCFG0_DIVF_MASK (0x1ff << PRCI_COREPLLCFG0_DIVF_SHIFT)</span><br><span style="color: hsl(120, 100%, 40%);">+#define PRCI_COREPLLCFG0_DIVQ_MASK (0x007 << PRCI_COREPLLCFG0_DIVQ_SHIFT)</span><br><span style="color: hsl(120, 100%, 40%);">+#define PRCI_COREPLLCFG0_RANGE_MASK (0x07 << PRCI_COREPLLCFG0_RANGE_SHIFT)</span><br><span style="color: hsl(120, 100%, 40%);">+#define PRCI_COREPLLCFG0_BYPASS_MASK (0x1 << PRCI_COREPLLCFG0_BYPASS_SHIFT)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define PRCI_DDRPLLCFG0_LOCK (1u << 31)</span><br><span style="color: hsl(120, 100%, 40%);">+#define PRCI_DDRPLLCFG0_DIVR_SHIFT 0</span><br><span style="color: hsl(120, 100%, 40%);">+#define PRCI_DDRPLLCFG0_DIVF_SHIFT 6</span><br><span style="color: hsl(120, 100%, 40%);">+#define PRCI_DDRPLLCFG0_DIVQ_SHIFT 15</span><br><span style="color: hsl(120, 100%, 40%);">+#define PRCI_DDRPLLCFG0_RANGE_SHIFT 18</span><br><span style="color: hsl(120, 100%, 40%);">+#define PRCI_DDRPLLCFG0_BYPASS_SHIFT 24</span><br><span style="color: hsl(120, 100%, 40%);">+#define PRCI_DDRPLLCFG0_DIVR_MASK (0x03f << PRCI_DDRPLLCFG0_DIVR_SHIFT)</span><br><span style="color: hsl(120, 100%, 40%);">+#define PRCI_DDRPLLCFG0_DIVF_MASK (0x1ff << PRCI_DDRPLLCFG0_DIVF_SHIFT)</span><br><span style="color: hsl(120, 100%, 40%);">+#define PRCI_DDRPLLCFG0_DIVQ_MASK (0x007 << PRCI_DDRPLLCFG0_DIVQ_SHIFT)</span><br><span style="color: hsl(120, 100%, 40%);">+#define PRCI_DDRPLLCFG0_RANGE_MASK (0x07 << PRCI_DDRPLLCFG0_RANGE_SHIFT)</span><br><span style="color: hsl(120, 100%, 40%);">+#define PRCI_DDRPLLCFG0_BYPASS_MASK (0x1 << PRCI_DDRPLLCFG0_BYPASS_SHIFT)</span><br><span style="color: hsl(120, 100%, 40%);">+#define PRCI_DDRPLLCFG1_MASK (1u << 31)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define PRCI_CORECLK_DIVR 0</span><br><span style="color: hsl(120, 100%, 40%);">+#define PRCI_CORECLK_DIVF 59</span><br><span style="color: hsl(120, 100%, 40%);">+#define PRCI_CORECLK_DIVQ 2</span><br><span style="color: hsl(120, 100%, 40%);">+#define PRCI_CORECLK_RANGE 4</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define PRCI_DDRCLK_DIVR 0</span><br><span style="color: hsl(120, 100%, 40%);">+#define PRCI_DDRCLK_DIVF 59</span><br><span style="color: hsl(120, 100%, 40%);">+#define PRCI_DDRCLK_DIVQ 5</span><br><span style="color: hsl(120, 100%, 40%);">+#define PRCI_DDRCLK_RANGE 4</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define PRCI_RESET_DDR_CTRL_RST_N (1 << 0)</span><br><span style="color: hsl(120, 100%, 40%);">+#define PRCI_RESET_DDR_AXI_RST_N (1 << 1)</span><br><span style="color: hsl(120, 100%, 40%);">+#define PRCI_RESET_DDR_AHB_RST_N (1 << 2)</span><br><span style="color: hsl(120, 100%, 40%);">+#define PRCI_RESET_DDR_PHY_RST_N (1 << 3)</span><br><span style="color: hsl(120, 100%, 40%);">+#define PRCI_RESET_GEMGXL_RST_N (1 << 5)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// 33.33 Mhz after reset</span><br><span style="color: hsl(120, 100%, 40%);">+#define FU540_BASE_FQY 33330</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static void init_pll_core(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&prci->coreclksel, PRCI_CORECLK_MASK, PRCI_CORECLK_HFCLK);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 c = read32(&prci->corepllcfg0);</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&c, PRCI_COREPLLCFG0_DIVR_MASK</span><br><span style="color: hsl(120, 100%, 40%);">+ | PRCI_COREPLLCFG0_DIVF_MASK | PRCI_COREPLLCFG0_DIVQ_MASK</span><br><span style="color: hsl(120, 100%, 40%);">+ | PRCI_COREPLLCFG0_RANGE_MASK | PRCI_COREPLLCFG0_BYPASS_MASK,</span><br><span style="color: hsl(120, 100%, 40%);">+ (PRCI_CORECLK_DIVR << PRCI_COREPLLCFG0_DIVR_SHIFT)</span><br><span style="color: hsl(120, 100%, 40%);">+ & (PRCI_CORECLK_DIVF << PRCI_COREPLLCFG0_DIVF_SHIFT)</span><br><span style="color: hsl(120, 100%, 40%);">+ & (PRCI_CORECLK_DIVQ << PRCI_COREPLLCFG0_DIVQ_SHIFT)</span><br><span style="color: hsl(120, 100%, 40%);">+ & (PRCI_CORECLK_RANGE << PRCI_COREPLLCFG0_RANGE_SHIFT));</span><br><span style="color: hsl(120, 100%, 40%);">+ write32(&prci->corepllcfg0, c);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ // wait for PLL lock</span><br><span style="color: hsl(120, 100%, 40%);">+ while (!(read32(&prci->corepllcfg0) & PRCI_COREPLLCFG0_LOCK))</span><br><span style="color: hsl(120, 100%, 40%);">+ ; /* TODO: implement a timeout */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&prci->coreclksel, PRCI_CORECLK_MASK, PRCI_CORECLK_CORE_PLL);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static void init_pll_ddr(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 cfg1 = read32(&prci->ddrpllcfg1);</span><br><span style="color: hsl(120, 100%, 40%);">+ clrbits_le32(&cfg1, PRCI_DDRPLLCFG1_MASK);</span><br><span style="color: hsl(120, 100%, 40%);">+ write32(&prci->ddrpllcfg1, cfg1);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 c = read32(&prci->ddrpllcfg0);</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&c, PRCI_DDRPLLCFG0_DIVR_MASK</span><br><span style="color: hsl(120, 100%, 40%);">+ | PRCI_DDRPLLCFG0_DIVF_MASK | PRCI_DDRPLLCFG0_DIVQ_MASK</span><br><span style="color: hsl(120, 100%, 40%);">+ | PRCI_DDRPLLCFG0_RANGE_MASK | PRCI_DDRPLLCFG0_BYPASS_MASK,</span><br><span style="color: hsl(120, 100%, 40%);">+ (PRCI_DDRCLK_DIVR << PRCI_DDRPLLCFG0_DIVR_SHIFT)</span><br><span style="color: hsl(120, 100%, 40%);">+ & (PRCI_DDRCLK_DIVF << PRCI_DDRPLLCFG0_DIVF_SHIFT)</span><br><span style="color: hsl(120, 100%, 40%);">+ & (PRCI_DDRCLK_DIVQ << PRCI_DDRPLLCFG0_DIVQ_SHIFT)</span><br><span style="color: hsl(120, 100%, 40%);">+ & (PRCI_DDRCLK_RANGE << PRCI_DDRPLLCFG0_RANGE_SHIFT));</span><br><span style="color: hsl(120, 100%, 40%);">+ write32(&prci->ddrpllcfg0, c);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ // wait for PLL lock</span><br><span style="color: hsl(120, 100%, 40%);">+ while (!(read32(&prci->ddrpllcfg0) & PRCI_DDRPLLCFG0_LOCK))</span><br><span style="color: hsl(120, 100%, 40%);">+ ; /* TODO: implement a timeout */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ setbits_le32(&cfg1, PRCI_DDRPLLCFG1_MASK);</span><br><span style="color: hsl(120, 100%, 40%);">+ write32(&prci->ddrpllcfg1, cfg1);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+int clock_get_coreclk_khz(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ if (read32(&prci->coreclksel) & PRCI_CORECLK_MASK) {</span><br><span style="color: hsl(120, 100%, 40%);">+ return FU540_BASE_FQY;</span><br><span style="color: hsl(120, 100%, 40%);">+ } else {</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 cfg = read32(&prci->corepllcfg0);</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 divr = (cfg & PRCI_COREPLLCFG0_DIVR_MASK)</span><br><span style="color: hsl(120, 100%, 40%);">+ >> PRCI_COREPLLCFG0_DIVR_SHIFT;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 divf = (cfg & PRCI_COREPLLCFG0_DIVF_MASK)</span><br><span style="color: hsl(120, 100%, 40%);">+ >> PRCI_COREPLLCFG0_DIVF_SHIFT;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 divq = (cfg & PRCI_COREPLLCFG0_DIVQ_MASK)</span><br><span style="color: hsl(120, 100%, 40%);">+ >> PRCI_COREPLLCFG0_DIVQ_SHIFT;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ printk(BIOS_SPEW, "clk: r=%d f=%d q=%d\n", divr, divf, divq);</span><br><span style="color: hsl(120, 100%, 40%);">+ return FU540_BASE_FQY</span><br><span style="color: hsl(120, 100%, 40%);">+ * 2 * (divf + 1)</span><br><span style="color: hsl(120, 100%, 40%);">+ / (divr + 1)</span><br><span style="color: hsl(120, 100%, 40%);">+ / (1 << divq);</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static void my_sdram_init(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ setbits_le32(&prci->devicesresetreg, PRCI_RESET_DDR_CTRL_RST_N);</span><br><span style="color: hsl(120, 100%, 40%);">+ mb();</span><br><span style="color: hsl(120, 100%, 40%);">+ setbits_le32(&prci->devicesresetreg, PRCI_RESET_DDR_AXI_RST_N);</span><br><span style="color: hsl(120, 100%, 40%);">+ setbits_le32(&prci->devicesresetreg, PRCI_RESET_DDR_AHB_RST_N);</span><br><span style="color: hsl(120, 100%, 40%);">+ setbits_le32(&prci->devicesresetreg, PRCI_RESET_DDR_PHY_RST_N);</span><br><span style="color: hsl(120, 100%, 40%);">+ for(int i = 0; i<256; i++)</span><br><span style="color: hsl(120, 100%, 40%);">+ mb();</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+void clock_init(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ init_pll_core();</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ // put all peripherals in reset</span><br><span style="color: hsl(120, 100%, 40%);">+ write32(&prci->devicesresetreg, 0);</span><br><span style="color: hsl(120, 100%, 40%);">+ init_pll_ddr();</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ my_sdram_init();</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span>diff --git a/src/soc/sifive/fu540/include/soc/clock.h b/src/soc/sifive/fu540/include/soc/clock.h</span><br><span>new file mode 100644</span><br><span>index 0000000..cc868e3</span><br><span>--- /dev/null</span><br><span>+++ b/src/soc/sifive/fu540/include/soc/clock.h</span><br><span>@@ -0,0 +1,24 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright 2018 Philipp Hug <philipp@hug.cx></span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef __SOC_SIFIVE_HIFIVE_U_CLOCK_H__</span><br><span style="color: hsl(120, 100%, 40%);">+#define __SOC_SIFIVE_HIFIVE_U_CLOCK_H__</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define PRCI_CORECLKSEL_CORECLKSEL 1</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+void clock_init(void);</span><br><span style="color: hsl(120, 100%, 40%);">+int clock_get_coreclk_khz(void);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#endif /* __SOC_SIFIVE_HIFIFE_U_CLOCK_H__ */</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/27439">change 27439</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/27439"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: Iba0669e08940e373aaf42cbba3a1ceffd68a4f52 </div>
<div style="display:none"> Gerrit-Change-Number: 27439 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Philipp Hug <philipp@hug.cx> </div>