<p>Martin Roth has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/27424">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">mainboard/google/kahlee: Init careena WLAN card at PCIe Gen 1<br><br>The WLAN card used for careena does not enumerate correctly if set to a<br>higer speed, so set the max speed to Gen 1.<br><br>BUG=b:110449139<br>TEST=Boot careena, verify that the wlan card is present.<br><br>Change-Id: Ib692d202a7fe67195a390553f70d60a9d955b6d8<br>Signed-off-by: Martin Roth <martinroth@google.com><br>---<br>M src/mainboard/google/kahlee/variants/careena/Makefile.inc<br>A src/mainboard/google/kahlee/variants/careena/OemCustomize.c<br>M src/mainboard/google/kahlee/variants/grunt/Makefile.inc<br>3 files changed, 156 insertions(+), 0 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/27424/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/mainboard/google/kahlee/variants/careena/Makefile.inc b/src/mainboard/google/kahlee/variants/careena/Makefile.inc</span><br><span>index 0579e18..3b14bf3 100644</span><br><span>--- a/src/mainboard/google/kahlee/variants/careena/Makefile.inc</span><br><span>+++ b/src/mainboard/google/kahlee/variants/careena/Makefile.inc</span><br><span>@@ -16,5 +16,6 @@</span><br><span> subdirs-y += ../baseboard/spd</span><br><span> </span><br><span> romstage-y += ../baseboard/romstage.c</span><br><span style="color: hsl(120, 100%, 40%);">+romatage-y += OemCustomize.c</span><br><span> </span><br><span> ramstage-y += ../baseboard/mainboard.c</span><br><span>diff --git a/src/mainboard/google/kahlee/variants/careena/OemCustomize.c b/src/mainboard/google/kahlee/variants/careena/OemCustomize.c</span><br><span>new file mode 100644</span><br><span>index 0000000..ac93712</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/google/kahlee/variants/careena/OemCustomize.c</span><br><span>@@ -0,0 +1,154 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2015-2016 Advanced Micro Devices, Inc.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <compiler.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <amdblocks/agesawrapper.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <variant/gpio.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <boardid.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static const PCIe_PORT_DESCRIPTOR PortList[] = {</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Initialize Port descriptor (PCIe port, Lanes 7:4, D2F1) for NC*/</span><br><span style="color: hsl(120, 100%, 40%);">+ {</span><br><span style="color: hsl(120, 100%, 40%);">+ 0,</span><br><span style="color: hsl(120, 100%, 40%);">+ PCIE_ENGINE_DATA_INITIALIZER(PcieUnusedEngine, 4, 7),</span><br><span style="color: hsl(120, 100%, 40%);">+ PCIE_PORT_DATA_INITIALIZER_V2(</span><br><span style="color: hsl(120, 100%, 40%);">+ PortDisabled, /* mPortPresent */</span><br><span style="color: hsl(120, 100%, 40%);">+ ChannelTypeExt6db, /* mChannelType */</span><br><span style="color: hsl(120, 100%, 40%);">+ 2, /* mDevAddress */</span><br><span style="color: hsl(120, 100%, 40%);">+ 1, /* mDevFunction */</span><br><span style="color: hsl(120, 100%, 40%);">+ HotplugDisabled, /* mHotplug */</span><br><span style="color: hsl(120, 100%, 40%);">+ PcieGenMaxSupported, /* mMaxLinkSpeed */</span><br><span style="color: hsl(120, 100%, 40%);">+ PcieGenMaxSupported, /* mMaxLinkCap */</span><br><span style="color: hsl(120, 100%, 40%);">+ AspmL0sL1, /* mAspm */</span><br><span style="color: hsl(120, 100%, 40%);">+ 0, /* mResetId */</span><br><span style="color: hsl(120, 100%, 40%);">+ 0) /* mClkPmSupport */</span><br><span style="color: hsl(120, 100%, 40%);">+ },</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Initialize Port descriptor (PCIe port, Lanes 0:0, D2F2) for WLAN */</span><br><span style="color: hsl(120, 100%, 40%);">+ {</span><br><span style="color: hsl(120, 100%, 40%);">+ 0,</span><br><span style="color: hsl(120, 100%, 40%);">+ PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 0, 0),</span><br><span style="color: hsl(120, 100%, 40%);">+ PCIE_PORT_DATA_INITIALIZER_V2(</span><br><span style="color: hsl(120, 100%, 40%);">+ PortEnabled, /* mPortPresent */</span><br><span style="color: hsl(120, 100%, 40%);">+ ChannelTypeMob0db, /* mChannelType */</span><br><span style="color: hsl(120, 100%, 40%);">+ 2, /* mDevAddress */</span><br><span style="color: hsl(120, 100%, 40%);">+ 2, /* mDevFunction */</span><br><span style="color: hsl(120, 100%, 40%);">+ HotplugDisabled, /* mHotplug */</span><br><span style="color: hsl(120, 100%, 40%);">+ PcieGen1, /* mPcieGen1 */</span><br><span style="color: hsl(120, 100%, 40%);">+ PcieGenMaxSupported, /* mMaxLinkCap */</span><br><span style="color: hsl(120, 100%, 40%);">+ AspmL0sL1, /* mAspm */</span><br><span style="color: hsl(120, 100%, 40%);">+ PCIE_0_RST, /* mResetId */</span><br><span style="color: hsl(120, 100%, 40%);">+ 0) /* mClkPmSupport */</span><br><span style="color: hsl(120, 100%, 40%);">+ },</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Init Port descriptor (PCIe port, Lanes 1:1, D2F3) NC */</span><br><span style="color: hsl(120, 100%, 40%);">+ {</span><br><span style="color: hsl(120, 100%, 40%);">+ 0,</span><br><span style="color: hsl(120, 100%, 40%);">+ PCIE_ENGINE_DATA_INITIALIZER(PcieUnusedEngine, 1, 1),</span><br><span style="color: hsl(120, 100%, 40%);">+ PCIE_PORT_DATA_INITIALIZER_V2(</span><br><span style="color: hsl(120, 100%, 40%);">+ PortDisabled, /* mPortPresent */</span><br><span style="color: hsl(120, 100%, 40%);">+ ChannelTypeExt6db, /* mChannelType */</span><br><span style="color: hsl(120, 100%, 40%);">+ 2, /* mDevAddress */</span><br><span style="color: hsl(120, 100%, 40%);">+ 3, /* mDevFunction */</span><br><span style="color: hsl(120, 100%, 40%);">+ HotplugDisabled, /* mHotplug */</span><br><span style="color: hsl(120, 100%, 40%);">+ PcieGenMaxSupported, /* mMaxLinkSpeed */</span><br><span style="color: hsl(120, 100%, 40%);">+ PcieGenMaxSupported, /* mMaxLinkCap */</span><br><span style="color: hsl(120, 100%, 40%);">+ AspmL0sL1, /* mAspm */</span><br><span style="color: hsl(120, 100%, 40%);">+ PCIE_1_RST, /* mResetId */</span><br><span style="color: hsl(120, 100%, 40%);">+ 0) /* mClkPmSupport */</span><br><span style="color: hsl(120, 100%, 40%);">+ },</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Initialize Port descriptor (PCIe port, Lane 2, D2F4) for EMMC */</span><br><span style="color: hsl(120, 100%, 40%);">+ {</span><br><span style="color: hsl(120, 100%, 40%);">+ 0,</span><br><span style="color: hsl(120, 100%, 40%);">+ PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 2, 2),</span><br><span style="color: hsl(120, 100%, 40%);">+ PCIE_PORT_DATA_INITIALIZER_V2(</span><br><span style="color: hsl(120, 100%, 40%);">+ PortEnabled, /* mPortPresent */</span><br><span style="color: hsl(120, 100%, 40%);">+ ChannelTypeExt6db, /* mChannelType */</span><br><span style="color: hsl(120, 100%, 40%);">+ 2, /* mDevAddress */</span><br><span style="color: hsl(120, 100%, 40%);">+ 4, /* mDevFunction */</span><br><span style="color: hsl(120, 100%, 40%);">+ HotplugDisabled, /* mHotplug */</span><br><span style="color: hsl(120, 100%, 40%);">+ PcieGenMaxSupported, /* mMaxLinkSpeed */</span><br><span style="color: hsl(120, 100%, 40%);">+ PcieGenMaxSupported, /* mMaxLinkCap */</span><br><span style="color: hsl(120, 100%, 40%);">+ AspmL0sL1, /* mAspm */</span><br><span style="color: hsl(120, 100%, 40%);">+ PCIE_2_RST, /* mResetId */</span><br><span style="color: hsl(120, 100%, 40%);">+ 0) /* mClkPmSupport */</span><br><span style="color: hsl(120, 100%, 40%);">+ },</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Initialize Port descriptor (PCIe port, Lane3, D2F5) for NC */</span><br><span style="color: hsl(120, 100%, 40%);">+ {</span><br><span style="color: hsl(120, 100%, 40%);">+ DESCRIPTOR_TERMINATE_LIST,</span><br><span style="color: hsl(120, 100%, 40%);">+ PCIE_ENGINE_DATA_INITIALIZER(PcieUnusedEngine, 3, 3),</span><br><span style="color: hsl(120, 100%, 40%);">+ PCIE_PORT_DATA_INITIALIZER_V2(</span><br><span style="color: hsl(120, 100%, 40%);">+ PortDisabled, /* mPortPresent */</span><br><span style="color: hsl(120, 100%, 40%);">+ ChannelTypeExt6db, /* mChannelType */</span><br><span style="color: hsl(120, 100%, 40%);">+ 2, /* mDevAddress */</span><br><span style="color: hsl(120, 100%, 40%);">+ 5, /* mDevFunction */</span><br><span style="color: hsl(120, 100%, 40%);">+ HotplugDisabled, /* mHotplug */</span><br><span style="color: hsl(120, 100%, 40%);">+ PcieGenMaxSupported, /* mMaxLinkSpeed */</span><br><span style="color: hsl(120, 100%, 40%);">+ PcieGenMaxSupported, /* mMaxLinkCap */</span><br><span style="color: hsl(120, 100%, 40%);">+ AspmL0sL1, /* mAspm */</span><br><span style="color: hsl(120, 100%, 40%);">+ PCIE_3_RST, /* mResetId */</span><br><span style="color: hsl(120, 100%, 40%);">+ 0) /* mClkPmSupport */</span><br><span style="color: hsl(120, 100%, 40%);">+ },</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static const PCIe_DDI_DESCRIPTOR DdiList[] = {</span><br><span style="color: hsl(120, 100%, 40%);">+ /* DDI0 - eDP */</span><br><span style="color: hsl(120, 100%, 40%);">+ {</span><br><span style="color: hsl(120, 100%, 40%);">+ 0,</span><br><span style="color: hsl(120, 100%, 40%);">+ PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 8, 11),</span><br><span style="color: hsl(120, 100%, 40%);">+ PCIE_DDI_DATA_INITIALIZER(ConnectorTypeEDP, Aux1, Hdp1)</span><br><span style="color: hsl(120, 100%, 40%);">+ },</span><br><span style="color: hsl(120, 100%, 40%);">+ /* DDI1 - DP */</span><br><span style="color: hsl(120, 100%, 40%);">+ {</span><br><span style="color: hsl(120, 100%, 40%);">+ 0,</span><br><span style="color: hsl(120, 100%, 40%);">+ PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 12, 15),</span><br><span style="color: hsl(120, 100%, 40%);">+ PCIE_DDI_DATA_INITIALIZER(ConnectorTypeDP, Aux2, Hdp2)</span><br><span style="color: hsl(120, 100%, 40%);">+ },</span><br><span style="color: hsl(120, 100%, 40%);">+ /* DDI2 - DP */</span><br><span style="color: hsl(120, 100%, 40%);">+ {</span><br><span style="color: hsl(120, 100%, 40%);">+ DESCRIPTOR_TERMINATE_LIST,</span><br><span style="color: hsl(120, 100%, 40%);">+ PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 16, 19),</span><br><span style="color: hsl(120, 100%, 40%);">+ PCIE_DDI_DATA_INITIALIZER(ConnectorTypeDP, Aux3, Hdp3)</span><br><span style="color: hsl(120, 100%, 40%);">+ },</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static const PCIe_COMPLEX_DESCRIPTOR PcieComplex = {</span><br><span style="color: hsl(120, 100%, 40%);">+ .Flags = DESCRIPTOR_TERMINATE_LIST,</span><br><span style="color: hsl(120, 100%, 40%);">+ .SocketId = 0,</span><br><span style="color: hsl(120, 100%, 40%);">+ .PciePortList = (void *)PortList,</span><br><span style="color: hsl(120, 100%, 40%);">+ .DdiLinkList = (void *)DdiList</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/*---------------------------------------------------------------------------*/</span><br><span style="color: hsl(120, 100%, 40%);">+/**</span><br><span style="color: hsl(120, 100%, 40%);">+ * OemCustomizeInitEarly</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Description:</span><br><span style="color: hsl(120, 100%, 40%);">+ * This is the stub function will call the host environment through the</span><br><span style="color: hsl(120, 100%, 40%);">+ * binary block interface (call-out port) to provide a user hook opportunity.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Parameters:</span><br><span style="color: hsl(120, 100%, 40%);">+ * @param[in] **PeiServices</span><br><span style="color: hsl(120, 100%, 40%);">+ * @param[in] *InitEarly</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * @retval VOID</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ **/</span><br><span style="color: hsl(120, 100%, 40%);">+/*---------------------------------------------------------------------------*/</span><br><span style="color: hsl(120, 100%, 40%);">+VOID __weak OemCustomizeInitEarly(IN OUT AMD_EARLY_PARAMS *InitEarly)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ InitEarly->GnbConfig.PcieComplexList = (void *)&PcieComplex;</span><br><span style="color: hsl(120, 100%, 40%);">+ InitEarly->PlatformConfig.GnbAzI2sBusSelect = GnbAcpI2sBus;</span><br><span style="color: hsl(120, 100%, 40%);">+ InitEarly->PlatformConfig.GnbAzI2sBusPinConfig = GnbAcp2Tx4RxBluetooth;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span>diff --git a/src/mainboard/google/kahlee/variants/grunt/Makefile.inc b/src/mainboard/google/kahlee/variants/grunt/Makefile.inc</span><br><span>index 0579e18..d5ad4ed 100644</span><br><span>--- a/src/mainboard/google/kahlee/variants/grunt/Makefile.inc</span><br><span>+++ b/src/mainboard/google/kahlee/variants/grunt/Makefile.inc</span><br><span>@@ -16,5 +16,6 @@</span><br><span> subdirs-y += ../baseboard/spd</span><br><span> </span><br><span> romstage-y += ../baseboard/romstage.c</span><br><span style="color: hsl(120, 100%, 40%);">+romstage-y += ../baseboard/OemCustomize.c</span><br><span> </span><br><span> ramstage-y += ../baseboard/mainboard.c</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/27424">change 27424</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/27424"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: Ib692d202a7fe67195a390553f70d60a9d955b6d8 </div>
<div style="display:none"> Gerrit-Change-Number: 27424 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Martin Roth <martinroth@google.com> </div>