<p>Patrick Rudolph has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/27425">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">[WIP]mb/facebook/satima: Add new port<br><br>Add support for satima.<br><br>TODO: Fill in correct devicetree values<br><br>Change-Id: I4f972d59ac2243823a77f614c4f92c1666185705<br>Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com><br>---<br>A src/mainboard/facebook/satima/Kconfig<br>A src/mainboard/facebook/satima/Kconfig.name<br>A src/mainboard/facebook/satima/Makefile.inc<br>A src/mainboard/facebook/satima/bdk_devicetree.c<br>A src/mainboard/facebook/satima/board.fmd<br>A src/mainboard/facebook/satima/board_info.txt<br>A src/mainboard/facebook/satima/bootblock.c<br>A src/mainboard/facebook/satima/cn81xx-linux.dtsi<br>A src/mainboard/facebook/satima/death.c<br>A src/mainboard/facebook/satima/devicetree.cb<br>A src/mainboard/facebook/satima/mainboard.c<br>A src/mainboard/facebook/satima/memlayout.ld<br>A src/mainboard/facebook/satima/romstage.c<br>A src/mainboard/facebook/satima/sff8104-linux.dts<br>14 files changed, 1,371 insertions(+), 0 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/27425/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/mainboard/facebook/satima/Kconfig b/src/mainboard/facebook/satima/Kconfig</span><br><span>new file mode 100644</span><br><span>index 0000000..9a6acc9</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/facebook/satima/Kconfig</span><br><span>@@ -0,0 +1,71 @@</span><br><span style="color: hsl(120, 100%, 40%);">+##</span><br><span style="color: hsl(120, 100%, 40%);">+## This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+##</span><br><span style="color: hsl(120, 100%, 40%);">+## Copyright 2018 Facebook, Inc.</span><br><span style="color: hsl(120, 100%, 40%);">+##</span><br><span style="color: hsl(120, 100%, 40%);">+## This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+## it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+## the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+##</span><br><span style="color: hsl(120, 100%, 40%);">+## This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+## but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+## GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+##</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+if BOARD_FACEBOOK_SATIMA</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+config BOARD_SPECIFIC_OPTIONS</span><br><span style="color: hsl(120, 100%, 40%);">+ def_bool y</span><br><span style="color: hsl(120, 100%, 40%);">+ select BOARD_ROMSIZE_KB_16384</span><br><span style="color: hsl(120, 100%, 40%);">+ select COMMON_CBFS_SPI_WRAPPER</span><br><span style="color: hsl(120, 100%, 40%);">+ select RTC</span><br><span style="color: hsl(120, 100%, 40%);">+ select SOC_CAVIUM_CN81XX</span><br><span style="color: hsl(120, 100%, 40%);">+ select SPI_FLASH</span><br><span style="color: hsl(120, 100%, 40%);">+ select SPI_FLASH_WINBOND</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+config MAINBOARD_DIR</span><br><span style="color: hsl(120, 100%, 40%);">+ string</span><br><span style="color: hsl(120, 100%, 40%);">+ default "facebook/satima"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+config MAINBOARD_VENDOR</span><br><span style="color: hsl(120, 100%, 40%);">+ string</span><br><span style="color: hsl(120, 100%, 40%);">+ default "Facebook"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+config DRAM_SIZE_MB</span><br><span style="color: hsl(120, 100%, 40%);">+ int</span><br><span style="color: hsl(120, 100%, 40%);">+ default 8192</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+config BOOT_DEVICE_SPI_FLASH_BUS</span><br><span style="color: hsl(120, 100%, 40%);">+ int</span><br><span style="color: hsl(120, 100%, 40%);">+ default 0</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+config CONSOLE_SERIAL_UART_ADDRESS</span><br><span style="color: hsl(120, 100%, 40%);">+ hex</span><br><span style="color: hsl(120, 100%, 40%);">+ depends on DRIVERS_UART</span><br><span style="color: hsl(120, 100%, 40%);">+ default 0x87E028000000</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+config UART_FOR_CONSOLE</span><br><span style="color: hsl(120, 100%, 40%);">+ int</span><br><span style="color: hsl(120, 100%, 40%);">+ depends on DRIVERS_UART</span><br><span style="color: hsl(120, 100%, 40%);">+ default 0</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+config FMDFILE</span><br><span style="color: hsl(120, 100%, 40%);">+ string</span><br><span style="color: hsl(120, 100%, 40%);">+ default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/board.fmd"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+config MAX_CPUS</span><br><span style="color: hsl(120, 100%, 40%);">+ default 4</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+##########################################################</span><br><span style="color: hsl(120, 100%, 40%);">+#### Update below when adding a new derivative board. ####</span><br><span style="color: hsl(120, 100%, 40%);">+##########################################################</span><br><span style="color: hsl(120, 100%, 40%);">+config DEVICETREE</span><br><span style="color: hsl(120, 100%, 40%);">+ string</span><br><span style="color: hsl(120, 100%, 40%);">+ default "devicetree.cb"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+config MAINBOARD_PART_NUMBER</span><br><span style="color: hsl(120, 100%, 40%);">+ string</span><br><span style="color: hsl(120, 100%, 40%);">+ default "SATIMA"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+endif</span><br><span>diff --git a/src/mainboard/facebook/satima/Kconfig.name b/src/mainboard/facebook/satima/Kconfig.name</span><br><span>new file mode 100644</span><br><span>index 0000000..8830cda</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/facebook/satima/Kconfig.name</span><br><span>@@ -0,0 +1,2 @@</span><br><span style="color: hsl(120, 100%, 40%);">+config BOARD_FACEBOOK_SATIMA</span><br><span style="color: hsl(120, 100%, 40%);">+ bool "Satima"</span><br><span>diff --git a/src/mainboard/facebook/satima/Makefile.inc b/src/mainboard/facebook/satima/Makefile.inc</span><br><span>new file mode 100644</span><br><span>index 0000000..bc4ece3</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/facebook/satima/Makefile.inc</span><br><span>@@ -0,0 +1,42 @@</span><br><span style="color: hsl(120, 100%, 40%);">+##</span><br><span style="color: hsl(120, 100%, 40%);">+## This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+##</span><br><span style="color: hsl(120, 100%, 40%);">+## Copyright 2017-present Facebook, Inc.</span><br><span style="color: hsl(120, 100%, 40%);">+##</span><br><span style="color: hsl(120, 100%, 40%);">+## This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+## it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+## the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+##</span><br><span style="color: hsl(120, 100%, 40%);">+## This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+## but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+## GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+##</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+bootblock-y += bootblock.c</span><br><span style="color: hsl(120, 100%, 40%);">+bootblock-y += memlayout.ld</span><br><span style="color: hsl(120, 100%, 40%);">+bootblock-y += death.c</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+romstage-y += memlayout.ld</span><br><span style="color: hsl(120, 100%, 40%);">+romstage-y += romstage.c</span><br><span style="color: hsl(120, 100%, 40%);">+romstage-y += bdk_devicetree.c</span><br><span style="color: hsl(120, 100%, 40%);">+romstage-y += death.c</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ramstage-y += mainboard.c</span><br><span style="color: hsl(120, 100%, 40%);">+ramstage-y += memlayout.ld</span><br><span style="color: hsl(120, 100%, 40%);">+ramstage-y += bdk_devicetree.c</span><br><span style="color: hsl(120, 100%, 40%);">+ramstage-y += death.c</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+verstage-y += memlayout.ld</span><br><span style="color: hsl(120, 100%, 40%);">+verstage-y += death.c</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+MB_DIR = src/mainboard/$(MAINBOARDDIR)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+LINUX_DTB = sff8104-linux.dtb</span><br><span style="color: hsl(120, 100%, 40%);">+build/$(LINUX_DTB):</span><br><span style="color: hsl(120, 100%, 40%);">+ # FIXME: why isn't this producing the correct size DTB?</span><br><span style="color: hsl(120, 100%, 40%);">+ dtc -p 4096 -I dts -O dtb -o build/$(LINUX_DTB) -i $(MB_DIR) $(MB_DIR)/$(patsubst %.dtb,%.dts,$(LINUX_DTB))</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+cbfs-files-y += $(LINUX_DTB)</span><br><span style="color: hsl(120, 100%, 40%);">+$(LINUX_DTB)-file := build/$(LINUX_DTB)</span><br><span style="color: hsl(120, 100%, 40%);">+$(LINUX_DTB)-type := raw</span><br><span>diff --git a/src/mainboard/facebook/satima/bdk_devicetree.c b/src/mainboard/facebook/satima/bdk_devicetree.c</span><br><span>new file mode 100644</span><br><span>index 0000000..6b8a7e4</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/facebook/satima/bdk_devicetree.c</span><br><span>@@ -0,0 +1,126 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright 2017-present Facebook, Inc.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// This file is automatically generated.</span><br><span style="color: hsl(120, 100%, 40%);">+// DO NOT EDIT BY HAND.</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <bdk-devicetree.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+const struct bdk_devicetree_key_value devtree[] = {</span><br><span style="color: hsl(120, 100%, 40%);">+{"DDR-TEST-BOOT", "0"},</span><br><span style="color: hsl(120, 100%, 40%);">+{"DDR-CONFIG-DQX-CTL", "0x4"},</span><br><span style="color: hsl(120, 100%, 40%);">+{"DDR-CONFIG-WODT-MASK.RANKS2.DIMMS2", "0xc0c0303"},</span><br><span style="color: hsl(120, 100%, 40%);">+{"DDR-CONFIG-WODT-MASK.RANKS4.DIMMS1", "0x1030203"},</span><br><span style="color: hsl(120, 100%, 40%);">+{"DDR-CONFIG-MODE1-RTT-WR.RANKS1.DIMMS1.RANK0", "0x4"},</span><br><span style="color: hsl(120, 100%, 40%);">+{"DDR-CONFIG-MODE1-RTT-WR.RANKS1.DIMMS2.RANK0", "0x4"},</span><br><span style="color: hsl(120, 100%, 40%);">+{"DDR-CONFIG-MODE1-RTT-WR.RANKS1.DIMMS2.RANK2", "0x4"},</span><br><span style="color: hsl(120, 100%, 40%);">+{"DDR-CONFIG-MODE1-RTT-WR.RANKS2.DIMMS1.RANK0", "0x2"},</span><br><span style="color: hsl(120, 100%, 40%);">+{"DDR-CONFIG-MODE1-RTT-WR.RANKS2.DIMMS1.RANK1", "0x2"},</span><br><span style="color: hsl(120, 100%, 40%);">+{"DDR-CONFIG-MODE1-RTT-WR.RANKS2.DIMMS2", "0x2"},</span><br><span style="color: hsl(120, 100%, 40%);">+{"DDR-CONFIG-MODE1-RTT-WR.RANKS4", "0x1"},</span><br><span style="color: hsl(120, 100%, 40%);">+{"DDR-CONFIG-MODE1-DIC.RANKS4.DIMMS1", "0x1"},</span><br><span style="color: hsl(120, 100%, 40%);">+{"DDR-CONFIG-MODE1-RTT-NOM.RANKS2.DIMMS2", "0x2"},</span><br><span style="color: hsl(120, 100%, 40%);">+{"DDR-CONFIG-MODE1-RTT-NOM.RANKS4.DIMMS1.RANK0", "0x4"},</span><br><span style="color: hsl(120, 100%, 40%);">+{"DDR-CONFIG-MODE1-RTT-NOM.RANKS4.DIMMS1.RANK2", "0x4"},</span><br><span style="color: hsl(120, 100%, 40%);">+{"DDR-CONFIG-MODE2-RTT-PARK.RANKS1.DIMMS1.RANK0", "0x1"},</span><br><span style="color: hsl(120, 100%, 40%);">+{"DDR-CONFIG-MODE2-RTT-PARK.RANKS1.DIMMS2.RANK0", "0x5"},</span><br><span style="color: hsl(120, 100%, 40%);">+{"DDR-CONFIG-MODE2-RTT-PARK.RANKS1.DIMMS2.RANK2", "0x5"},</span><br><span style="color: hsl(120, 100%, 40%);">+{"DDR-CONFIG-MODE2-RTT-PARK.RANKS2.DIMMS1.RANK0", "0x2"},</span><br><span style="color: hsl(120, 100%, 40%);">+{"DDR-CONFIG-MODE2-RTT-PARK.RANKS2.DIMMS1.RANK1", "0x2"},</span><br><span style="color: hsl(120, 100%, 40%);">+{"DDR-CONFIG-MODE2-RTT-PARK.RANKS2.DIMMS2", "0x1"},</span><br><span style="color: hsl(120, 100%, 40%);">+{"DDR-CONFIG-MODE2-RTT-PARK.RANKS4.DIMMS1.RANK0", "0x6"},</span><br><span style="color: hsl(120, 100%, 40%);">+{"DDR-CONFIG-MODE2-RTT-PARK.RANKS4.DIMMS1.RANK1", "0x6"},</span><br><span style="color: hsl(120, 100%, 40%);">+{"DDR-CONFIG-MODE2-VREF-VALUE.RANKS1.DIMMS1.RANK0", "0x22"},</span><br><span style="color: hsl(120, 100%, 40%);">+{"DDR-CONFIG-MODE2-VREF-VALUE.RANKS1.DIMMS2.RANK0", "0x1f"},</span><br><span style="color: hsl(120, 100%, 40%);">+{"DDR-CONFIG-MODE2-VREF-VALUE.RANKS1.DIMMS2.RANK2", "0x1f"},</span><br><span style="color: hsl(120, 100%, 40%);">+{"DDR-CONFIG-MODE2-VREF-VALUE.RANKS2.DIMMS1.RANK0", "0x19"},</span><br><span style="color: hsl(120, 100%, 40%);">+{"DDR-CONFIG-MODE2-VREF-VALUE.RANKS2.DIMMS1.RANK1", "0x19"},</span><br><span style="color: hsl(120, 100%, 40%);">+{"DDR-CONFIG-MODE2-VREF-VALUE.RANKS2.DIMMS2", "0x19"},</span><br><span style="color: hsl(120, 100%, 40%);">+{"DDR-CONFIG-MODE2-VREF-VALUE.RANKS4.DIMMS1.RANK0", "0x1f"},</span><br><span style="color: hsl(120, 100%, 40%);">+{"DDR-CONFIG-MODE2-VREF-VALUE.RANKS4.DIMMS1.RANK1", "0x1f"},</span><br><span style="color: hsl(120, 100%, 40%);">+{"DDR-CONFIG-RODT-CTL.RANKS1.DIMMS1", "0x7"},</span><br><span style="color: hsl(120, 100%, 40%);">+{"DDR-CONFIG-RODT-CTL.RANKS1.DIMMS2", "0x3"},</span><br><span style="color: hsl(120, 100%, 40%);">+{"DDR-CONFIG-RODT-CTL.RANKS2.DIMMS1", "0x3"},</span><br><span style="color: hsl(120, 100%, 40%);">+{"DDR-CONFIG-RODT-CTL.RANKS2.DIMMS2", "0x7"},</span><br><span style="color: hsl(120, 100%, 40%);">+{"DDR-CONFIG-RODT-CTL.RANKS4.DIMMS1", "0x7"},</span><br><span style="color: hsl(120, 100%, 40%);">+{"DDR-CONFIG-RODT-MASK.RANKS2.DIMMS2", "0x4080102"},</span><br><span style="color: hsl(120, 100%, 40%);">+{"DDR-CONFIG-RODT-MASK.RANKS4.DIMMS1", "0x1010202"},</span><br><span style="color: hsl(120, 100%, 40%);">+{"DDR-CONFIG-CUSTOM-MIN-RTT-NOM-IDX", "0x1"},</span><br><span style="color: hsl(120, 100%, 40%);">+{"DDR-CONFIG-CUSTOM-MAX-RTT-NOM-IDX", "0x7"},</span><br><span style="color: hsl(120, 100%, 40%);">+{"DDR-CONFIG-CUSTOM-MIN-RODT-CTL", "0x1"},</span><br><span style="color: hsl(120, 100%, 40%);">+{"DDR-CONFIG-CUSTOM-MAX-RODT-CTL", "0x7"},</span><br><span style="color: hsl(120, 100%, 40%);">+{"DDR-CONFIG-CUSTOM-CK-CTL", "0x4"},</span><br><span style="color: hsl(120, 100%, 40%);">+{"DDR-CONFIG-CUSTOM-CMD-CTL", "0x4"},</span><br><span style="color: hsl(120, 100%, 40%);">+{"DDR-CONFIG-CUSTOM-CTL-CTL", "0x4"},</span><br><span style="color: hsl(120, 100%, 40%);">+{"DDR-CONFIG-CUSTOM-OFFSET-EN", "0x1"},</span><br><span style="color: hsl(120, 100%, 40%);">+{"DDR-CONFIG-CUSTOM-OFFSET", "0x2"},</span><br><span style="color: hsl(120, 100%, 40%);">+{"DDR-CONFIG-CUSTOM-DDR2T", "0x1"},</span><br><span style="color: hsl(120, 100%, 40%);">+{"DDR-CONFIG-CUSTOM-MAXIMUM-ADJACENT-RLEVEL-DELAY-INCREMENT", "0x2"},</span><br><span style="color: hsl(120, 100%, 40%);">+{"DDR-CONFIG-CUSTOM-FPRCH2", "0x2"},</span><br><span style="color: hsl(120, 100%, 40%);">+{"PHY-ADDRESS.N0.BGX0.P0", "0xff000010"},</span><br><span style="color: hsl(120, 100%, 40%);">+{"PHY-ADDRESS.N0.BGX0.P1", "0xff000011"},</span><br><span style="color: hsl(120, 100%, 40%);">+{"PHY-ADDRESS.N0.BGX0.P2", "0xff000012"},</span><br><span style="color: hsl(120, 100%, 40%);">+{"PHY-ADDRESS.N0.BGX0.P3", "0xff000013"},</span><br><span style="color: hsl(120, 100%, 40%);">+{"PHY-ADDRESS.N0.BGX1.P0", "0xff002014"},</span><br><span style="color: hsl(120, 100%, 40%);">+{"PHY-ADDRESS.N0.BGX1.P1", "0xff002014"},</span><br><span style="color: hsl(120, 100%, 40%);">+{"PHY-ADDRESS.N0.BGX2.P0", "0xff000000"},</span><br><span style="color: hsl(120, 100%, 40%);">+{"BGX-ENABLE.N0.BGX0.P0", "1"},</span><br><span style="color: hsl(120, 100%, 40%);">+{"BGX-ENABLE.N0.BGX0.P1", "1"},</span><br><span style="color: hsl(120, 100%, 40%);">+{"BGX-ENABLE.N0.BGX0.P2", "1"},</span><br><span style="color: hsl(120, 100%, 40%);">+{"BGX-ENABLE.N0.BGX0.P3", "1"},</span><br><span style="color: hsl(120, 100%, 40%);">+{"BGX-ENABLE.N0.BGX1.P0", "0"},</span><br><span style="color: hsl(120, 100%, 40%);">+{"BGX-ENABLE.N0.BGX1.P1", "0"},</span><br><span style="color: hsl(120, 100%, 40%);">+{"BGX-ENABLE.N0.BGX2.P0", "0"},</span><br><span style="color: hsl(120, 100%, 40%);">+{"BDK-NUM-PACKET-BUFFERS", "0x1000"},</span><br><span style="color: hsl(120, 100%, 40%);">+{"BDK-PACKET-BUFFER-SIZE", "0x400"},</span><br><span style="color: hsl(120, 100%, 40%);">+{"BDK-SHOW-LINK-STATUS", "1"},</span><br><span style="color: hsl(120, 100%, 40%);">+{"BDK-COREMASK", "0"},</span><br><span style="color: hsl(120, 100%, 40%);">+{"MULTI-NODE", "0"},</span><br><span style="color: hsl(120, 100%, 40%);">+{"QLM-AUTO-CONFIG", "0"},</span><br><span style="color: hsl(120, 100%, 40%);">+{"QLM-DIP-AUTO-CONFIG", "0"},</span><br><span style="color: hsl(120, 100%, 40%);">+{"DDR-SPEED.N0", "1333"},</span><br><span style="color: hsl(120, 100%, 40%);">+{"DDR-CONFIG-SPD-ADDR.DIMM0.LMC0", "0x1050"},</span><br><span style="color: hsl(120, 100%, 40%);">+{"USB-PWR-GPIO.N0.PORT0", "12"},</span><br><span style="color: hsl(120, 100%, 40%);">+{"USB-PWR-GPIO-POLARITY.N0.PORT0", "0"},</span><br><span style="color: hsl(120, 100%, 40%);">+{"USB-REFCLK-SRC.N0.PORT0", "0"},</span><br><span style="color: hsl(120, 100%, 40%);">+{"GPIO-PIN-SELECT-GPIO15", "0x24f"},</span><br><span style="color: hsl(120, 100%, 40%);">+{"GPIO-PIN-SELECT-GPIO16", "0x24e"},</span><br><span style="color: hsl(120, 100%, 40%);">+{"GPIO-PIN-SELECT-GPIO17", "0x24b"},</span><br><span style="color: hsl(120, 100%, 40%);">+{"GPIO-PIN-SELECT-GPIO18", "0x247"},</span><br><span style="color: hsl(120, 100%, 40%);">+{"GPIO-PIN-SELECT-GPIO19", "0x24d"},</span><br><span style="color: hsl(120, 100%, 40%);">+{"GPIO-PIN-SELECT-GPIO20", "0x24c"},</span><br><span style="color: hsl(120, 100%, 40%);">+{"GPIO-PIN-SELECT-GPIO37", "0x24a"},</span><br><span style="color: hsl(120, 100%, 40%);">+{"GPIO-PIN-SELECT-GPIO38", "0x246"},</span><br><span style="color: hsl(120, 100%, 40%);">+{"GPIO-PIN-SELECT-GPIO7", "0xe1"},</span><br><span style="color: hsl(120, 100%, 40%);">+{"GPIO-PIN-SELECT-GPIO24", "0xeb"},</span><br><span style="color: hsl(120, 100%, 40%);">+{"GPIO-PIN-SELECT-GPIO27", "0xed"},</span><br><span style="color: hsl(120, 100%, 40%);">+{"GPIO-PIN-SELECT-GPIO28", "0xe3"},</span><br><span style="color: hsl(120, 100%, 40%);">+{"GPIO-PIN-SELECT-GPIO29", "0xe0"},</span><br><span style="color: hsl(120, 100%, 40%);">+{"GPIO-PIN-SELECT-GPIO30", "0xe2"},</span><br><span style="color: hsl(120, 100%, 40%);">+{"GPIO-PIN-SELECT-GPIO40", "0x112"},</span><br><span style="color: hsl(120, 100%, 40%);">+{"GPIO-PIN-SELECT-GPIO41", "0x113"},</span><br><span style="color: hsl(120, 100%, 40%);">+{"GPIO-PIN-SELECT-GPIO42", "0x114"},</span><br><span style="color: hsl(120, 100%, 40%);">+{"GPIO-PIN-SELECT-GPIO43", "0x115"},</span><br><span style="color: hsl(120, 100%, 40%);">+{"GPIO-PIN-SELECT-GPIO44", "0x116"},</span><br><span style="color: hsl(120, 100%, 40%);">+{"GPIO-PIN-SELECT-GPIO45", "0x117"},</span><br><span style="color: hsl(120, 100%, 40%);">+{"GPIO-PIN-SELECT-GPIO46", "0x118"},</span><br><span style="color: hsl(120, 100%, 40%);">+{"GPIO-PIN-SELECT-GPIO47", "0x119"},</span><br><span style="color: hsl(120, 100%, 40%);">+{"GPIO-POLARITY-GPIO7", "1"},</span><br><span style="color: hsl(120, 100%, 40%);">+{"GPIO-POLARITY-GPIO27", "1"},</span><br><span style="color: hsl(120, 100%, 40%);">+{"GPIO-POLARITY-GPIO28", "1"},</span><br><span style="color: hsl(120, 100%, 40%);">+{"GPIO-POLARITY-GPIO30", "1"},</span><br><span style="color: hsl(120, 100%, 40%);">+{0, 0},</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span>diff --git a/src/mainboard/facebook/satima/board.fmd b/src/mainboard/facebook/satima/board.fmd</span><br><span>new file mode 100644</span><br><span>index 0000000..3a7dbfc</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/facebook/satima/board.fmd</span><br><span>@@ -0,0 +1,27 @@</span><br><span style="color: hsl(120, 100%, 40%);">+FLASH@0x0 16M {</span><br><span style="color: hsl(120, 100%, 40%);">+ WP_RO@0x0 0x800000 {</span><br><span style="color: hsl(120, 100%, 40%);">+ RO_SECTION@0x0 0x800000 {</span><br><span style="color: hsl(120, 100%, 40%);">+ # bootblock includes trusted/non-trusted CLIB, CSIB,</span><br><span style="color: hsl(120, 100%, 40%);">+ # and BL1FWs packaged in</span><br><span style="color: hsl(120, 100%, 40%);">+ # src/soc/cavium/common/Makefile.inc.</span><br><span style="color: hsl(120, 100%, 40%);">+ BOOTBLOCK@0x10000 0x70000</span><br><span style="color: hsl(120, 100%, 40%);">+ FMAP@0x80000 0x1000</span><br><span style="color: hsl(120, 100%, 40%);">+ COREBOOT(CBFS)@0x90000 0x770000</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ RW_SECTION_A@0x800000 0x100000 {</span><br><span style="color: hsl(120, 100%, 40%);">+ VBLOCK_A@0x0 0x2000</span><br><span style="color: hsl(120, 100%, 40%);">+ FW_MAIN_A(CBFS)@0x2000 0xfdf00</span><br><span style="color: hsl(120, 100%, 40%);">+ RW_FWID_A@0xfff00 0x100</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ RW_SECTION_B@0x900000 0x100000 {</span><br><span style="color: hsl(120, 100%, 40%);">+ VBLOCK_B@0x0 0x2000</span><br><span style="color: hsl(120, 100%, 40%);">+ FW_MAIN_B(CBFS)@0x2000 0xfdf00</span><br><span style="color: hsl(120, 100%, 40%);">+ RW_FWID_B@0xfff00 0x100</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ RW_ELOG@0xfd0000 0x1000</span><br><span style="color: hsl(120, 100%, 40%);">+ RW_SHARED@0xfe0000 0x10000 {</span><br><span style="color: hsl(120, 100%, 40%);">+ SHARED_DATA@0x0 0x10000</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ RW_NVRAM@0xff0000 0x10000</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span>diff --git a/src/mainboard/facebook/satima/board_info.txt b/src/mainboard/facebook/satima/board_info.txt</span><br><span>new file mode 100644</span><br><span>index 0000000..6d0d0a8</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/facebook/satima/board_info.txt</span><br><span>@@ -0,0 +1,6 @@</span><br><span style="color: hsl(120, 100%, 40%);">+Vendor name: Facebook</span><br><span style="color: hsl(120, 100%, 40%);">+Board name: Satima</span><br><span style="color: hsl(120, 100%, 40%);">+Category: network</span><br><span style="color: hsl(120, 100%, 40%);">+ROM protocol: SPI</span><br><span style="color: hsl(120, 100%, 40%);">+ROM socketed: n</span><br><span style="color: hsl(120, 100%, 40%);">+Flashrom support: y</span><br><span>diff --git a/src/mainboard/facebook/satima/bootblock.c b/src/mainboard/facebook/satima/bootblock.c</span><br><span>new file mode 100644</span><br><span>index 0000000..a8e6961</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/facebook/satima/bootblock.c</span><br><span>@@ -0,0 +1,44 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright 2018 Facebook, Inc.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <bootblock_common.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/soc.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/spi.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/uart.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+void bootblock_mainboard_early_init(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ if (IS_ENABLED(CONFIG_BOOTBLOCK_CONSOLE)) {</span><br><span style="color: hsl(120, 100%, 40%);">+ if (!uart_is_enabled(CONFIG_UART_FOR_CONSOLE))</span><br><span style="color: hsl(120, 100%, 40%);">+ uart_setup(CONFIG_UART_FOR_CONSOLE, CONFIG_TTYS0_BAUD);</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static void configure_spi_flash(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ /* FIXME: Only tested on EM100 Pro */</span><br><span style="color: hsl(120, 100%, 40%);">+ spi_init_custom(0, // bus</span><br><span style="color: hsl(120, 100%, 40%);">+ 12500000, // speed Hz</span><br><span style="color: hsl(120, 100%, 40%);">+ 0, // idle low disabled</span><br><span style="color: hsl(120, 100%, 40%);">+ 0, // zero idle cycles between transfers</span><br><span style="color: hsl(120, 100%, 40%);">+ 0, // MSB first</span><br><span style="color: hsl(120, 100%, 40%);">+ 0, // Chip select 0</span><br><span style="color: hsl(120, 100%, 40%);">+ 1); // assert is high</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+void bootblock_mainboard_init(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ configure_spi_flash();</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span>diff --git a/src/mainboard/facebook/satima/cn81xx-linux.dtsi b/src/mainboard/facebook/satima/cn81xx-linux.dtsi</span><br><span>new file mode 100644</span><br><span>index 0000000..d82b5ac</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/facebook/satima/cn81xx-linux.dtsi</span><br><span>@@ -0,0 +1,496 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * Cavium Thunder DTS file - Thunder SoC description</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2016, Cavium Inc.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is dual-licensed: you can use it either under the terms</span><br><span style="color: hsl(120, 100%, 40%);">+ * of the GPL or the X11 license, at your option. Note that this dual</span><br><span style="color: hsl(120, 100%, 40%);">+ * licensing only applies to this file, and not this project as a</span><br><span style="color: hsl(120, 100%, 40%);">+ * whole.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * a) This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Or, alternatively,</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * b) Permission is hereby granted, free of charge, to any person</span><br><span style="color: hsl(120, 100%, 40%);">+ * obtaining a copy of this software and associated documentation</span><br><span style="color: hsl(120, 100%, 40%);">+ * files (the "Software"), to deal in the Software without</span><br><span style="color: hsl(120, 100%, 40%);">+ * restriction, including without limitation the rights to use,</span><br><span style="color: hsl(120, 100%, 40%);">+ * copy, modify, merge, publish, distribute, sublicense, and/or</span><br><span style="color: hsl(120, 100%, 40%);">+ * sell copies of the Software, and to permit persons to whom the</span><br><span style="color: hsl(120, 100%, 40%);">+ * Software is furnished to do so, subject to the following</span><br><span style="color: hsl(120, 100%, 40%);">+ * conditions:</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * The above copyright notice and this permission notice shall be</span><br><span style="color: hsl(120, 100%, 40%);">+ * included in all copies or substantial portions of the Software.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,</span><br><span style="color: hsl(120, 100%, 40%);">+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES</span><br><span style="color: hsl(120, 100%, 40%);">+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND</span><br><span style="color: hsl(120, 100%, 40%);">+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT</span><br><span style="color: hsl(120, 100%, 40%);">+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,</span><br><span style="color: hsl(120, 100%, 40%);">+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING</span><br><span style="color: hsl(120, 100%, 40%);">+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR</span><br><span style="color: hsl(120, 100%, 40%);">+ * OTHER DEALINGS IN THE SOFTWARE.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/ {</span><br><span style="color: hsl(120, 100%, 40%);">+ model = "Cavium ThunderX CN81XX board";</span><br><span style="color: hsl(120, 100%, 40%);">+ compatible = "cavium,thunder-81xx";</span><br><span style="color: hsl(120, 100%, 40%);">+ interrupt-parent = <&gic0>;</span><br><span style="color: hsl(120, 100%, 40%);">+ #address-cells = <2>;</span><br><span style="color: hsl(120, 100%, 40%);">+ #size-cells = <2>;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ psci {</span><br><span style="color: hsl(120, 100%, 40%);">+ compatible = "arm,psci-0.2";</span><br><span style="color: hsl(120, 100%, 40%);">+ method = "smc";</span><br><span style="color: hsl(120, 100%, 40%);">+ };</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ cpus {</span><br><span style="color: hsl(120, 100%, 40%);">+ #address-cells = <2>;</span><br><span style="color: hsl(120, 100%, 40%);">+ #size-cells = <0>;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ cpu-map {</span><br><span style="color: hsl(120, 100%, 40%);">+ cluster0 {</span><br><span style="color: hsl(120, 100%, 40%);">+ core0 {</span><br><span style="color: hsl(120, 100%, 40%);">+ cpu = <&CPU0>;</span><br><span style="color: hsl(120, 100%, 40%);">+ };</span><br><span style="color: hsl(120, 100%, 40%);">+ core1 {</span><br><span style="color: hsl(120, 100%, 40%);">+ cpu = <&CPU1>;</span><br><span style="color: hsl(120, 100%, 40%);">+ };</span><br><span style="color: hsl(120, 100%, 40%);">+ core2 {</span><br><span style="color: hsl(120, 100%, 40%);">+ cpu = <&CPU2>;</span><br><span style="color: hsl(120, 100%, 40%);">+ };</span><br><span style="color: hsl(120, 100%, 40%);">+ core3 {</span><br><span style="color: hsl(120, 100%, 40%);">+ cpu = <&CPU3>;</span><br><span style="color: hsl(120, 100%, 40%);">+ };</span><br><span style="color: hsl(120, 100%, 40%);">+ };</span><br><span style="color: hsl(120, 100%, 40%);">+ };</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ CPU0: cpu@0 {</span><br><span style="color: hsl(120, 100%, 40%);">+ device_type = "cpu";</span><br><span style="color: hsl(120, 100%, 40%);">+ compatible = "cavium,thunder", "arm,armv8";</span><br><span style="color: hsl(120, 100%, 40%);">+ reg = <0x0 0x000>;</span><br><span style="color: hsl(120, 100%, 40%);">+ enable-method = "psci";</span><br><span style="color: hsl(120, 100%, 40%);">+ /* socket 0 */</span><br><span style="color: hsl(120, 100%, 40%);">+ numa-node-id = <0>;</span><br><span style="color: hsl(120, 100%, 40%);">+ next-level-cache = <&thunderx_L2_0>;</span><br><span style="color: hsl(120, 100%, 40%);">+ };</span><br><span style="color: hsl(120, 100%, 40%);">+ CPU1: cpu@1 {</span><br><span style="color: hsl(120, 100%, 40%);">+ device_type = "cpu";</span><br><span style="color: hsl(120, 100%, 40%);">+ compatible = "cavium,thunder", "arm,armv8";</span><br><span style="color: hsl(120, 100%, 40%);">+ reg = <0x0 0x001>;</span><br><span style="color: hsl(120, 100%, 40%);">+ enable-method = "psci";</span><br><span style="color: hsl(120, 100%, 40%);">+ numa-node-id = <0>;</span><br><span style="color: hsl(120, 100%, 40%);">+ next-level-cache = <&thunderx_L2_0>;</span><br><span style="color: hsl(120, 100%, 40%);">+ };</span><br><span style="color: hsl(120, 100%, 40%);">+ CPU2: cpu@2 {</span><br><span style="color: hsl(120, 100%, 40%);">+ device_type = "cpu";</span><br><span style="color: hsl(120, 100%, 40%);">+ compatible = "cavium,thunder", "arm,armv8";</span><br><span style="color: hsl(120, 100%, 40%);">+ reg = <0x0 0x002>;</span><br><span style="color: hsl(120, 100%, 40%);">+ enable-method = "psci";</span><br><span style="color: hsl(120, 100%, 40%);">+ numa-node-id = <0>;</span><br><span style="color: hsl(120, 100%, 40%);">+ next-level-cache = <&thunderx_L2_0>;</span><br><span style="color: hsl(120, 100%, 40%);">+ };</span><br><span style="color: hsl(120, 100%, 40%);">+ CPU3: cpu@3 {</span><br><span style="color: hsl(120, 100%, 40%);">+ device_type = "cpu";</span><br><span style="color: hsl(120, 100%, 40%);">+ compatible = "cavium,thunder", "arm,armv8";</span><br><span style="color: hsl(120, 100%, 40%);">+ reg = <0x0 0x003>;</span><br><span style="color: hsl(120, 100%, 40%);">+ enable-method = "psci";</span><br><span style="color: hsl(120, 100%, 40%);">+ numa-node-id = <0>;</span><br><span style="color: hsl(120, 100%, 40%);">+ next-level-cache = <&thunderx_L2_0>;</span><br><span style="color: hsl(120, 100%, 40%);">+ };</span><br><span style="color: hsl(120, 100%, 40%);">+ };</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ thunderx_L2_0: l2-cache0 {</span><br><span style="color: hsl(120, 100%, 40%);">+ compatible = "cache";</span><br><span style="color: hsl(120, 100%, 40%);">+ numa-node-id = <0>;</span><br><span style="color: hsl(120, 100%, 40%);">+ };</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ timer {</span><br><span style="color: hsl(120, 100%, 40%);">+ compatible = "arm,armv8-timer";</span><br><span style="color: hsl(120, 100%, 40%);">+ interrupts = <1 13 4>,</span><br><span style="color: hsl(120, 100%, 40%);">+ <1 14 4>,</span><br><span style="color: hsl(120, 100%, 40%);">+ <1 11 4>,</span><br><span style="color: hsl(120, 100%, 40%);">+ <1 10 4>;</span><br><span style="color: hsl(120, 100%, 40%);">+ };</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ pmu {</span><br><span style="color: hsl(120, 100%, 40%);">+ compatible = "cavium,thunder-pmu", "arm,armv8-pmuv3";</span><br><span style="color: hsl(120, 100%, 40%);">+ interrupts = <1 7 4>;</span><br><span style="color: hsl(120, 100%, 40%);">+ };</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ mmc_supply_3v3: mmc_supply_3v3 {</span><br><span style="color: hsl(120, 100%, 40%);">+ compatible = "regulator-fixed";</span><br><span style="color: hsl(120, 100%, 40%);">+ regulator-name = "mmc_supply_3v3";</span><br><span style="color: hsl(120, 100%, 40%);">+ regulator-min-microvolt = <3300000>;</span><br><span style="color: hsl(120, 100%, 40%);">+ regulator-max-microvolt = <3300000>;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ gpio = <&gpio_6_0 8 0>;</span><br><span style="color: hsl(120, 100%, 40%);">+ enable-active-high;</span><br><span style="color: hsl(120, 100%, 40%);">+ };</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ gic0: interrupt-controller@801000000000 {</span><br><span style="color: hsl(120, 100%, 40%);">+ compatible = "arm,gic-v3";</span><br><span style="color: hsl(120, 100%, 40%);">+ #interrupt-cells = <3>;</span><br><span style="color: hsl(120, 100%, 40%);">+ #address-cells = <2>;</span><br><span style="color: hsl(120, 100%, 40%);">+ #size-cells = <2>;</span><br><span style="color: hsl(120, 100%, 40%);">+ #redistributor-regions = <1>;</span><br><span style="color: hsl(120, 100%, 40%);">+ ranges;</span><br><span style="color: hsl(120, 100%, 40%);">+ interrupt-controller;</span><br><span style="color: hsl(120, 100%, 40%);">+ reg = <0x8010 0x00000000 0x0 0x010000>, /* GICD */</span><br><span style="color: hsl(120, 100%, 40%);">+ <0x8010 0x80000000 0x0 0x600000>; /* GICR */</span><br><span style="color: hsl(120, 100%, 40%);">+ interrupts = <1 9 4>;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ its: gic-its@801000020000 {</span><br><span style="color: hsl(120, 100%, 40%);">+ compatible = "arm,gic-v3-its";</span><br><span style="color: hsl(120, 100%, 40%);">+ reg = <0x8010 0x20000 0x0 0x200000>;</span><br><span style="color: hsl(120, 100%, 40%);">+ msi-controller;</span><br><span style="color: hsl(120, 100%, 40%);">+ numa-node-id = <0>;</span><br><span style="color: hsl(120, 100%, 40%);">+ };</span><br><span style="color: hsl(120, 100%, 40%);">+ };</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ soc@0 {</span><br><span style="color: hsl(120, 100%, 40%);">+ compatible = "simple-bus";</span><br><span style="color: hsl(120, 100%, 40%);">+ #address-cells = <2>;</span><br><span style="color: hsl(120, 100%, 40%);">+ #size-cells = <2>;</span><br><span style="color: hsl(120, 100%, 40%);">+ ranges;</span><br><span style="color: hsl(120, 100%, 40%);">+ numa-node-id = <0>;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ refclkuaa: refclkuaa {</span><br><span style="color: hsl(120, 100%, 40%);">+ compatible = "fixed-clock";</span><br><span style="color: hsl(120, 100%, 40%);">+ #clock-cells = <0>;</span><br><span style="color: hsl(120, 100%, 40%);">+ clock-frequency = <116640000>;</span><br><span style="color: hsl(120, 100%, 40%);">+ clock-output-names = "refclkuaa";</span><br><span style="color: hsl(120, 100%, 40%);">+ };</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ sclk: sclk {</span><br><span style="color: hsl(120, 100%, 40%);">+ compatible = "fixed-clock";</span><br><span style="color: hsl(120, 100%, 40%);">+ #clock-cells = <0>;</span><br><span style="color: hsl(120, 100%, 40%);">+ clock-frequency = <800000000>;</span><br><span style="color: hsl(120, 100%, 40%);">+ clock-output-names = "sclk";</span><br><span style="color: hsl(120, 100%, 40%);">+ };</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ uaa0: serial@87e028000000 {</span><br><span style="color: hsl(120, 100%, 40%);">+ compatible = "arm,pl011", "arm,primecell";</span><br><span style="color: hsl(120, 100%, 40%);">+ reg = <0x87e0 0x28000000 0x0 0x1000>;</span><br><span style="color: hsl(120, 100%, 40%);">+ interrupts = <0 5 4>;</span><br><span style="color: hsl(120, 100%, 40%);">+ clocks = <&refclkuaa>;</span><br><span style="color: hsl(120, 100%, 40%);">+ clock-names = "apb_pclk";</span><br><span style="color: hsl(120, 100%, 40%);">+ skip-init;</span><br><span style="color: hsl(120, 100%, 40%);">+ };</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ uaa1: serial@87e029000000 {</span><br><span style="color: hsl(120, 100%, 40%);">+ compatible = "arm,pl011", "arm,primecell";</span><br><span style="color: hsl(120, 100%, 40%);">+ reg = <0x87e0 0x29000000 0x0 0x1000>;</span><br><span style="color: hsl(120, 100%, 40%);">+ interrupts = <0 6 4>;</span><br><span style="color: hsl(120, 100%, 40%);">+ clocks = <&refclkuaa>;</span><br><span style="color: hsl(120, 100%, 40%);">+ clock-names = "apb_pclk";</span><br><span style="color: hsl(120, 100%, 40%);">+ skip-init;</span><br><span style="color: hsl(120, 100%, 40%);">+ };</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ uaa2: serial@87e02a000000 {</span><br><span style="color: hsl(120, 100%, 40%);">+ compatible = "arm,pl011", "arm,primecell";</span><br><span style="color: hsl(120, 100%, 40%);">+ reg = <0x87e0 0x2a000000 0x0 0x1000>;</span><br><span style="color: hsl(120, 100%, 40%);">+ interrupts = <0 7 4>;</span><br><span style="color: hsl(120, 100%, 40%);">+ clocks = <&refclkuaa>;</span><br><span style="color: hsl(120, 100%, 40%);">+ clock-names = "apb_pclk";</span><br><span style="color: hsl(120, 100%, 40%);">+ skip-init;</span><br><span style="color: hsl(120, 100%, 40%);">+ };</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ uaa3: serial@87e02b000000 {</span><br><span style="color: hsl(120, 100%, 40%);">+ compatible = "arm,pl011", "arm,primecell";</span><br><span style="color: hsl(120, 100%, 40%);">+ reg = <0x87e0 0x2b000000 0x0 0x1000>;</span><br><span style="color: hsl(120, 100%, 40%);">+ interrupts = <0 8 4>;</span><br><span style="color: hsl(120, 100%, 40%);">+ clocks = <&refclkuaa>;</span><br><span style="color: hsl(120, 100%, 40%);">+ clock-names = "apb_pclk";</span><br><span style="color: hsl(120, 100%, 40%);">+ skip-init;</span><br><span style="color: hsl(120, 100%, 40%);">+ };</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ watch-dog@8440000a0000 {</span><br><span style="color: hsl(120, 100%, 40%);">+ compatible = "arm,sbsa-gwdt";</span><br><span style="color: hsl(120, 100%, 40%);">+ reg = <0x8440 0xa0000 0x0 0x1000>, <0x8440 0xb0000 0x0 0x1000>;</span><br><span style="color: hsl(120, 100%, 40%);">+ interrupts = <0 9 4>;</span><br><span style="color: hsl(120, 100%, 40%);">+ };</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ pbus0: nor@0 {</span><br><span style="color: hsl(120, 100%, 40%);">+ compatible = "cfi-flash";</span><br><span style="color: hsl(120, 100%, 40%);">+ reg = <0x8000 0x0 0x0 0x800000>;</span><br><span style="color: hsl(120, 100%, 40%);">+ device-width = <1>;</span><br><span style="color: hsl(120, 100%, 40%);">+ bank-width = <1>;</span><br><span style="color: hsl(120, 100%, 40%);">+ clocks = <&sclk>;</span><br><span style="color: hsl(120, 100%, 40%);">+ };</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ smmu0@830000000000 {</span><br><span style="color: hsl(120, 100%, 40%);">+ compatible = "cavium,smmu-v2";</span><br><span style="color: hsl(120, 100%, 40%);">+ reg = <0x8300 0x0 0x0 0x2000000>;</span><br><span style="color: hsl(120, 100%, 40%);">+ #global-interrupts = <1>;</span><br><span style="color: hsl(120, 100%, 40%);">+ interrupts = <0 68 4>, <0 69 4>, <0 69 4>, <0 69 4>, <0 69 4>, <0 69 4>,</span><br><span style="color: hsl(120, 100%, 40%);">+ <0 69 4>, <0 69 4>, <0 69 4>, <0 69 4>, <0 69 4>, <0 69 4>,</span><br><span style="color: hsl(120, 100%, 40%);">+ <0 69 4>, <0 69 4>, <0 69 4>, <0 69 4>, <0 69 4>, <0 69 4>,</span><br><span style="color: hsl(120, 100%, 40%);">+ <0 69 4>, <0 69 4>, <0 69 4>, <0 69 4>, <0 69 4>, <0 69 4>,</span><br><span style="color: hsl(120, 100%, 40%);">+ <0 69 4>, <0 69 4>, <0 69 4>, <0 69 4>, <0 69 4>, <0 69 4>,</span><br><span style="color: hsl(120, 100%, 40%);">+ <0 69 4>, <0 69 4>, <0 69 4>, <0 69 4>, <0 69 4>, <0 69 4>,</span><br><span style="color: hsl(120, 100%, 40%);">+ <0 69 4>, <0 69 4>, <0 69 4>, <0 69 4>, <0 69 4>, <0 69 4>,</span><br><span style="color: hsl(120, 100%, 40%);">+ <0 69 4>, <0 69 4>, <0 69 4>, <0 69 4>, <0 69 4>, <0 69 4>,</span><br><span style="color: hsl(120, 100%, 40%);">+ <0 69 4>, <0 69 4>, <0 69 4>, <0 69 4>, <0 69 4>, <0 69 4>,</span><br><span style="color: hsl(120, 100%, 40%);">+ <0 69 4>, <0 69 4>, <0 69 4>, <0 69 4>, <0 69 4>, <0 69 4>,</span><br><span style="color: hsl(120, 100%, 40%);">+ <0 69 4>, <0 69 4>, <0 69 4>, <0 69 4>, <0 69 4>;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ mmu-masters = <&ecam0 0x100>,</span><br><span style="color: hsl(120, 100%, 40%);">+ <&pem0 0x200>,</span><br><span style="color: hsl(120, 100%, 40%);">+ <&pem1 0x300>,</span><br><span style="color: hsl(120, 100%, 40%);">+ <&pem2 0x400>;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ };</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ ecam0: pci@848000000000 {</span><br><span style="color: hsl(120, 100%, 40%);">+ compatible = "pci-host-ecam-generic";</span><br><span style="color: hsl(120, 100%, 40%);">+ device_type = "pci";</span><br><span style="color: hsl(120, 100%, 40%);">+ msi-parent = <&its>;</span><br><span style="color: hsl(120, 100%, 40%);">+ msi-map = <0 &its 0 0x10000>;</span><br><span style="color: hsl(120, 100%, 40%);">+ bus-range = <0 31>;</span><br><span style="color: hsl(120, 100%, 40%);">+ #size-cells = <2>;</span><br><span style="color: hsl(120, 100%, 40%);">+ #address-cells = <3>;</span><br><span style="color: hsl(120, 100%, 40%);">+ #stream-id-cells = <1>;</span><br><span style="color: hsl(120, 100%, 40%);">+ u-boot,dm-pre-reloc;</span><br><span style="color: hsl(120, 100%, 40%);">+ dma-coherent;</span><br><span style="color: hsl(120, 100%, 40%);">+ reg = <0x8480 0x00000000 0 0x02000000>; /* Configuration space */</span><br><span style="color: hsl(120, 100%, 40%);">+ ranges = <0x03000000 0x8010 0x00000000 0x8010 0x00000000 0x080 0x00000000>, /* mem ranges */</span><br><span style="color: hsl(120, 100%, 40%);">+ <0x03000000 0x8100 0x00000000 0x8100 0x00000000 0x80 0x00000000>, /* SATA */</span><br><span style="color: hsl(120, 100%, 40%);">+ <0x03000000 0x8680 0x00000000 0x8680 0x00000000 0x160 0x28000000>, /* UARTs */</span><br><span style="color: hsl(120, 100%, 40%);">+ <0x03000000 0x87e0 0x2c000000 0x87e0 0x2c000000 0x000 0x94000000>, /* PEMs */</span><br><span style="color: hsl(120, 100%, 40%);">+ <0x03000000 0x8400 0x00000000 0x8400 0x00000000 0x010 0x00000000>, /* RNM */</span><br><span style="color: hsl(120, 100%, 40%);">+ <0x03000000 0x8430 0x00000000 0x8430 0x00000000 0x02 0x00000000>, /* NIC0*/</span><br><span style="color: hsl(120, 100%, 40%);">+ <0x03000000 0x87e0 0xc6000000 0x87e0 0xc6000000 0x01f 0x3a000000>;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ mrml_bridge: mrml-bridge0@1,0 {</span><br><span style="color: hsl(120, 100%, 40%);">+ compatible = "pci-bridge", "cavium,thunder-8890-mrml-bridge";</span><br><span style="color: hsl(120, 100%, 40%);">+ #size-cells = <2>;</span><br><span style="color: hsl(120, 100%, 40%);">+ #address-cells = <3>;</span><br><span style="color: hsl(120, 100%, 40%);">+ ranges = <0x03000000 0x87e0 0x00000000 0x03000000 0x87e0 0x00000000 0x10 0x00000000>;</span><br><span style="color: hsl(120, 100%, 40%);">+ reg = <0x0800 0 0 0 0>; /* DEVFN = 0x08 (1:0) */</span><br><span style="color: hsl(120, 100%, 40%);">+ device_type = "pci";</span><br><span style="color: hsl(120, 100%, 40%);">+ u-boot,dm-pre-reloc;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ mdio-nexus@1,3 {</span><br><span style="color: hsl(120, 100%, 40%);">+ compatible = "cavium,thunder-8890-mdio-nexus";</span><br><span style="color: hsl(120, 100%, 40%);">+ #address-cells = <2>;</span><br><span style="color: hsl(120, 100%, 40%);">+ #size-cells = <2>;</span><br><span style="color: hsl(120, 100%, 40%);">+ reg = <0x0b00 0 0 0 0>; /* DEVFN = 0x0b (1:3) */</span><br><span style="color: hsl(120, 100%, 40%);">+ assigned-addresses = <0x03000000 0x87e0 0x05000000 0x0 0x800000>;</span><br><span style="color: hsl(120, 100%, 40%);">+ ranges = <0x87e0 0x05000000 0x03000000 0x87e0 0x05000000 0x0 0x800000>;</span><br><span style="color: hsl(120, 100%, 40%);">+ mdio0@87e005003800 {</span><br><span style="color: hsl(120, 100%, 40%);">+ compatible = "cavium,thunder-8890-mdio";</span><br><span style="color: hsl(120, 100%, 40%);">+ #address-cells = <1>;</span><br><span style="color: hsl(120, 100%, 40%);">+ #size-cells = <0>;</span><br><span style="color: hsl(120, 100%, 40%);">+ reg = <0x87e0 0x05003800 0x0 0x30>;</span><br><span style="color: hsl(120, 100%, 40%);">+ };</span><br><span style="color: hsl(120, 100%, 40%);">+ mdio1@87e005003880 {</span><br><span style="color: hsl(120, 100%, 40%);">+ compatible = "cavium,thunder-8890-mdio";</span><br><span style="color: hsl(120, 100%, 40%);">+ #address-cells = <1>;</span><br><span style="color: hsl(120, 100%, 40%);">+ #size-cells = <0>;</span><br><span style="color: hsl(120, 100%, 40%);">+ reg = <0x87e0 0x05003880 0x0 0x30>;</span><br><span style="color: hsl(120, 100%, 40%);">+ };</span><br><span style="color: hsl(120, 100%, 40%);">+ };</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ mmc_1_4: mmc@1,4 {</span><br><span style="color: hsl(120, 100%, 40%);">+ compatible = "cavium,thunder-8890-mmc";</span><br><span style="color: hsl(120, 100%, 40%);">+ reg = <0x0c00 0 0 0 0>; /* DEVFN = 0x0c (1:4) */</span><br><span style="color: hsl(120, 100%, 40%);">+ #address-cells = <1>;</span><br><span style="color: hsl(120, 100%, 40%);">+ #size-cells = <0>;</span><br><span style="color: hsl(120, 100%, 40%);">+ clocks = <&sclk>;</span><br><span style="color: hsl(120, 100%, 40%);">+ };</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ i2c_9_0: i2c@9,0 {</span><br><span style="color: hsl(120, 100%, 40%);">+ #address-cells = <1>;</span><br><span style="color: hsl(120, 100%, 40%);">+ #size-cells = <0>;</span><br><span style="color: hsl(120, 100%, 40%);">+ compatible = "cavium,thunder-8890-twsi";</span><br><span style="color: hsl(120, 100%, 40%);">+ reg = <0x4800 0 0 0 0>; /* DEVFN = 0x48 (9:0) */</span><br><span style="color: hsl(120, 100%, 40%);">+ clock-frequency = <100000>;</span><br><span style="color: hsl(120, 100%, 40%);">+ clocks = <&sclk>;</span><br><span style="color: hsl(120, 100%, 40%);">+ u-boot,dm-pre-reloc;</span><br><span style="color: hsl(120, 100%, 40%);">+ };</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ i2c_9_1: i2c@9,1 {</span><br><span style="color: hsl(120, 100%, 40%);">+ #address-cells = <1>;</span><br><span style="color: hsl(120, 100%, 40%);">+ #size-cells = <0>;</span><br><span style="color: hsl(120, 100%, 40%);">+ compatible = "cavium,thunder-8890-twsi";</span><br><span style="color: hsl(120, 100%, 40%);">+ reg = <0x4900 0 0 0 0>; /* DEVFN = 0x49 (9:1) */</span><br><span style="color: hsl(120, 100%, 40%);">+ clock-frequency = <100000>;</span><br><span style="color: hsl(120, 100%, 40%);">+ clocks = <&sclk>;</span><br><span style="color: hsl(120, 100%, 40%);">+ u-boot,dm-pre-reloc;</span><br><span style="color: hsl(120, 100%, 40%);">+ };</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ rgx0 {</span><br><span style="color: hsl(120, 100%, 40%);">+ #address-cells = <1>;</span><br><span style="color: hsl(120, 100%, 40%);">+ #size-cells = <0>;</span><br><span style="color: hsl(120, 100%, 40%);">+ compatible = "cavium,thunder-8890-bgx";</span><br><span style="color: hsl(120, 100%, 40%);">+ reg = <0x9000 0 0 0 0>; /* DEVFN = 0x90 (16:1) */</span><br><span style="color: hsl(120, 100%, 40%);">+ };</span><br><span style="color: hsl(120, 100%, 40%);">+ bgx0 {</span><br><span style="color: hsl(120, 100%, 40%);">+ #address-cells = <1>;</span><br><span style="color: hsl(120, 100%, 40%);">+ #size-cells = <0>;</span><br><span style="color: hsl(120, 100%, 40%);">+ compatible = "cavium,thunder-8890-bgx";</span><br><span style="color: hsl(120, 100%, 40%);">+ reg = <0x8000 0 0 0 0>; /* DEVFN = 0x80 (16:0) */</span><br><span style="color: hsl(120, 100%, 40%);">+ };</span><br><span style="color: hsl(120, 100%, 40%);">+ bgx1 {</span><br><span style="color: hsl(120, 100%, 40%);">+ #address-cells = <1>;</span><br><span style="color: hsl(120, 100%, 40%);">+ #size-cells = <0>;</span><br><span style="color: hsl(120, 100%, 40%);">+ compatible = "cavium,thunder-8890-bgx";</span><br><span style="color: hsl(120, 100%, 40%);">+ reg = <0x8100 0 0 0 0>; /* DEVFN = 0x81 (16:1) */</span><br><span style="color: hsl(120, 100%, 40%);">+ };</span><br><span style="color: hsl(120, 100%, 40%);">+ };</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ spi_7_0: spi@7,0 {</span><br><span style="color: hsl(120, 100%, 40%);">+ compatible = "cavium,thunder-8190-spi";</span><br><span style="color: hsl(120, 100%, 40%);">+ reg = <0x3800 0x0 0x0 0x0 0x0>; /* DEVFN = 0x38 (7:0) */</span><br><span style="color: hsl(120, 100%, 40%);">+ #address-cells = <1>;</span><br><span style="color: hsl(120, 100%, 40%);">+ #size-cells = <0>;</span><br><span style="color: hsl(120, 100%, 40%);">+ clocks = <&sclk>;</span><br><span style="color: hsl(120, 100%, 40%);">+ };</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ gpio_6_0: gpio0@6,0 {</span><br><span style="color: hsl(120, 100%, 40%);">+ #gpio-cells = <2>;</span><br><span style="color: hsl(120, 100%, 40%);">+ compatible = "cavium,thunder-8890-gpio";</span><br><span style="color: hsl(120, 100%, 40%);">+ gpio-controller;</span><br><span style="color: hsl(120, 100%, 40%);">+ reg = <0x3000 0 0 0 0>; /* DEVFN = 0x30 (6:0) */</span><br><span style="color: hsl(120, 100%, 40%);">+ u-boot,dm-pre-reloc;</span><br><span style="color: hsl(120, 100%, 40%);">+ };</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ nfc: nand@b,0 {</span><br><span style="color: hsl(120, 100%, 40%);">+ #address-cells = <1>;</span><br><span style="color: hsl(120, 100%, 40%);">+ #size-cells = <0>;</span><br><span style="color: hsl(120, 100%, 40%);">+ compatible = "cavium,cn8130-nand";</span><br><span style="color: hsl(120, 100%, 40%);">+ reg = <0x5800 0 0 0 0>; /* DEVFN = 0x58 (b:0) */</span><br><span style="color: hsl(120, 100%, 40%);">+ clocks = <&sclk>;</span><br><span style="color: hsl(120, 100%, 40%);">+ };</span><br><span style="color: hsl(120, 100%, 40%);">+ };</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ pem0: pci@87e0c0000000 {</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* "cavium,pci-host-thunder-pem" implies that</span><br><span style="color: hsl(120, 100%, 40%);">+ the first bus in bus-range has config access</span><br><span style="color: hsl(120, 100%, 40%);">+ via the "PEM space", subsequent buses have</span><br><span style="color: hsl(120, 100%, 40%);">+ config assess via the "Configuration space".</span><br><span style="color: hsl(120, 100%, 40%);">+ The "mem64 PEM" range is used to map the PEM</span><br><span style="color: hsl(120, 100%, 40%);">+ BAR0, which is used by the AER and PME MSI-X</span><br><span style="color: hsl(120, 100%, 40%);">+ sources. UEFI and Linux must assign the same</span><br><span style="color: hsl(120, 100%, 40%);">+ bus number to each device, otherwise Linux</span><br><span style="color: hsl(120, 100%, 40%);">+ enumeration gets confused. Because UEFI</span><br><span style="color: hsl(120, 100%, 40%);">+ skips the PEM bus and its PCIe-RC bridge it</span><br><span style="color: hsl(120, 100%, 40%);">+ uses a numbering that starts 1 bus higher.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ compatible = "cavium,pci-host-thunder-pem";</span><br><span style="color: hsl(120, 100%, 40%);">+ device_type = "pci";</span><br><span style="color: hsl(120, 100%, 40%);">+ msi-parent = <&its>;</span><br><span style="color: hsl(120, 100%, 40%);">+ msi-map = <0 &its 0 0x10000>;</span><br><span style="color: hsl(120, 100%, 40%);">+ bus-range = <0x1f 0x57>;</span><br><span style="color: hsl(120, 100%, 40%);">+ #size-cells = <2>;</span><br><span style="color: hsl(120, 100%, 40%);">+ #address-cells = <3>;</span><br><span style="color: hsl(120, 100%, 40%);">+ #stream-id-cells = <1>;</span><br><span style="color: hsl(120, 100%, 40%);">+ dma-coherent;</span><br><span style="color: hsl(120, 100%, 40%);">+ reg = <0x8800 0x1f000000 0x0 0x39000000>, /* Configuration space */</span><br><span style="color: hsl(120, 100%, 40%);">+ <0x87e0 0xc0000000 0x0 0x01000000>; /* PEM space */</span><br><span style="color: hsl(120, 100%, 40%);">+ ranges = <0x01000000 0x00 0x00000000 0x8830 0x00000000 0x00 0x00010000>, /* I/O */</span><br><span style="color: hsl(120, 100%, 40%);">+ <0x03000000 0x00 0x10000000 0x8810 0x10000000 0x0f 0xf0000000>, /* mem64 */</span><br><span style="color: hsl(120, 100%, 40%);">+ <0x43000000 0x10 0x00000000 0x8820 0x00000000 0x10 0x00000000>, /* mem64-pref */</span><br><span style="color: hsl(120, 100%, 40%);">+ <0x03000000 0x87e0 0xc0000000 0x87e0 0xc0000000 0x00 0x01000000>; /* mem64 PEM */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ #interrupt-cells = <1>;</span><br><span style="color: hsl(120, 100%, 40%);">+ interrupt-map-mask = <0 0 0 7>;</span><br><span style="color: hsl(120, 100%, 40%);">+ interrupt-map = <0 0 0 1 &gic0 0 0 0 16 4>, /* INTA */</span><br><span style="color: hsl(120, 100%, 40%);">+ <0 0 0 2 &gic0 0 0 0 17 4>, /* INTB */</span><br><span style="color: hsl(120, 100%, 40%);">+ <0 0 0 3 &gic0 0 0 0 18 4>, /* INTC */</span><br><span style="color: hsl(120, 100%, 40%);">+ <0 0 0 4 &gic0 0 0 0 19 4>; /* INTD */</span><br><span style="color: hsl(120, 100%, 40%);">+ };</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ pem1: pci@87e0c1000000 {</span><br><span style="color: hsl(120, 100%, 40%);">+ compatible = "cavium,pci-host-thunder-pem";</span><br><span style="color: hsl(120, 100%, 40%);">+ device_type = "pci";</span><br><span style="color: hsl(120, 100%, 40%);">+ msi-parent = <&its>;</span><br><span style="color: hsl(120, 100%, 40%);">+ msi-map = <0 &its 0 0x10000>;</span><br><span style="color: hsl(120, 100%, 40%);">+ bus-range = <0x57 0x8f>;</span><br><span style="color: hsl(120, 100%, 40%);">+ #size-cells = <2>;</span><br><span style="color: hsl(120, 100%, 40%);">+ #address-cells = <3>;</span><br><span style="color: hsl(120, 100%, 40%);">+ #stream-id-cells = <1>;</span><br><span style="color: hsl(120, 100%, 40%);">+ dma-coherent;</span><br><span style="color: hsl(120, 100%, 40%);">+ reg = <0x8840 0x57000000 0x0 0x39000000>, /* Configuration space */</span><br><span style="color: hsl(120, 100%, 40%);">+ <0x87e0 0xc1000000 0x0 0x01000000>; /* PEM space */</span><br><span style="color: hsl(120, 100%, 40%);">+ ranges = <0x01000000 0x00 0x00010000 0x8870 0x00010000 0x00 0x00010000>, /* I/O */</span><br><span style="color: hsl(120, 100%, 40%);">+ <0x03000000 0x00 0x10000000 0x8850 0x10000000 0x0f 0xf0000000>, /* mem64 */</span><br><span style="color: hsl(120, 100%, 40%);">+ <0x43000000 0x10 0x00000000 0x8860 0x00000000 0x10 0x00000000>, /* mem64-pref */</span><br><span style="color: hsl(120, 100%, 40%);">+ <0x03000000 0x87e0 0xc1000000 0x87e0 0xc1000000 0x00 0x01000000>; /* mem64 PEM */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ #interrupt-cells = <1>;</span><br><span style="color: hsl(120, 100%, 40%);">+ interrupt-map-mask = <0 0 0 7>;</span><br><span style="color: hsl(120, 100%, 40%);">+ interrupt-map = <0 0 0 1 &gic0 0 0 0 20 4>, /* INTA */</span><br><span style="color: hsl(120, 100%, 40%);">+ <0 0 0 2 &gic0 0 0 0 21 4>, /* INTB */</span><br><span style="color: hsl(120, 100%, 40%);">+ <0 0 0 3 &gic0 0 0 0 22 4>, /* INTC */</span><br><span style="color: hsl(120, 100%, 40%);">+ <0 0 0 4 &gic0 0 0 0 23 4>; /* INTD */</span><br><span style="color: hsl(120, 100%, 40%);">+ };</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ pem2: pci@87e0c2000000 {</span><br><span style="color: hsl(120, 100%, 40%);">+ compatible = "cavium,pci-host-thunder-pem";</span><br><span style="color: hsl(120, 100%, 40%);">+ device_type = "pci";</span><br><span style="color: hsl(120, 100%, 40%);">+ msi-parent = <&its>;</span><br><span style="color: hsl(120, 100%, 40%);">+ msi-map = <0 &its 0 0x10000>;</span><br><span style="color: hsl(120, 100%, 40%);">+ bus-range = <0x8f 0xc7>;</span><br><span style="color: hsl(120, 100%, 40%);">+ #size-cells = <2>;</span><br><span style="color: hsl(120, 100%, 40%);">+ #address-cells = <3>;</span><br><span style="color: hsl(120, 100%, 40%);">+ #stream-id-cells = <1>;</span><br><span style="color: hsl(120, 100%, 40%);">+ dma-coherent;</span><br><span style="color: hsl(120, 100%, 40%);">+ reg = <0x8880 0x8f000000 0x0 0x39000000>, /* Configuration space */</span><br><span style="color: hsl(120, 100%, 40%);">+ <0x87e0 0xc2000000 0x0 0x01000000>; /* PEM space */</span><br><span style="color: hsl(120, 100%, 40%);">+ ranges = <0x01000000 0x00 0x00020000 0x88b0 0x00020000 0x00 0x00010000>, /* I/O */</span><br><span style="color: hsl(120, 100%, 40%);">+ <0x03000000 0x00 0x10000000 0x8890 0x10000000 0x0f 0xf0000000>, /* mem64 */</span><br><span style="color: hsl(120, 100%, 40%);">+ <0x43000000 0x10 0x00000000 0x88a0 0x00000000 0x10 0x00000000>, /* mem64-pref */</span><br><span style="color: hsl(120, 100%, 40%);">+ <0x03000000 0x87e0 0xc2000000 0x87e0 0xc2000000 0x00 0x01000000>; /* mem64 PEM */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ #interrupt-cells = <1>;</span><br><span style="color: hsl(120, 100%, 40%);">+ interrupt-map-mask = <0 0 0 7>;</span><br><span style="color: hsl(120, 100%, 40%);">+ interrupt-map = <0 0 0 1 &gic0 0 0 0 24 4>, /* INTA */</span><br><span style="color: hsl(120, 100%, 40%);">+ <0 0 0 2 &gic0 0 0 0 25 4>, /* INTB */</span><br><span style="color: hsl(120, 100%, 40%);">+ <0 0 0 3 &gic0 0 0 0 26 4>, /* INTC */</span><br><span style="color: hsl(120, 100%, 40%);">+ <0 0 0 4 &gic0 0 0 0 27 4>; /* INTD */</span><br><span style="color: hsl(120, 100%, 40%);">+ };</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ tdm: tdm@d,0 {</span><br><span style="color: hsl(120, 100%, 40%);">+ #address-cells = <1>;</span><br><span style="color: hsl(120, 100%, 40%);">+ #size-cells = <0>;</span><br><span style="color: hsl(120, 100%, 40%);">+ compatible = "cavium,thunder-8190-tdm";</span><br><span style="color: hsl(120, 100%, 40%);">+ reg = <0x6800 0 0 0>; /* DEVFN = 0x68 (d:0) */</span><br><span style="color: hsl(120, 100%, 40%);">+ clocks = <&sclk>;</span><br><span style="color: hsl(120, 100%, 40%);">+ };</span><br><span style="color: hsl(120, 100%, 40%);">+ };</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ aliases {</span><br><span style="color: hsl(120, 100%, 40%);">+ serial0 = &uaa0;</span><br><span style="color: hsl(120, 100%, 40%);">+ serial1 = &uaa1;</span><br><span style="color: hsl(120, 100%, 40%);">+ serial2 = &uaa2;</span><br><span style="color: hsl(120, 100%, 40%);">+ serial3 = &uaa3;</span><br><span style="color: hsl(120, 100%, 40%);">+ i2c0 = &i2c_9_0;</span><br><span style="color: hsl(120, 100%, 40%);">+ i2c1 = &i2c_9_1;</span><br><span style="color: hsl(120, 100%, 40%);">+ spi0 = &spi_7_0;</span><br><span style="color: hsl(120, 100%, 40%);">+ };</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ chosen {</span><br><span style="color: hsl(120, 100%, 40%);">+ stdout-path = "serial0:115200n8";</span><br><span style="color: hsl(120, 100%, 40%);">+ };</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ memory@0 {</span><br><span style="color: hsl(120, 100%, 40%);">+ device_type = "memory";</span><br><span style="color: hsl(120, 100%, 40%);">+ reg = <0x0 0x01400000 0x0 0x7EC00000>;</span><br><span style="color: hsl(120, 100%, 40%);">+ /* socket 0 */</span><br><span style="color: hsl(120, 100%, 40%);">+ numa-node-id = <0>;</span><br><span style="color: hsl(120, 100%, 40%);">+ };</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span>diff --git a/src/mainboard/facebook/satima/death.c b/src/mainboard/facebook/satima/death.c</span><br><span>new file mode 100644</span><br><span>index 0000000..1e64e15</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/facebook/satima/death.c</span><br><span>@@ -0,0 +1,31 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright 2017-present Facebook, Inc.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/gpio.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <console/console.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <delay.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+void die_notify(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ const u32 rate = 1000 / 5; // blink at 5 Hz</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ do {</span><br><span style="color: hsl(120, 100%, 40%);">+ gpio_output(11, 0);</span><br><span style="color: hsl(120, 100%, 40%);">+ mdelay(rate);</span><br><span style="color: hsl(120, 100%, 40%);">+ gpio_output(11, 1);</span><br><span style="color: hsl(120, 100%, 40%);">+ mdelay(rate);</span><br><span style="color: hsl(120, 100%, 40%);">+ } while(1);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span>diff --git a/src/mainboard/facebook/satima/devicetree.cb b/src/mainboard/facebook/satima/devicetree.cb</span><br><span>new file mode 100644</span><br><span>index 0000000..07d508a</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/facebook/satima/devicetree.cb</span><br><span>@@ -0,0 +1,210 @@</span><br><span style="color: hsl(120, 100%, 40%);">+##</span><br><span style="color: hsl(120, 100%, 40%);">+## This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+##</span><br><span style="color: hsl(120, 100%, 40%);">+## Copyright 2017-present Facebook, Inc.</span><br><span style="color: hsl(120, 100%, 40%);">+##</span><br><span style="color: hsl(120, 100%, 40%);">+## This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+## it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+## the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+##</span><br><span style="color: hsl(120, 100%, 40%);">+## This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+## but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+## GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+##</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+chip soc/cavium/cn81xx</span><br><span style="color: hsl(120, 100%, 40%);">+ device cpu_cluster 0 on end</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ device domain 0 on</span><br><span style="color: hsl(120, 100%, 40%);">+ chip soc/cavium/common/pci</span><br><span style="color: hsl(120, 100%, 40%);">+ register "secure" = "0"</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 01.0 on # PCI bridge</span><br><span style="color: hsl(120, 100%, 40%);">+ chip soc/cavium/common/pci</span><br><span style="color: hsl(120, 100%, 40%);">+ register "secure" = "0"</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 00.0 on end # MRML</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ chip soc/cavium/common/pci</span><br><span style="color: hsl(120, 100%, 40%);">+ register "secure" = "0"</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 00.1 on end # RESET</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ chip soc/cavium/common/pci</span><br><span style="color: hsl(120, 100%, 40%);">+ register "secure" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 00.2 on end # DAP</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ chip soc/cavium/common/pci</span><br><span style="color: hsl(120, 100%, 40%);">+ register "secure" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 00.3 on end # MDIO</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ chip soc/cavium/common/pci</span><br><span style="color: hsl(120, 100%, 40%);">+ register "secure" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 00.4 on end # FUSE</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ chip soc/cavium/common/pci</span><br><span style="color: hsl(120, 100%, 40%);">+ register "secure" = "0"</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 01.2 on end # SGPIO</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ chip soc/cavium/common/pci</span><br><span style="color: hsl(120, 100%, 40%);">+ register "secure" = "0"</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 01.3 on end # SMI</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ chip soc/cavium/common/pci</span><br><span style="color: hsl(120, 100%, 40%);">+ register "secure" = "0"</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 01.4 on end # MMC</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ chip soc/cavium/common/pci</span><br><span style="color: hsl(120, 100%, 40%);">+ register "secure" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 01.5 on end # KEY</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ chip soc/cavium/common/pci</span><br><span style="color: hsl(120, 100%, 40%);">+ register "secure" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 01.6 on end # BOOT BUS</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ chip soc/cavium/common/pci</span><br><span style="color: hsl(120, 100%, 40%);">+ register "secure" = "0"</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 01.7 on end # PBUS</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ chip soc/cavium/common/pci</span><br><span style="color: hsl(120, 100%, 40%);">+ register "secure" = "0"</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 02.0 on end # XCV</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 04.0 on end</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ chip soc/cavium/common/pci</span><br><span style="color: hsl(120, 100%, 40%);">+ register "secure" = "0"</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 06.0 on end # L2C-TAD</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ chip soc/cavium/common/pci</span><br><span style="color: hsl(120, 100%, 40%);">+ register "secure" = "0"</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 07.0 on end # L2C-CBC</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ chip soc/cavium/common/pci</span><br><span style="color: hsl(120, 100%, 40%);">+ register "secure" = "0"</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 07.4 on end # L2C-MCI</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ chip soc/cavium/common/pci</span><br><span style="color: hsl(120, 100%, 40%);">+ register "secure" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 08.0 on end # UUA0</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ chip soc/cavium/common/pci</span><br><span style="color: hsl(120, 100%, 40%);">+ register "secure" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 08.1 on end # UUA1</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ chip soc/cavium/common/pci</span><br><span style="color: hsl(120, 100%, 40%);">+ register "secure" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 08.2 off end # UUA2</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ chip soc/cavium/common/pci</span><br><span style="color: hsl(120, 100%, 40%);">+ register "secure" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 08.3 off end # UUA3</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ chip soc/cavium/common/pci</span><br><span style="color: hsl(120, 100%, 40%);">+ register "secure" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 08.4 on end # VRM</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ chip soc/cavium/common/pci</span><br><span style="color: hsl(120, 100%, 40%);">+ register "secure" = "0"</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 09.0 on end # I2C0</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ chip soc/cavium/common/pci</span><br><span style="color: hsl(120, 100%, 40%);">+ register "secure" = "0"</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 09.1 on end # I2C1</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ chip soc/cavium/common/pci</span><br><span style="color: hsl(120, 100%, 40%);">+ register "secure" = "0"</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 0a.0 on end # PCC Bridge</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ chip soc/cavium/common/pci</span><br><span style="color: hsl(120, 100%, 40%);">+ register "secure" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 0b.0 on end # IOBN</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ chip soc/cavium/common/pci</span><br><span style="color: hsl(120, 100%, 40%);">+ register "secure" = "0"</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 0c.0 on end # OCLA0</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ chip soc/cavium/common/pci</span><br><span style="color: hsl(120, 100%, 40%);">+ register "secure" = "0"</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 0c.1 on end # OCLA1</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ chip soc/cavium/common/pci</span><br><span style="color: hsl(120, 100%, 40%);">+ register "secure" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 0d.0 on end</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ chip soc/cavium/common/pci</span><br><span style="color: hsl(120, 100%, 40%);">+ register "secure" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 0e.0 on end # PCIe0</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ chip soc/cavium/common/pci</span><br><span style="color: hsl(120, 100%, 40%);">+ register "secure" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 0e.1 on end # PCIe1</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ chip soc/cavium/common/pci</span><br><span style="color: hsl(120, 100%, 40%);">+ register "secure" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 0e.2 on end # PCIe2</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ chip soc/cavium/common/pci</span><br><span style="color: hsl(120, 100%, 40%);">+ register "secure" = "0"</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 10.0 on end # bgx0</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ chip soc/cavium/common/pci</span><br><span style="color: hsl(120, 100%, 40%);">+ register "secure" = "0"</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 10.1 off end # bgx1</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ chip soc/cavium/common/pci</span><br><span style="color: hsl(120, 100%, 40%);">+ register "secure" = "0"</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 11.0 on end # rgx0</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ chip soc/cavium/common/pci</span><br><span style="color: hsl(120, 100%, 40%);">+ register "secure" = "0"</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 12.0 on end # MAC</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ chip soc/cavium/common/pci</span><br><span style="color: hsl(120, 100%, 40%);">+ register "secure" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1c.0 on end # GSER0</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ chip soc/cavium/common/pci</span><br><span style="color: hsl(120, 100%, 40%);">+ register "secure" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1c.1 on end # GSER1</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ chip soc/cavium/common/pci</span><br><span style="color: hsl(120, 100%, 40%);">+ register "secure" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1c.2 on end # GSER2</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ chip soc/cavium/common/pci</span><br><span style="color: hsl(120, 100%, 40%);">+ register "secure" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1c.3 on end # GSER3</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ chip soc/cavium/common/pci</span><br><span style="color: hsl(120, 100%, 40%);">+ register "secure" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 02.0 on end #SMMU</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ chip soc/cavium/common/pci</span><br><span style="color: hsl(120, 100%, 40%);">+ register "secure" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 03.0 on end #GIC</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ chip soc/cavium/common/pci</span><br><span style="color: hsl(120, 100%, 40%);">+ register "secure" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 04.0 on end #GTI</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 05.0 on end # NIC</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 06.0 on end # GPIO</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 07.0 on end # SPI</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 08.0 on end # MIO</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 09.0 on end # PCI bridge</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 0a.0 on end # PCI bridge</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 0b.0 on end # NFC</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 0c.0 on end # PCI bridge</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 0d.0 on end # PCM</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 0e.0 on end # VRM</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 0f.0 on end # PCI bridge</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 10.0 on end # USB0</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 11.0 on end # USB1</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 16.0 on end # SATA0</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 17.0 on end # SATA1</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+end</span><br><span>diff --git a/src/mainboard/facebook/satima/mainboard.c b/src/mainboard/facebook/satima/mainboard.c</span><br><span>new file mode 100644</span><br><span>index 0000000..9636715</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/facebook/satima/mainboard.c</span><br><span>@@ -0,0 +1,112 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright 2017-2018 Facebook, Inc.</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright 2003-2017 Cavium Inc. (support@cavium.com)</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Derived from Cavium's BSD-3 Clause OCTEONTX-SDK-6.2.0.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <device/device.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <libbdk-hal/bdk-config.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <libbdk-hal/bdk-twsi.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/gpio.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <delay.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/uart.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <console/console.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/clock.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/gpio.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/timer.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/cpu.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/sdram.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <libbdk-hal/bdk-config.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static void mainboard_print_info(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ printk(BIOS_INFO, "MB: trusted boot : %s\n",</span><br><span style="color: hsl(120, 100%, 40%);">+ gpio_strap_value(10) ? "yes" : "no");</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ const size_t boot_method = gpio_strap_value(0) |</span><br><span style="color: hsl(120, 100%, 40%);">+ (gpio_strap_value(1) << 1) |</span><br><span style="color: hsl(120, 100%, 40%);">+ (gpio_strap_value(2) << 2) |</span><br><span style="color: hsl(120, 100%, 40%);">+ (gpio_strap_value(3) << 3);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ printk(BIOS_INFO, "MB: boot method : ");</span><br><span style="color: hsl(120, 100%, 40%);">+ switch (boot_method) {</span><br><span style="color: hsl(120, 100%, 40%);">+ case 0x2:</span><br><span style="color: hsl(120, 100%, 40%);">+ case 0x3:</span><br><span style="color: hsl(120, 100%, 40%);">+ printk(BIOS_INFO, "EMMC\n");</span><br><span style="color: hsl(120, 100%, 40%);">+ break;</span><br><span style="color: hsl(120, 100%, 40%);">+ case 0x5:</span><br><span style="color: hsl(120, 100%, 40%);">+ case 0x6:</span><br><span style="color: hsl(120, 100%, 40%);">+ printk(BIOS_INFO, "SPI\n");</span><br><span style="color: hsl(120, 100%, 40%);">+ break;</span><br><span style="color: hsl(120, 100%, 40%);">+ case 0x8:</span><br><span style="color: hsl(120, 100%, 40%);">+ printk(BIOS_INFO, "REMOTE\n");</span><br><span style="color: hsl(120, 100%, 40%);">+ break;</span><br><span style="color: hsl(120, 100%, 40%);">+ case 0xc:</span><br><span style="color: hsl(120, 100%, 40%);">+ case 0xd:</span><br><span style="color: hsl(120, 100%, 40%);">+ printk(BIOS_INFO, "PCIe\n");</span><br><span style="color: hsl(120, 100%, 40%);">+ break;</span><br><span style="color: hsl(120, 100%, 40%);">+ default:</span><br><span style="color: hsl(120, 100%, 40%);">+ printk(BIOS_INFO, "unknown\n");</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ printk(BIOS_INFO, "MB: REFclk : %llu MHz\n",</span><br><span style="color: hsl(120, 100%, 40%);">+ thunderx_get_ref_clock() / 1000000ULL);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ printk(BIOS_INFO, "MB: IOclk : %llu MHz\n",</span><br><span style="color: hsl(120, 100%, 40%);">+ thunderx_get_io_clock() / 1000000ULL);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ printk(BIOS_INFO, "MB: COREclk : %llu MHz\n",</span><br><span style="color: hsl(120, 100%, 40%);">+ thunderx_get_core_clock() / 1000000ULL);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ printk(BIOS_INFO, "MB: #CPU cores : %zu\n",</span><br><span style="color: hsl(120, 100%, 40%);">+ cpu_get_num_available_cores());</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ printk(BIOS_INFO, "MB: RAM : %zu MiB\n",</span><br><span style="color: hsl(120, 100%, 40%);">+ sdram_size_mb());</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+extern const struct bdk_devicetree_key_value devtree[];</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static void mainboard_init(struct device *dev)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ size_t i;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Init UARTs */</span><br><span style="color: hsl(120, 100%, 40%);">+ for (i = 0; i < 4; i++) {</span><br><span style="color: hsl(120, 100%, 40%);">+ if (!uart_is_enabled(i))</span><br><span style="color: hsl(120, 100%, 40%);">+ uart_setup(i, 0);</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Init timer */</span><br><span style="color: hsl(120, 100%, 40%);">+ soc_timer_init();</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Init CPUs */</span><br><span style="color: hsl(120, 100%, 40%);">+ for (i = 1; i < CONFIG_MAX_CPUS; i++)</span><br><span style="color: hsl(120, 100%, 40%);">+ start_cpu(i, NULL);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static void mainboard_enable(struct device *dev)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ dev->ops->init = &mainboard_init;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ bdk_config_set_fdt(devtree);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ mainboard_print_info();</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+struct chip_operations mainboard_ops = {</span><br><span style="color: hsl(120, 100%, 40%);">+ .name = CONFIG_MAINBOARD_PART_NUMBER,</span><br><span style="color: hsl(120, 100%, 40%);">+ .enable_dev = mainboard_enable,</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span>diff --git a/src/mainboard/facebook/satima/memlayout.ld b/src/mainboard/facebook/satima/memlayout.ld</span><br><span>new file mode 100644</span><br><span>index 0000000..9349362</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/facebook/satima/memlayout.ld</span><br><span>@@ -0,0 +1 @@</span><br><span style="color: hsl(120, 100%, 40%);">+ #include <soc/memlayout.ld></span><br><span>diff --git a/src/mainboard/facebook/satima/romstage.c b/src/mainboard/facebook/satima/romstage.c</span><br><span>new file mode 100644</span><br><span>index 0000000..e8e5cd6</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/facebook/satima/romstage.c</span><br><span>@@ -0,0 +1,47 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright 2017-present Facebook, Inc.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <arch/exception.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <cbmem.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <romstage_handoff.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/sdram.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/timer.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/mmu.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <stdlib.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <console/console.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <program_loading.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <libbdk-hal/bdk-config.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <string.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+extern const struct bdk_devicetree_key_value devtree[];</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+void main(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ watchdog_poke(0);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ console_init();</span><br><span style="color: hsl(120, 100%, 40%);">+ exception_init();</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ bdk_config_set_fdt(devtree);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ sdram_init();</span><br><span style="color: hsl(120, 100%, 40%);">+ soc_mmu_init();</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ watchdog_poke(0);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ cbmem_initialize_empty();</span><br><span style="color: hsl(120, 100%, 40%);">+ run_ramstage();</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span>diff --git a/src/mainboard/facebook/satima/sff8104-linux.dts b/src/mainboard/facebook/satima/sff8104-linux.dts</span><br><span>new file mode 100644</span><br><span>index 0000000..ff0121e</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/facebook/satima/sff8104-linux.dts</span><br><span>@@ -0,0 +1,156 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * Cavium Thunder DTS file - Thunder board description</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2016, Cavium Inc.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is dual-licensed: you can use it either under the terms</span><br><span style="color: hsl(120, 100%, 40%);">+ * of the GPL or the X11 license, at your option. Note that this dual</span><br><span style="color: hsl(120, 100%, 40%);">+ * licensing only applies to this file, and not this project as a</span><br><span style="color: hsl(120, 100%, 40%);">+ * whole.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * a) This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Or, alternatively,</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * b) Permission is hereby granted, free of charge, to any person</span><br><span style="color: hsl(120, 100%, 40%);">+ * obtaining a copy of this software and associated documentation</span><br><span style="color: hsl(120, 100%, 40%);">+ * files (the "Software"), to deal in the Software without</span><br><span style="color: hsl(120, 100%, 40%);">+ * restriction, including without limitation the rights to use,</span><br><span style="color: hsl(120, 100%, 40%);">+ * copy, modify, merge, publish, distribute, sublicense, and/or</span><br><span style="color: hsl(120, 100%, 40%);">+ * sell copies of the Software, and to permit persons to whom the</span><br><span style="color: hsl(120, 100%, 40%);">+ * Software is furnished to do so, subject to the following</span><br><span style="color: hsl(120, 100%, 40%);">+ * conditions:</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * The above copyright notice and this permission notice shall be</span><br><span style="color: hsl(120, 100%, 40%);">+ * included in all copies or substantial portions of the Software.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,</span><br><span style="color: hsl(120, 100%, 40%);">+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES</span><br><span style="color: hsl(120, 100%, 40%);">+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND</span><br><span style="color: hsl(120, 100%, 40%);">+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT</span><br><span style="color: hsl(120, 100%, 40%);">+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,</span><br><span style="color: hsl(120, 100%, 40%);">+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING</span><br><span style="color: hsl(120, 100%, 40%);">+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR</span><br><span style="color: hsl(120, 100%, 40%);">+ * OTHER DEALINGS IN THE SOFTWARE.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/dts-v1/;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/include/ "cn81xx-linux.dtsi"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+&mrml_bridge {</span><br><span style="color: hsl(120, 100%, 40%);">+ mdio-nexus@1,3 {</span><br><span style="color: hsl(120, 100%, 40%);">+ mdio0@87e005003800 {</span><br><span style="color: hsl(120, 100%, 40%);">+ rgmii00: rgmii00 {</span><br><span style="color: hsl(120, 100%, 40%);">+ reg = <0> ;</span><br><span style="color: hsl(120, 100%, 40%);">+ compatible = "marvell,88e1510", "ethernet-phy-ieee802.3-c22";</span><br><span style="color: hsl(120, 100%, 40%);">+ };</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ qsgmii00: qsgmii00 {</span><br><span style="color: hsl(120, 100%, 40%);">+ qlm-mode = "0x000,qsgmii";</span><br><span style="color: hsl(120, 100%, 40%);">+ reg = <0x10> ;</span><br><span style="color: hsl(120, 100%, 40%);">+ compatible = "vitesse,vsc8574", "ethernet-phy-ieee802.3-c22";</span><br><span style="color: hsl(120, 100%, 40%);">+ };</span><br><span style="color: hsl(120, 100%, 40%);">+ };</span><br><span style="color: hsl(120, 100%, 40%);">+ mdio1@87e005003880 {</span><br><span style="color: hsl(120, 100%, 40%);">+ xfi00: xfi00 {</span><br><span style="color: hsl(120, 100%, 40%);">+ qlm-mode = "0x000,xfi";</span><br><span style="color: hsl(120, 100%, 40%);">+ reg = <0x0>;</span><br><span style="color: hsl(120, 100%, 40%);">+ compatible = "aquantia,aqr105", "ethernet-phy-ieee802.3-c45";</span><br><span style="color: hsl(120, 100%, 40%);">+ };</span><br><span style="color: hsl(120, 100%, 40%);">+ };</span><br><span style="color: hsl(120, 100%, 40%);">+ };</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ rgx0 {</span><br><span style="color: hsl(120, 100%, 40%);">+ rgmii00 {</span><br><span style="color: hsl(120, 100%, 40%);">+ reg = <0>;</span><br><span style="color: hsl(120, 100%, 40%);">+ local-mac-address = [00 00 00 00 00 00];</span><br><span style="color: hsl(120, 100%, 40%);">+ phy-handle = <&rgmii00>;</span><br><span style="color: hsl(120, 100%, 40%);">+ };</span><br><span style="color: hsl(120, 100%, 40%);">+ };</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ bgx0 {</span><br><span style="color: hsl(120, 100%, 40%);">+ /* typename+qlm+typenumber eg :</span><br><span style="color: hsl(120, 100%, 40%);">+ qsgmii+bgx0+sgmmi0</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+ qsgmii00 {</span><br><span style="color: hsl(120, 100%, 40%);">+ reg = <0>;</span><br><span style="color: hsl(120, 100%, 40%);">+ qlm-mode = "0x000,qsgmii";</span><br><span style="color: hsl(120, 100%, 40%);">+ local-mac-address = [00 00 00 00 00 00];</span><br><span style="color: hsl(120, 100%, 40%);">+ phy-handle = <&qsgmii00>;</span><br><span style="color: hsl(120, 100%, 40%);">+ };</span><br><span style="color: hsl(120, 100%, 40%);">+ };</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+&mmc_1_4 {</span><br><span style="color: hsl(120, 100%, 40%);">+ /* NOTE: the BDK is responsible for swapping the two slots.</span><br><span style="color: hsl(120, 100%, 40%);">+ * Unfortunately there does not appear to be any way to read the</span><br><span style="color: hsl(120, 100%, 40%);">+ * position of SW2-7 in software.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+ mmc-slot@0 {</span><br><span style="color: hsl(120, 100%, 40%);">+ compatible = "mmc-slot";</span><br><span style="color: hsl(120, 100%, 40%);">+ reg = <0>;</span><br><span style="color: hsl(120, 100%, 40%);">+ vmmc-supply = <&mmc_supply_3v3>;</span><br><span style="color: hsl(120, 100%, 40%);">+ max-frequency = <26000000>;</span><br><span style="color: hsl(120, 100%, 40%);">+ /* 1.8v is not supported */</span><br><span style="color: hsl(120, 100%, 40%);">+ no-1-8-v;</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Bus width is only 4 bits maximum */</span><br><span style="color: hsl(120, 100%, 40%);">+ bus-width = <4>;</span><br><span style="color: hsl(120, 100%, 40%);">+ /* No write-protect switch is present */</span><br><span style="color: hsl(120, 100%, 40%);">+ disable-wp;</span><br><span style="color: hsl(120, 100%, 40%);">+ /* There is no card detection available; polling must be used. */</span><br><span style="color: hsl(120, 100%, 40%);">+ broken-cd;</span><br><span style="color: hsl(120, 100%, 40%);">+ /* High-speed mode is supported */</span><br><span style="color: hsl(120, 100%, 40%);">+ cap-sd-highspeed;</span><br><span style="color: hsl(120, 100%, 40%);">+ /* speed up device probing */</span><br><span style="color: hsl(120, 100%, 40%);">+ no-sdio;</span><br><span style="color: hsl(120, 100%, 40%);">+ no-mmc;</span><br><span style="color: hsl(120, 100%, 40%);">+ };</span><br><span style="color: hsl(120, 100%, 40%);">+ mmc-slot@1 {</span><br><span style="color: hsl(120, 100%, 40%);">+ compatible = "mmc-slot";</span><br><span style="color: hsl(120, 100%, 40%);">+ reg = <1>;</span><br><span style="color: hsl(120, 100%, 40%);">+ vmmc-supply = <&mmc_supply_3v3>;</span><br><span style="color: hsl(120, 100%, 40%);">+ max-frequency = <26000000>;</span><br><span style="color: hsl(120, 100%, 40%);">+ mmc-ddr-3_3v;</span><br><span style="color: hsl(120, 100%, 40%);">+ /* 1.8v is not supported */</span><br><span style="color: hsl(120, 100%, 40%);">+ no-1-8-v;</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Bus width is only 8 bits maximum */</span><br><span style="color: hsl(120, 100%, 40%);">+ bus-width = <8>;</span><br><span style="color: hsl(120, 100%, 40%);">+ /* No write-protect switch is present */</span><br><span style="color: hsl(120, 100%, 40%);">+ disable-wp;</span><br><span style="color: hsl(120, 100%, 40%);">+ /* There is no card detection available; polling must be used. */</span><br><span style="color: hsl(120, 100%, 40%);">+ broken-cd;</span><br><span style="color: hsl(120, 100%, 40%);">+ /* High-speed mode is supported */</span><br><span style="color: hsl(120, 100%, 40%);">+ cap-mmc-highspeed;</span><br><span style="color: hsl(120, 100%, 40%);">+ /* eMMC device is soldered onto the board */</span><br><span style="color: hsl(120, 100%, 40%);">+ non-removable;</span><br><span style="color: hsl(120, 100%, 40%);">+ /* speed up device probing */</span><br><span style="color: hsl(120, 100%, 40%);">+ no-sdio;</span><br><span style="color: hsl(120, 100%, 40%);">+ no-sd;</span><br><span style="color: hsl(120, 100%, 40%);">+ };</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+&spi_7_0 {</span><br><span style="color: hsl(120, 100%, 40%);">+ flash@0 {</span><br><span style="color: hsl(120, 100%, 40%);">+ compatible = "micron,n25q128a13", "spi-flash", "jedec,spi-nor";</span><br><span style="color: hsl(120, 100%, 40%);">+ reg = <0x0>;</span><br><span style="color: hsl(120, 100%, 40%);">+ spi-max-frequency = <16000000>;</span><br><span style="color: hsl(120, 100%, 40%);">+ #address-cells = <1>;</span><br><span style="color: hsl(120, 100%, 40%);">+ #size-cells = <1>;</span><br><span style="color: hsl(120, 100%, 40%);">+ };</span><br><span style="color: hsl(120, 100%, 40%);">+ flash@1 {</span><br><span style="color: hsl(120, 100%, 40%);">+ compatible = "spinand,mt29f", "mt29f";</span><br><span style="color: hsl(120, 100%, 40%);">+ reg = <0x1>;</span><br><span style="color: hsl(120, 100%, 40%);">+ spi-max-frequency = <50000000>;</span><br><span style="color: hsl(120, 100%, 40%);">+ #address-cells = <1>;</span><br><span style="color: hsl(120, 100%, 40%);">+ #size-cells = <1>;</span><br><span style="color: hsl(120, 100%, 40%);">+ nand-ecc-mode = "none";</span><br><span style="color: hsl(120, 100%, 40%);">+ };</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/27425">change 27425</a>. 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<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I4f972d59ac2243823a77f614c4f92c1666185705 </div>
<div style="display:none"> Gerrit-Change-Number: 27425 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Patrick Rudolph <patrick.rudolph@9elements.com> </div>