<p>Matt DeVillier has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/27421">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">google/asuka: Add as a variant of glados<br><br>Add google/asuka (Dell Chromebook 13 3380) as a variant of<br>glados Skylake reference board:<br>- add asuka-specific DPTF, EC config, GPIO config, Kconfig,<br> NHLT config, PEI data, VBT, SPD data, and devicetree<br><br>Adapted from Chromium branch firmware-glados-7820.B, commit<br>b0c3efe54d877246d07f2467b2dff51cc30348fa [soc/intel/skylake: Enable VMX]<br><br>Test: build/boot google/asuka, verify correct functionality<br><br>Change-Id: I591578fea2514a28c75177835807c3f250904577<br>Signed-off-by: Matt DeVillier <matt.devillier@gmail.com><br>---<br>M src/mainboard/google/glados/Kconfig<br>M src/mainboard/google/glados/Kconfig.name<br>A src/mainboard/google/glados/variants/asuka/Makefile.inc<br>A src/mainboard/google/glados/variants/asuka/data.vbt<br>A src/mainboard/google/glados/variants/asuka/devicetree.cb<br>A src/mainboard/google/glados/variants/asuka/include/variant/acpi/dptf.asl<br>A src/mainboard/google/glados/variants/asuka/include/variant/acpi/mainboard.asl<br>A src/mainboard/google/glados/variants/asuka/include/variant/ec.h<br>A src/mainboard/google/glados/variants/asuka/include/variant/gpio.h<br>A src/mainboard/google/glados/variants/asuka/variant.c<br>10 files changed, 775 insertions(+), 1 deletion(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/27421/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/mainboard/google/glados/Kconfig b/src/mainboard/google/glados/Kconfig</span><br><span>index 412aefe..53edb4f 100644</span><br><span>--- a/src/mainboard/google/glados/Kconfig</span><br><span>+++ b/src/mainboard/google/glados/Kconfig</span><br><span>@@ -36,6 +36,7 @@</span><br><span> </span><br><span> config MAINBOARD_PART_NUMBER</span><br><span> string</span><br><span style="color: hsl(120, 100%, 40%);">+ default "Asuka" if BOARD_GOOGLE_ASUKA</span><br><span> default "Caroline" if BOARD_GOOGLE_CAROLINE</span><br><span> default "Cave" if BOARD_GOOGLE_CAVE</span><br><span> default "Chell" if BOARD_GOOGLE_CHELL</span><br><span>@@ -49,6 +50,7 @@</span><br><span> </span><br><span> config VARIANT_DIR</span><br><span> string</span><br><span style="color: hsl(120, 100%, 40%);">+ default "asuka" if BOARD_GOOGLE_ASUKA</span><br><span> default "caroline" if BOARD_GOOGLE_CAROLINE</span><br><span> default "cave" if BOARD_GOOGLE_CAVE</span><br><span> default "chell" if BOARD_GOOGLE_CHELL</span><br><span>@@ -58,6 +60,7 @@</span><br><span> </span><br><span> config DEVICETREE</span><br><span> string</span><br><span style="color: hsl(120, 100%, 40%);">+ default "variants/asuka/devicetree.cb" if BOARD_GOOGLE_ASUKA</span><br><span> default "variants/caroline/devicetree.cb" if BOARD_GOOGLE_CAROLINE</span><br><span> default "variants/cave/devicetree.cb" if BOARD_GOOGLE_CAVE</span><br><span> default "variants/chell/devicetree.cb" if BOARD_GOOGLE_CHELL</span><br><span>@@ -93,8 +96,9 @@</span><br><span> config GBB_HWID</span><br><span> string</span><br><span> depends on CHROMEOS</span><br><span style="color: hsl(120, 100%, 40%);">+ default "ASUKA TEST 2547" if BOARD_GOOGLE_ASUKA</span><br><span> default "CAROLINE TEST 0958" if BOARD_GOOGLE_CAROLINE</span><br><span style="color: hsl(0, 100%, 40%);">- default "CAVE TEST 9629" if BOARD_GOOGLE_CAVE</span><br><span style="color: hsl(120, 100%, 40%);">+ default "CAVE TEST 6297" if BOARD_GOOGLE_CAVE</span><br><span> default "CHELL TEST 6297" if BOARD_GOOGLE_CHELL</span><br><span> default "GLADOS TEST 1988" if BOARD_GOOGLE_GLADOS</span><br><span> default "LARS TEST 5001" if BOARD_GOOGLE_LARS</span><br><span>diff --git a/src/mainboard/google/glados/Kconfig.name b/src/mainboard/google/glados/Kconfig.name</span><br><span>index d20230e..5162e48 100644</span><br><span>--- a/src/mainboard/google/glados/Kconfig.name</span><br><span>+++ b/src/mainboard/google/glados/Kconfig.name</span><br><span>@@ -1,5 +1,12 @@</span><br><span> comment "Glados"</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+config BOARD_GOOGLE_ASUKA</span><br><span style="color: hsl(120, 100%, 40%);">+ bool "-> Asuka (Dell Chromebook 13 3380)"</span><br><span style="color: hsl(120, 100%, 40%);">+ select BOARD_GOOGLE_BASEBOARD_GLADOS</span><br><span style="color: hsl(120, 100%, 40%);">+ select DRIVERS_GENERIC_MAX98357A</span><br><span style="color: hsl(120, 100%, 40%);">+ select EXCLUDE_NATIVE_SD_INTERFACE</span><br><span style="color: hsl(120, 100%, 40%);">+ select NHLT_MAX98357 if INCLUDE_NHLT_BLOBS</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> config BOARD_GOOGLE_CAROLINE</span><br><span> bool "-> Caroline (Samsung Chromebook Pro)"</span><br><span> select BOARD_GOOGLE_BASEBOARD_GLADOS</span><br><span>diff --git a/src/mainboard/google/glados/variants/asuka/Makefile.inc b/src/mainboard/google/glados/variants/asuka/Makefile.inc</span><br><span>new file mode 100644</span><br><span>index 0000000..e8e2f23</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/google/glados/variants/asuka/Makefile.inc</span><br><span>@@ -0,0 +1,41 @@</span><br><span style="color: hsl(120, 100%, 40%);">+##</span><br><span style="color: hsl(120, 100%, 40%);">+## This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+##</span><br><span style="color: hsl(120, 100%, 40%);">+## Copyright (C) 2015 Google Inc.</span><br><span style="color: hsl(120, 100%, 40%);">+## Copyright (C) 2015 Intel Corporation</span><br><span style="color: hsl(120, 100%, 40%);">+##</span><br><span style="color: hsl(120, 100%, 40%);">+## This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+## it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+## the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+##</span><br><span style="color: hsl(120, 100%, 40%);">+## This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+## but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+## GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+##</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+romstage-y += variant.c</span><br><span style="color: hsl(120, 100%, 40%);">+ramstage-y += variant.c</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+SPD_BIN = $(obj)/spd.bin</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+SPD_SOURCES = hynix_dimm_H9CCNNN8GTMLAR-NUD # 0b0000 Single Channel 2GB</span><br><span style="color: hsl(120, 100%, 40%);">+SPD_SOURCES += hynix_dimm_H9CCNNN8GTMLAR-NUD # 0b0001 Dual Channel 4GB</span><br><span style="color: hsl(120, 100%, 40%);">+SPD_SOURCES += samsung_dimm_K4E8E324EB-EGCF # 0b0010 Single Channel 2GB</span><br><span style="color: hsl(120, 100%, 40%);">+SPD_SOURCES += samsung_dimm_K4E8E324EB-EGCF # 0b0011 Dual Channel 4GB</span><br><span style="color: hsl(120, 100%, 40%);">+SPD_SOURCES += micron_dimm_MT52L256M32D1PF-107-1G-1866 # 0b0100 Single Channel 2GB</span><br><span style="color: hsl(120, 100%, 40%);">+SPD_SOURCES += micron_dimm_MT52L256M32D1PF-107-1G-1866 # 0b0101 Dual Channel 4GB</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f).spd.hex)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+# Include spd ROM data</span><br><span style="color: hsl(120, 100%, 40%);">+$(SPD_BIN): $(SPD_DEPS)</span><br><span style="color: hsl(120, 100%, 40%);">+ for f in $+; \</span><br><span style="color: hsl(120, 100%, 40%);">+ do for c in $$(cat $$f | grep -v ^#); \</span><br><span style="color: hsl(120, 100%, 40%);">+ do printf $$(printf '\%o' 0x$$c); \</span><br><span style="color: hsl(120, 100%, 40%);">+ done; \</span><br><span style="color: hsl(120, 100%, 40%);">+ done > $@</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+cbfs-files-y += spd.bin</span><br><span style="color: hsl(120, 100%, 40%);">+spd.bin-file := $(SPD_BIN)</span><br><span style="color: hsl(120, 100%, 40%);">+spd.bin-type := spd</span><br><span>diff --git a/src/mainboard/google/glados/variants/asuka/data.vbt b/src/mainboard/google/glados/variants/asuka/data.vbt</span><br><span>new file mode 100644</span><br><span>index 0000000..8f2a7b0</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/google/glados/variants/asuka/data.vbt</span><br><span>Binary files differ</span><br><span>diff --git a/src/mainboard/google/glados/variants/asuka/devicetree.cb b/src/mainboard/google/glados/variants/asuka/devicetree.cb</span><br><span>new file mode 100644</span><br><span>index 0000000..cbd8b01</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/google/glados/variants/asuka/devicetree.cb</span><br><span>@@ -0,0 +1,288 @@</span><br><span style="color: hsl(120, 100%, 40%);">+chip soc/intel/skylake</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ # Enable deep Sx states</span><br><span style="color: hsl(120, 100%, 40%);">+ register "deep_s3_enable_ac" = "0"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "deep_s3_enable_dc" = "0"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "deep_s5_enable_ac" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "deep_s5_enable_dc" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "deep_sx_config" = "DSX_EN_LAN_WAKE_PIN"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ # GPE configuration</span><br><span style="color: hsl(120, 100%, 40%);">+ # Note that GPE events called out in ASL code rely on this</span><br><span style="color: hsl(120, 100%, 40%);">+ # route. i.e. If this route changes then the affected GPE</span><br><span style="color: hsl(120, 100%, 40%);">+ # offset bits also need to be changed.</span><br><span style="color: hsl(120, 100%, 40%);">+ register "gpe0_dw0" = "GPP_B"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "gpe0_dw1" = "GPP_D"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "gpe0_dw2" = "GPP_E"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f</span><br><span style="color: hsl(120, 100%, 40%);">+ register "gen1_dec" = "0x00fc0801"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "gen2_dec" = "0x000c0201"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ # Enable "Intel Speed Shift Technology"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "speed_shift_enable" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ # Enable DPTF</span><br><span style="color: hsl(120, 100%, 40%);">+ register "dptf_enable" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ # FSP Configuration</span><br><span style="color: hsl(120, 100%, 40%);">+ register "EnableAzalia" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "DspEnable" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "IoBufferOwnership" = "3"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "SmbusEnable" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "ScsEmmcEnabled" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "ScsEmmcHs400Enabled" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "ScsSdCardEnabled" = "0"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "InternalGfx" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "SkipExtGfxScan" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "Device4Enable" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "HeciEnabled" = "0"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "SaGv" = "3"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "SerialIrqConfigSirqEnable" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PmConfigSlpS3MinAssert" = "2" # 50ms</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PmConfigSlpS4MinAssert" = "4" # 4s</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PmConfigSlpSusMinAssert" = "3" # 4s</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PmConfigSlpAMinAssert" = "3" # 2s</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PmTimerDisabled" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ register "pirqa_routing" = "PCH_IRQ11"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "pirqb_routing" = "PCH_IRQ10"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "pirqc_routing" = "PCH_IRQ11"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "pirqd_routing" = "PCH_IRQ11"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "pirqe_routing" = "PCH_IRQ11"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "pirqf_routing" = "PCH_IRQ11"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "pirqg_routing" = "PCH_IRQ11"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "pirqh_routing" = "PCH_IRQ11"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ # VR Settings Configuration for 5 Domains</span><br><span style="color: hsl(120, 100%, 40%);">+ #+----------------+-------+-------+-------------+-------------+-------+</span><br><span style="color: hsl(120, 100%, 40%);">+ #| Domain/Setting | SA | IA | Ring Sliced | GT Unsliced | GT |</span><br><span style="color: hsl(120, 100%, 40%);">+ #+----------------+-------+-------+-------------+-------------+-------+</span><br><span style="color: hsl(120, 100%, 40%);">+ #| Psi1Threshold | 20A | 20A | 20A | 20A | 20A |</span><br><span style="color: hsl(120, 100%, 40%);">+ #| Psi2Threshold | 4A | 5A | 5A | 5A | 5A |</span><br><span style="color: hsl(120, 100%, 40%);">+ #| Psi3Threshold | 1A | 1A | 1A | 1A | 1A |</span><br><span style="color: hsl(120, 100%, 40%);">+ #| Psi3Enable | 1 | 1 | 1 | 1 | 1 |</span><br><span style="color: hsl(120, 100%, 40%);">+ #| Psi4Enable | 1 | 1 | 1 | 1 | 1 |</span><br><span style="color: hsl(120, 100%, 40%);">+ #| ImonSlope | 0 | 0 | 0 | 0 | 0 |</span><br><span style="color: hsl(120, 100%, 40%);">+ #| ImonOffset | 0 | 0 | 0 | 0 | 0 |</span><br><span style="color: hsl(120, 100%, 40%);">+ #| IccMax | 7A | 34A | 34A | 35A | 35A |</span><br><span style="color: hsl(120, 100%, 40%);">+ #| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V | 1.52V |</span><br><span style="color: hsl(120, 100%, 40%);">+ #+----------------+-------+-------+-------------+-------------+-------+</span><br><span style="color: hsl(120, 100%, 40%);">+ register "domain_vr_config[VR_SYSTEM_AGENT]" = "{</span><br><span style="color: hsl(120, 100%, 40%);">+ .vr_config_enable = 1,</span><br><span style="color: hsl(120, 100%, 40%);">+ .psi1threshold = VR_CFG_AMP(20),</span><br><span style="color: hsl(120, 100%, 40%);">+ .psi2threshold = VR_CFG_AMP(4),</span><br><span style="color: hsl(120, 100%, 40%);">+ .psi3threshold = VR_CFG_AMP(1),</span><br><span style="color: hsl(120, 100%, 40%);">+ .psi3enable = 1,</span><br><span style="color: hsl(120, 100%, 40%);">+ .psi4enable = 1,</span><br><span style="color: hsl(120, 100%, 40%);">+ .imon_slope = 0x0,</span><br><span style="color: hsl(120, 100%, 40%);">+ .imon_offset = 0x0,</span><br><span style="color: hsl(120, 100%, 40%);">+ .icc_max = VR_CFG_AMP(7),</span><br><span style="color: hsl(120, 100%, 40%);">+ .voltage_limit = 1520,</span><br><span style="color: hsl(120, 100%, 40%);">+ }"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ register "domain_vr_config[VR_IA_CORE]" = "{</span><br><span style="color: hsl(120, 100%, 40%);">+ .vr_config_enable = 1,</span><br><span style="color: hsl(120, 100%, 40%);">+ .psi1threshold = VR_CFG_AMP(20),</span><br><span style="color: hsl(120, 100%, 40%);">+ .psi2threshold = VR_CFG_AMP(5),</span><br><span style="color: hsl(120, 100%, 40%);">+ .psi3threshold = VR_CFG_AMP(1),</span><br><span style="color: hsl(120, 100%, 40%);">+ .psi3enable = 1,</span><br><span style="color: hsl(120, 100%, 40%);">+ .psi4enable = 1,</span><br><span style="color: hsl(120, 100%, 40%);">+ .imon_slope = 0x0,</span><br><span style="color: hsl(120, 100%, 40%);">+ .imon_offset = 0x0,</span><br><span style="color: hsl(120, 100%, 40%);">+ .icc_max = VR_CFG_AMP(34),</span><br><span style="color: hsl(120, 100%, 40%);">+ .voltage_limit = 1520,</span><br><span style="color: hsl(120, 100%, 40%);">+ }"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ register "domain_vr_config[VR_RING]" = "{</span><br><span style="color: hsl(120, 100%, 40%);">+ .vr_config_enable = 1,</span><br><span style="color: hsl(120, 100%, 40%);">+ .psi1threshold = VR_CFG_AMP(20),</span><br><span style="color: hsl(120, 100%, 40%);">+ .psi2threshold = VR_CFG_AMP(5),</span><br><span style="color: hsl(120, 100%, 40%);">+ .psi3threshold = VR_CFG_AMP(1),</span><br><span style="color: hsl(120, 100%, 40%);">+ .psi3enable = 1,</span><br><span style="color: hsl(120, 100%, 40%);">+ .psi4enable = 1,</span><br><span style="color: hsl(120, 100%, 40%);">+ .imon_slope = 0x0,</span><br><span style="color: hsl(120, 100%, 40%);">+ .imon_offset = 0x0,</span><br><span style="color: hsl(120, 100%, 40%);">+ .icc_max = VR_CFG_AMP(34),</span><br><span style="color: hsl(120, 100%, 40%);">+ .voltage_limit = 1520,</span><br><span style="color: hsl(120, 100%, 40%);">+ }"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ register "domain_vr_config[VR_GT_UNSLICED]" = "{</span><br><span style="color: hsl(120, 100%, 40%);">+ .vr_config_enable = 1,</span><br><span style="color: hsl(120, 100%, 40%);">+ .psi1threshold = VR_CFG_AMP(20),</span><br><span style="color: hsl(120, 100%, 40%);">+ .psi2threshold = VR_CFG_AMP(5),</span><br><span style="color: hsl(120, 100%, 40%);">+ .psi3threshold = VR_CFG_AMP(1),</span><br><span style="color: hsl(120, 100%, 40%);">+ .psi3enable = 1,</span><br><span style="color: hsl(120, 100%, 40%);">+ .psi4enable = 1,</span><br><span style="color: hsl(120, 100%, 40%);">+ .imon_slope = 0x0,</span><br><span style="color: hsl(120, 100%, 40%);">+ .imon_offset = 0x0,</span><br><span style="color: hsl(120, 100%, 40%);">+ .icc_max = VR_CFG_AMP(35),</span><br><span style="color: hsl(120, 100%, 40%);">+ .voltage_limit = 1520,</span><br><span style="color: hsl(120, 100%, 40%);">+ }"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ register "domain_vr_config[VR_GT_SLICED]" = "{</span><br><span style="color: hsl(120, 100%, 40%);">+ .vr_config_enable = 1,</span><br><span style="color: hsl(120, 100%, 40%);">+ .psi1threshold = VR_CFG_AMP(20),</span><br><span style="color: hsl(120, 100%, 40%);">+ .psi2threshold = VR_CFG_AMP(5),</span><br><span style="color: hsl(120, 100%, 40%);">+ .psi3threshold = VR_CFG_AMP(1),</span><br><span style="color: hsl(120, 100%, 40%);">+ .psi3enable = 1,</span><br><span style="color: hsl(120, 100%, 40%);">+ .psi4enable = 1,</span><br><span style="color: hsl(120, 100%, 40%);">+ .imon_slope = 0x0,</span><br><span style="color: hsl(120, 100%, 40%);">+ .imon_offset = 0x0,</span><br><span style="color: hsl(120, 100%, 40%);">+ .icc_max = VR_CFG_AMP(35),</span><br><span style="color: hsl(120, 100%, 40%);">+ .voltage_limit = 1520,</span><br><span style="color: hsl(120, 100%, 40%);">+ }"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ # Enable Root port 1</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieRpEnable[0]" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ # Enable CLKREQ#</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieRpClkReqSupport[0]" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ # RP 1 uses SRCCLKREQ1#</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieRpClkReqNumber[0]" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC0)" # Type-C Port 1</span><br><span style="color: hsl(120, 100%, 40%);">+ register "usb2_ports[1]" = "USB2_PORT_MID(OC2)" # Card Reader</span><br><span style="color: hsl(120, 100%, 40%);">+ register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth</span><br><span style="color: hsl(120, 100%, 40%);">+ register "usb2_ports[4]" = "USB2_PORT_MID(OC2)" # Type-A Port (board)</span><br><span style="color: hsl(120, 100%, 40%);">+ register "usb2_ports[6]" = "USB2_PORT_FLEX(OC_SKIP)" # Camera</span><br><span style="color: hsl(120, 100%, 40%);">+ register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # PIC MCU</span><br><span style="color: hsl(120, 100%, 40%);">+ register "usb2_ports[8]" = "USB2_PORT_LONG(OC3)" # Type-A Port (board)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)" # Type-C Port 1</span><br><span style="color: hsl(120, 100%, 40%);">+ register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Card Reader</span><br><span style="color: hsl(120, 100%, 40%);">+ register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC2)" # Type-A Port (board)</span><br><span style="color: hsl(120, 100%, 40%);">+ register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC3)" # Type-A Port (board)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ register "i2c_voltage[4]" = "I2C_VOLTAGE_1V8" # I2C4 is 1.8V</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ # Must leave UART0 enabled or SD/eMMC will not work as PCI</span><br><span style="color: hsl(120, 100%, 40%);">+ register "SerialIoDevMode" = "{</span><br><span style="color: hsl(120, 100%, 40%);">+ [PchSerialIoIndexI2C0] = PchSerialIoPci,</span><br><span style="color: hsl(120, 100%, 40%);">+ [PchSerialIoIndexI2C1] = PchSerialIoPci,</span><br><span style="color: hsl(120, 100%, 40%);">+ [PchSerialIoIndexI2C2] = PchSerialIoDisabled,</span><br><span style="color: hsl(120, 100%, 40%);">+ [PchSerialIoIndexI2C3] = PchSerialIoDisabled,</span><br><span style="color: hsl(120, 100%, 40%);">+ [PchSerialIoIndexI2C4] = PchSerialIoPci,</span><br><span style="color: hsl(120, 100%, 40%);">+ [PchSerialIoIndexI2C5] = PchSerialIoDisabled,</span><br><span style="color: hsl(120, 100%, 40%);">+ [PchSerialIoIndexSpi0] = PchSerialIoDisabled,</span><br><span style="color: hsl(120, 100%, 40%);">+ [PchSerialIoIndexSpi1] = PchSerialIoDisabled,</span><br><span style="color: hsl(120, 100%, 40%);">+ [PchSerialIoIndexUart0] = PchSerialIoPci,</span><br><span style="color: hsl(120, 100%, 40%);">+ [PchSerialIoIndexUart1] = PchSerialIoDisabled,</span><br><span style="color: hsl(120, 100%, 40%);">+ [PchSerialIoIndexUart2] = PchSerialIoSkipInit,</span><br><span style="color: hsl(120, 100%, 40%);">+ }"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ # PL2 override 25W</span><br><span style="color: hsl(120, 100%, 40%);">+ register "tdp_pl2_override" = "25"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ # Send an extra VR mailbox command for the PS4 exit issue</span><br><span style="color: hsl(120, 100%, 40%);">+ register "SendVrMbxCmd" = "2"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ # Lock Down</span><br><span style="color: hsl(120, 100%, 40%);">+ register "common_soc_config" = "{</span><br><span style="color: hsl(120, 100%, 40%);">+ .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,</span><br><span style="color: hsl(120, 100%, 40%);">+ }"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ device cpu_cluster 0 on</span><br><span style="color: hsl(120, 100%, 40%);">+ device lapic 0 on end</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ device domain 0 on</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 00.0 on end # Host Bridge</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 02.0 on end # Integrated Graphics Device</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 14.0 on end # USB xHCI</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 14.1 off end # USB xDCI (OTG)</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 14.2 on end # Thermal Subsystem</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 15.0 on</span><br><span style="color: hsl(120, 100%, 40%);">+ chip drivers/i2c/generic</span><br><span style="color: hsl(120, 100%, 40%);">+ register "hid" = ""ELAN0001""</span><br><span style="color: hsl(120, 100%, 40%);">+ register "desc" = ""ELAN Touchscreen""</span><br><span style="color: hsl(120, 100%, 40%);">+ register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_E7_IRQ)"</span><br><span style="color: hsl(120, 100%, 40%);">+ device i2c 10 on end</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ end # I2C #0</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 15.1 on</span><br><span style="color: hsl(120, 100%, 40%);">+ chip drivers/i2c/generic</span><br><span style="color: hsl(120, 100%, 40%);">+ register "hid" = ""ELAN0000""</span><br><span style="color: hsl(120, 100%, 40%);">+ register "desc" = ""ELAN Touchpad""</span><br><span style="color: hsl(120, 100%, 40%);">+ register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_B3_IRQ)"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "wake" = "GPE0_DW0_05"</span><br><span style="color: hsl(120, 100%, 40%);">+ device i2c 15 on end</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ end # I2C #1</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 15.2 off end # I2C #2</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 15.3 off end # I2C #3</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 16.0 on end # Management Engine Interface 1</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 16.1 off end # Management Engine Interface 2</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 16.2 off end # Management Engine IDE-R</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 16.3 off end # Management Engine KT Redirection</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 16.4 off end # Management Engine Interface 3</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 17.0 off end # SATA</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 19.0 on end # UART #2</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 19.1 off end # I2C #5</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 19.2 on</span><br><span style="color: hsl(120, 100%, 40%);">+ chip drivers/i2c/nau8825</span><br><span style="color: hsl(120, 100%, 40%);">+ register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_F10_IRQ)"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "jkdet_enable" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "jkdet_pull_enable" = "0" # R389</span><br><span style="color: hsl(120, 100%, 40%);">+ register "jkdet_polarity" = "1" # ActiveLow</span><br><span style="color: hsl(120, 100%, 40%);">+ register "vref_impedance" = "2" # 125kOhm</span><br><span style="color: hsl(120, 100%, 40%);">+ register "micbias_voltage" = "6" # 2.754</span><br><span style="color: hsl(120, 100%, 40%);">+ register "sar_threshold_num" = "4"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "sar_threshold[0]" = "0x08"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "sar_threshold[1]" = "0x12"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "sar_threshold[2]" = "0x26"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "sar_threshold[3]" = "0x73"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "sar_hysteresis" = "0"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "sar_voltage" = "6"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "sar_compare_time" = "1" # 1us</span><br><span style="color: hsl(120, 100%, 40%);">+ register "sar_sampling_time" = "1" # 4us</span><br><span style="color: hsl(120, 100%, 40%);">+ register "short_key_debounce" = "3" # 30ms</span><br><span style="color: hsl(120, 100%, 40%);">+ register "jack_insert_debounce" = "7" # 512ms</span><br><span style="color: hsl(120, 100%, 40%);">+ register "jack_eject_debounce" = "0"</span><br><span style="color: hsl(120, 100%, 40%);">+ device i2c 1a on end</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ end # I2C #4</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1c.0 on</span><br><span style="color: hsl(120, 100%, 40%);">+ chip drivers/intel/wifi</span><br><span style="color: hsl(120, 100%, 40%);">+ register "wake" = "GPE0_DW0_16"</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 00.0 on end</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ end # PCI Express Port 1</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1c.1 off end # PCI Express Port 2</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1c.2 off end # PCI Express Port 3</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1c.3 off end # PCI Express Port 4</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1c.4 off end # PCI Express Port 5</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1c.5 off end # PCI Express Port 6</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1c.6 off end # PCI Express Port 7</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1c.7 off end # PCI Express Port 8</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1d.0 off end # PCI Express Port 9</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1d.1 off end # PCI Express Port 10</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1d.2 off end # PCI Express Port 11</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1d.3 off end # PCI Express Port 12</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1e.0 on end # UART #0</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1e.1 off end # UART #1</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1e.2 off end # GSPI #0</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1e.3 off end # GSPI #1</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1e.4 on end # eMMC</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1e.5 off end # SDIO</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1e.6 off end # SDCard</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1f.0 on</span><br><span style="color: hsl(120, 100%, 40%);">+ chip drivers/pc80/tpm</span><br><span style="color: hsl(120, 100%, 40%);">+ device pnp 0c31.0 on end</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ chip ec/google/chromeec</span><br><span style="color: hsl(120, 100%, 40%);">+ device pnp 0c09.0 on end</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ end # LPC Interface</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1f.1 on end # P2SB</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1f.2 on end # Power Management Controller</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1f.3 on</span><br><span style="color: hsl(120, 100%, 40%);">+ chip drivers/generic/max98357a</span><br><span style="color: hsl(120, 100%, 40%);">+ register "sdmode_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E3)"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "sdmode_delay" = "5"</span><br><span style="color: hsl(120, 100%, 40%);">+ device generic 0 on end</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ end # Intel HDA</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1f.4 on end # SMBus</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1f.5 on end # PCH SPI</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1f.6 off end # GbE</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+end</span><br><span>diff --git a/src/mainboard/google/glados/variants/asuka/include/variant/acpi/dptf.asl b/src/mainboard/google/glados/variants/asuka/include/variant/acpi/dptf.asl</span><br><span>new file mode 100644</span><br><span>index 0000000..c2d2914</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/google/glados/variants/asuka/include/variant/acpi/dptf.asl</span><br><span>@@ -0,0 +1,142 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2014 Google Inc.</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2015 Intel Corporation</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define DPTF_CPU_PASSIVE 101</span><br><span style="color: hsl(120, 100%, 40%);">+#define DPTF_CPU_CRITICAL 106</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define DPTF_TSR0_SENSOR_ID 0</span><br><span style="color: hsl(120, 100%, 40%);">+#define DPTF_TSR0_SENSOR_NAME "TMP432_Memory"</span><br><span style="color: hsl(120, 100%, 40%);">+#define DPTF_TSR0_PASSIVE 74</span><br><span style="color: hsl(120, 100%, 40%);">+#define DPTF_TSR0_CRITICAL 79</span><br><span style="color: hsl(120, 100%, 40%);">+#define DPTF_TSR0_ACTIVE_AC0 120</span><br><span style="color: hsl(120, 100%, 40%);">+#define DPTF_TSR0_ACTIVE_AC1 110</span><br><span style="color: hsl(120, 100%, 40%);">+#define DPTF_TSR0_ACTIVE_AC2 47</span><br><span style="color: hsl(120, 100%, 40%);">+#define DPTF_TSR0_ACTIVE_AC3 44</span><br><span style="color: hsl(120, 100%, 40%);">+#define DPTF_TSR0_ACTIVE_AC4 41</span><br><span style="color: hsl(120, 100%, 40%);">+#define DPTF_TSR0_ACTIVE_AC5 38</span><br><span style="color: hsl(120, 100%, 40%);">+#define DPTF_TSR0_ACTIVE_AC6 35</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define DPTF_TSR1_SENSOR_ID 1</span><br><span style="color: hsl(120, 100%, 40%);">+#define DPTF_TSR1_SENSOR_NAME "TMP432_PCH"</span><br><span style="color: hsl(120, 100%, 40%);">+#define DPTF_TSR1_PASSIVE 72</span><br><span style="color: hsl(120, 100%, 40%);">+#define DPTF_TSR1_CRITICAL 77</span><br><span style="color: hsl(120, 100%, 40%);">+#define DPTF_TSR1_ACTIVE_AC0 45</span><br><span style="color: hsl(120, 100%, 40%);">+#define DPTF_TSR1_ACTIVE_AC1 42</span><br><span style="color: hsl(120, 100%, 40%);">+#define DPTF_TSR1_ACTIVE_AC2 39</span><br><span style="color: hsl(120, 100%, 40%);">+#define DPTF_TSR1_ACTIVE_AC3 36</span><br><span style="color: hsl(120, 100%, 40%);">+#define DPTF_TSR1_ACTIVE_AC4 33</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define DPTF_TSR2_SENSOR_ID 2</span><br><span style="color: hsl(120, 100%, 40%);">+#define DPTF_TSR2_SENSOR_NAME "TMP432_Battery"</span><br><span style="color: hsl(120, 100%, 40%);">+#define DPTF_TSR2_PASSIVE 67</span><br><span style="color: hsl(120, 100%, 40%);">+#define DPTF_TSR2_CRITICAL 72</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define DPTF_ENABLE_CHARGER</span><br><span style="color: hsl(120, 100%, 40%);">+#define DPTF_ENABLE_FAN_CONTROL</span><br><span style="color: hsl(120, 100%, 40%);">+#define DPTF_ENABLE_FAN_CONTROL_TSR1</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* Charger performance states, board-specific values from charger and EC */</span><br><span style="color: hsl(120, 100%, 40%);">+Name (CHPS, Package () {</span><br><span style="color: hsl(120, 100%, 40%);">+ Package () { 0, 0, 0, 0, 255, 0x6a4, "mA", 0 }, /* 1.7A (MAX) */</span><br><span style="color: hsl(120, 100%, 40%);">+ Package () { 0, 0, 0, 0, 24, 0x600, "mA", 0 }, /* 1.5A */</span><br><span style="color: hsl(120, 100%, 40%);">+ Package () { 0, 0, 0, 0, 16, 0x400, "mA", 0 }, /* 1.0A */</span><br><span style="color: hsl(120, 100%, 40%);">+ Package () { 0, 0, 0, 0, 8, 0x200, "mA", 0 }, /* 0.5A */</span><br><span style="color: hsl(120, 100%, 40%);">+ Package () { 0, 0, 0, 0, 0, 0x000, "mA", 0 }, /* 0.0A */</span><br><span style="color: hsl(120, 100%, 40%);">+})</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#ifdef DPTF_ENABLE_FAN_CONTROL</span><br><span style="color: hsl(120, 100%, 40%);">+/* DFPS: Fan Performance States */</span><br><span style="color: hsl(120, 100%, 40%);">+Name (DFPS, Package () {</span><br><span style="color: hsl(120, 100%, 40%);">+ 0, // Revision</span><br><span style="color: hsl(120, 100%, 40%);">+ /*</span><br><span style="color: hsl(120, 100%, 40%);">+ * TODO : Need to update this Table after characterization.</span><br><span style="color: hsl(120, 100%, 40%);">+ * These are initial reference values.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Control, Trip Point, Speed, NoiseLevel, Power */</span><br><span style="color: hsl(120, 100%, 40%);">+ Package () {100, 0xFFFFFFFF, 4986, 220, 2200},</span><br><span style="color: hsl(120, 100%, 40%);">+ Package () {90, 0xFFFFFFFF, 4804, 180, 1800},</span><br><span style="color: hsl(120, 100%, 40%);">+ Package () {80, 0xFFFFFFFF, 4512, 145, 1450},</span><br><span style="color: hsl(120, 100%, 40%);">+ Package () {70, 0xFFFFFFFF, 4204, 115, 1150},</span><br><span style="color: hsl(120, 100%, 40%);">+ Package () {60, 0xFFFFFFFF, 3838, 90, 900},</span><br><span style="color: hsl(120, 100%, 40%);">+ Package () {50, 0xFFFFFFFF, 3402, 65, 650},</span><br><span style="color: hsl(120, 100%, 40%);">+ Package () {40, 0xFFFFFFFF, 2904, 45, 450},</span><br><span style="color: hsl(120, 100%, 40%);">+ Package () {30, 0xFFFFFFFF, 2337, 30, 300},</span><br><span style="color: hsl(120, 100%, 40%);">+ Package () {20, 0xFFFFFFFF, 1608, 15, 150},</span><br><span style="color: hsl(120, 100%, 40%);">+ Package () {10, 0xFFFFFFFF, 800, 10, 100},</span><br><span style="color: hsl(120, 100%, 40%);">+ Package () {0, 0xFFFFFFFF, 0, 0, 50}</span><br><span style="color: hsl(120, 100%, 40%);">+})</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+Name (DART, Package () {</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Fan effect on CPU */</span><br><span style="color: hsl(120, 100%, 40%);">+ 0, // Revision</span><br><span style="color: hsl(120, 100%, 40%);">+ Package () {</span><br><span style="color: hsl(120, 100%, 40%);">+ /*</span><br><span style="color: hsl(120, 100%, 40%);">+ * Source, Target, Weight, AC0, AC1, AC2, AC3, AC4, AC5, AC6,</span><br><span style="color: hsl(120, 100%, 40%);">+ * AC7, AC8, AC9</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+ \_SB.DPTF.TFN1, \_SB.PCI0.B0D4, 100, 0, 0, 0, 0, 0, 0, 0,</span><br><span style="color: hsl(120, 100%, 40%);">+ 0, 0, 0</span><br><span style="color: hsl(120, 100%, 40%);">+ },</span><br><span style="color: hsl(120, 100%, 40%);">+ Package () {</span><br><span style="color: hsl(120, 100%, 40%);">+ \_SB.DPTF.TFN1, \_SB.DPTF.TSR0, 100, 0, 0, 0, 0, 0, 0,</span><br><span style="color: hsl(120, 100%, 40%);">+ 0, 0, 0, 0</span><br><span style="color: hsl(120, 100%, 40%);">+ },</span><br><span style="color: hsl(120, 100%, 40%);">+ Package () {</span><br><span style="color: hsl(120, 100%, 40%);">+ \_SB.DPTF.TFN1, \_SB.DPTF.TSR1, 100, 79, 66, 50, 41, 39, 0,</span><br><span style="color: hsl(120, 100%, 40%);">+ 0, 0, 0, 0</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+})</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+Name (DTRT, Package () {</span><br><span style="color: hsl(120, 100%, 40%);">+ /* CPU Throttle Effect on CPU */</span><br><span style="color: hsl(120, 100%, 40%);">+ Package () { \_SB.PCI0.B0D4, \_SB.PCI0.B0D4, 100, 10, 0, 0, 0, 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* CPU Effect on Temp Sensor 0 */</span><br><span style="color: hsl(120, 100%, 40%);">+ Package () { \_SB.PCI0.B0D4, \_SB.DPTF.TSR0, 100, 10, 0, 0, 0, 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#ifdef DPTF_ENABLE_CHARGER</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Charger Effect on Temp Sensor 1 */</span><br><span style="color: hsl(120, 100%, 40%);">+ Package () { \_SB.DPTF.TCHG, \_SB.DPTF.TSR1, 200, 10, 0, 0, 0, 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* CPU Effect on Temp Sensor 1 */</span><br><span style="color: hsl(120, 100%, 40%);">+ Package () { \_SB.PCI0.B0D4, \_SB.DPTF.TSR1, 100, 10, 0, 0, 0, 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* CPU Effect on Temp Sensor 2 */</span><br><span style="color: hsl(120, 100%, 40%);">+ Package () { \_SB.PCI0.B0D4, \_SB.DPTF.TSR2, 100, 10, 0, 0, 0, 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+})</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+Name (MPPC, Package ()</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x2, /* Revision */</span><br><span style="color: hsl(120, 100%, 40%);">+ Package () { /* Power Limit 1 */</span><br><span style="color: hsl(120, 100%, 40%);">+ 0, /* PowerLimitIndex, 0 for Power Limit 1 */</span><br><span style="color: hsl(120, 100%, 40%);">+ 3000, /* PowerLimitMinimum */</span><br><span style="color: hsl(120, 100%, 40%);">+ 15000, /* PowerLimitMaximum */</span><br><span style="color: hsl(120, 100%, 40%);">+ 28000, /* TimeWindowMinimum */</span><br><span style="color: hsl(120, 100%, 40%);">+ 28000, /* TimeWindowMaximum */</span><br><span style="color: hsl(120, 100%, 40%);">+ 100 /* StepSize */</span><br><span style="color: hsl(120, 100%, 40%);">+ },</span><br><span style="color: hsl(120, 100%, 40%);">+ Package () { /* Power Limit 2 */</span><br><span style="color: hsl(120, 100%, 40%);">+ 1, /* PowerLimitIndex, 1 for Power Limit 2 */</span><br><span style="color: hsl(120, 100%, 40%);">+ 25000, /* PowerLimitMinimum */</span><br><span style="color: hsl(120, 100%, 40%);">+ 25000, /* PowerLimitMaximum */</span><br><span style="color: hsl(120, 100%, 40%);">+ 1000, /* TimeWindowMinimum */</span><br><span style="color: hsl(120, 100%, 40%);">+ 1000, /* TimeWindowMaximum */</span><br><span style="color: hsl(120, 100%, 40%);">+ 100 /* StepSize */</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+})</span><br><span>diff --git a/src/mainboard/google/glados/variants/asuka/include/variant/acpi/mainboard.asl b/src/mainboard/google/glados/variants/asuka/include/variant/acpi/mainboard.asl</span><br><span>new file mode 100644</span><br><span>index 0000000..e69de29</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/google/glados/variants/asuka/include/variant/acpi/mainboard.asl</span><br><span>diff --git a/src/mainboard/google/glados/variants/asuka/include/variant/ec.h b/src/mainboard/google/glados/variants/asuka/include/variant/ec.h</span><br><span>new file mode 100644</span><br><span>index 0000000..e69de29</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/google/glados/variants/asuka/include/variant/ec.h</span><br><span>diff --git a/src/mainboard/google/glados/variants/asuka/include/variant/gpio.h b/src/mainboard/google/glados/variants/asuka/include/variant/gpio.h</span><br><span>new file mode 100644</span><br><span>index 0000000..30c0b01</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/google/glados/variants/asuka/include/variant/gpio.h</span><br><span>@@ -0,0 +1,238 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2013 Google Inc.</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2015 Intel Corporation</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef MAINBOARD_GPIO_H</span><br><span style="color: hsl(120, 100%, 40%);">+#define MAINBOARD_GPIO_H</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/gpe.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/gpio.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* EC in RW */</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_EC_IN_RW GPP_C6</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* BIOS Flash Write Protect */</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_PCH_WP GPP_C23</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* Memory configuration board straps */</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_MEM_CONFIG_0 GPP_C12</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_MEM_CONFIG_1 GPP_C13</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_MEM_CONFIG_2 GPP_C14</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_MEM_CONFIG_3 GPP_C15</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* EC wake is LAN_WAKE# which is a special DeepSX wake pin */</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPE_EC_WAKE GPE0_LAN_WAK</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* GPP_B16 is WLAN_WAKE. GPP_B group is routed to DW0 in the GPE0 block */</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPE_WLAN_WAKE GPE0_DW0_16</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* GPP_B5 is TOUCHPAD WAKE. GPP_B group is routed to DW0 in the GPE0 block */</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPE_TOUCHPAD_WAKE GPE0_DW0_05</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* Input device interrupt configuration */</span><br><span style="color: hsl(120, 100%, 40%);">+#define TOUCHPAD_INT_L GPP_B3_IRQ</span><br><span style="color: hsl(120, 100%, 40%);">+#define TOUCHSCREEN_INT_L GPP_E7_IRQ</span><br><span style="color: hsl(120, 100%, 40%);">+#define MIC_INT_L GPP_F10_IRQ</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* GPP_E16 is EC_SCI_L. GPP_E group is routed to DW2 in the GPE0 block */</span><br><span style="color: hsl(120, 100%, 40%);">+#define EC_SCI_GPI GPE0_DW2_16</span><br><span style="color: hsl(120, 100%, 40%);">+#define EC_SMI_GPI GPP_E15</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * GPP_E3 is AUDIO_DB_ID.</span><br><span style="color: hsl(120, 100%, 40%);">+ * It is a dual purpose GPIO, used for Audio Daughter</span><br><span style="color: hsl(120, 100%, 40%);">+ * Board Identification & to control the shutdown mode pin</span><br><span style="color: hsl(120, 100%, 40%);">+ * of the Maxim amp.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+#define AUDIO_DB_ID GPP_E3</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef __ACPI__</span><br><span style="color: hsl(120, 100%, 40%);">+/* Pad configuration in ramstage. */</span><br><span style="color: hsl(120, 100%, 40%);">+static const struct pad_config gpio_table[] = {</span><br><span style="color: hsl(120, 100%, 40%);">+/* EC_PCH_RCIN */ PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* LPC_LAD_0 */ PAD_CFG_NF(GPP_A1, 20K_PU, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* LPC_LAD_1 */ PAD_CFG_NF(GPP_A2, 20K_PU, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* LPC_LAD_2 */ PAD_CFG_NF(GPP_A3, 20K_PU, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* LPC_LAD_3 */ PAD_CFG_NF(GPP_A4, 20K_PU, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* LPC_FRAME */ PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* LPC_SERIRQ */ PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* SD_CD_WAKE */ PAD_CFG_GPI_GPIO_DRIVER(GPP_A7, 20K_PU, DEEP),</span><br><span style="color: hsl(120, 100%, 40%);">+/* LPC_CLKRUN */ PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* EC_LPC_CLK */ PAD_CFG_NF(GPP_A9, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* PCH_LPC_CLK */ PAD_CFG_NC(GPP_A10),</span><br><span style="color: hsl(120, 100%, 40%);">+/* EC_HID_INT */ PAD_CFG_NC(GPP_A11),</span><br><span style="color: hsl(120, 100%, 40%);">+/* ISH_KB_PROX_INT */ PAD_CFG_NC(GPP_A12),</span><br><span style="color: hsl(120, 100%, 40%);">+/* PCH_SUSPWRACB */ PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* PM_SUS_STAT */ PAD_CFG_NC(GPP_A14),</span><br><span style="color: hsl(120, 100%, 40%);">+/* PCH_SUSACK */ PAD_CFG_NF(GPP_A15, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* SD_1P8_SEL */ PAD_CFG_NC(GPP_A16),</span><br><span style="color: hsl(120, 100%, 40%);">+/* SD_PWR_EN */ PAD_CFG_NC(GPP_A17),</span><br><span style="color: hsl(120, 100%, 40%);">+/* ACCEL INTERRUPT */ PAD_CFG_NC(GPP_A18),</span><br><span style="color: hsl(120, 100%, 40%);">+/* ISH_GP1 */ PAD_CFG_NC(GPP_A19),</span><br><span style="color: hsl(120, 100%, 40%);">+/* GYRO_DRDY */ PAD_CFG_NC(GPP_A20),</span><br><span style="color: hsl(120, 100%, 40%);">+/* FLIP_ACCEL_INT */ PAD_CFG_NC(GPP_A21),</span><br><span style="color: hsl(120, 100%, 40%);">+/* GYRO_INT */ PAD_CFG_NC(GPP_A22),</span><br><span style="color: hsl(120, 100%, 40%);">+/* ISH_GP5 */ PAD_CFG_NC(GPP_A23),</span><br><span style="color: hsl(120, 100%, 40%);">+/* CORE_VID0 */ PAD_CFG_NC(GPP_B0),</span><br><span style="color: hsl(120, 100%, 40%);">+/* CORE_VID1 */ PAD_CFG_NC(GPP_B1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* HSJ_MIC_DET */ PAD_CFG_GPI_GPIO_DRIVER(GPP_B2, NONE, DEEP),</span><br><span style="color: hsl(120, 100%, 40%);">+/* TRACKPAD_INT */ PAD_CFG_GPI_APIC(GPP_B3, NONE, PLTRST),</span><br><span style="color: hsl(120, 100%, 40%);">+/* BT_RF_KILL */ PAD_CFG_NC(GPP_B4),</span><br><span style="color: hsl(120, 100%, 40%);">+/* SRCCLKREQ0# */ PAD_CFG_GPI_ACPI_SCI(GPP_B5, NONE, DEEP, YES), /* TOUCHPAD WAKE */</span><br><span style="color: hsl(120, 100%, 40%);">+/* WIFI_CLK_REQ */ PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* SRCCLKREQ2 */ PAD_CFG_NC(GPP_B7),</span><br><span style="color: hsl(120, 100%, 40%);">+/* AUDIO_INT_WAK */ PAD_CFG_GPI_ACPI_SCI(GPP_B8, NONE, DEEP, YES),</span><br><span style="color: hsl(120, 100%, 40%);">+/* SRCCLKREQ4 */ PAD_CFG_NC(GPP_B9),</span><br><span style="color: hsl(120, 100%, 40%);">+/* SRCCLKREQ5# */ PAD_CFG_NC(GPP_B10),</span><br><span style="color: hsl(120, 100%, 40%);">+/* MPHY_EXT_PWR_GATE */ PAD_CFG_NC(GPP_B11),</span><br><span style="color: hsl(120, 100%, 40%);">+/* PM_SLP_S0 */ PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* PCH_PLT_RST */ PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* PCH_BUZZER */ PAD_CFG_GPI_GPIO_DRIVER(GPP_B14, NONE, DEEP),</span><br><span style="color: hsl(120, 100%, 40%);">+/* GSPI0_CS# */ PAD_CFG_NC(GPP_B15),</span><br><span style="color: hsl(120, 100%, 40%);">+/* WLAN_PCIE_WAKE */ PAD_CFG_GPI_ACPI_SCI(GPP_B16, NONE, DEEP, YES),</span><br><span style="color: hsl(120, 100%, 40%);">+/* SSD_PCIE_WAKE */ PAD_CFG_NC(GPP_B17),</span><br><span style="color: hsl(120, 100%, 40%);">+/* GSPI0_MOSI */ PAD_CFG_NC(GPP_B18),</span><br><span style="color: hsl(120, 100%, 40%);">+/* CCODEC_SPI_CS */ PAD_CFG_NC(GPP_B19),</span><br><span style="color: hsl(120, 100%, 40%);">+/* CODEC_SPI_CLK */ PAD_CFG_NC(GPP_B20),</span><br><span style="color: hsl(120, 100%, 40%);">+/* CODEC_SPI_MISO */ PAD_CFG_NC(GPP_B21),</span><br><span style="color: hsl(120, 100%, 40%);">+/* CODEC_SPI_MOSI */ PAD_CFG_NC(GPP_B22),</span><br><span style="color: hsl(120, 100%, 40%);">+/* SM1ALERT# */ PAD_CFG_NC(GPP_B23),</span><br><span style="color: hsl(120, 100%, 40%);">+/* SMB_CLK */ PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* SMB_DATA */ PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* SMBALERT# */ PAD_CFG_GPO(GPP_C2, 0, DEEP),</span><br><span style="color: hsl(120, 100%, 40%);">+/* M2_WWAN_PWREN */ PAD_CFG_NC(GPP_C3),</span><br><span style="color: hsl(120, 100%, 40%);">+/* SML0DATA */ PAD_CFG_NC(GPP_C4),</span><br><span style="color: hsl(120, 100%, 40%);">+/* SML0ALERT# */ PAD_CFG_NC(GPP_C5),</span><br><span style="color: hsl(120, 100%, 40%);">+/* EC_IN_RW */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C6, NONE, DEEP),</span><br><span style="color: hsl(120, 100%, 40%);">+/* USB_CTL */ PAD_CFG_NC(GPP_C7),</span><br><span style="color: hsl(120, 100%, 40%);">+/* UART0_RXD */ PAD_CFG_NC(GPP_C8),</span><br><span style="color: hsl(120, 100%, 40%);">+/* UART0_TXD */ PAD_CFG_NC(GPP_C9),</span><br><span style="color: hsl(120, 100%, 40%);">+/* NFC_RST* */ PAD_CFG_NC(GPP_C10),</span><br><span style="color: hsl(120, 100%, 40%);">+/* EN_PP3300_KEPLER */ PAD_CFG_NC(GPP_C11),</span><br><span style="color: hsl(120, 100%, 40%);">+/* PCH_MEM_CFG0 */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C12, NONE, DEEP),</span><br><span style="color: hsl(120, 100%, 40%);">+/* PCH_MEM_CFG1 */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C13, NONE, DEEP),</span><br><span style="color: hsl(120, 100%, 40%);">+/* PCH_MEM_CFG2 */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C14, NONE, DEEP),</span><br><span style="color: hsl(120, 100%, 40%);">+/* PCH_MEM_CFG3 */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C15, NONE, DEEP),</span><br><span style="color: hsl(120, 100%, 40%);">+/* I2C0_SDA */ PAD_CFG_NF(GPP_C16, 5K_PU, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* I2C0_SCL */ PAD_CFG_NF(GPP_C17, 5K_PU, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* I2C1_SDA */ PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* I2C1_SCL */ PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* GD_UART2_RXD */ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* GD_UART2_TXD */ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* TCH_PNL_PWREN */ PAD_CFG_GPO(GPP_C22, 1, DEEP),</span><br><span style="color: hsl(120, 100%, 40%);">+/* SPI_WP_STATUS */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, 20K_PU, DEEP),</span><br><span style="color: hsl(120, 100%, 40%);">+/* ITCH_SPI_CS */ PAD_CFG_NC(GPP_D0),</span><br><span style="color: hsl(120, 100%, 40%);">+/* ITCH_SPI_CLK */ PAD_CFG_NC(GPP_D1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* ITCH_SPI_MISO_1 */ PAD_CFG_NC(GPP_D2),</span><br><span style="color: hsl(120, 100%, 40%);">+/* ITCH_SPI_MISO_0 */ PAD_CFG_NC(GPP_D3),</span><br><span style="color: hsl(120, 100%, 40%);">+/* CAM_FLASH_STROBE */ PAD_CFG_NC(GPP_D4),</span><br><span style="color: hsl(120, 100%, 40%);">+/* EN_PP3300_DX_EMMC */ PAD_CFG_NC(GPP_D5),</span><br><span style="color: hsl(120, 100%, 40%);">+/* EN_PP1800_DX_EMMC */ PAD_CFG_NC(GPP_D6),</span><br><span style="color: hsl(120, 100%, 40%);">+/* SH_I2C1_SDA */ PAD_CFG_NC(GPP_D7),</span><br><span style="color: hsl(120, 100%, 40%);">+/* SH_I2C1_SCL */ PAD_CFG_NC(GPP_D8),</span><br><span style="color: hsl(120, 100%, 40%);">+/* ISH_SPI_CSB */ PAD_CFG_NC(GPP_D9),</span><br><span style="color: hsl(120, 100%, 40%);">+/* USB_A0_ILIM_SEL */ PAD_CFG_GPO(GPP_D10, 0, DEEP),</span><br><span style="color: hsl(120, 100%, 40%);">+/* USB_A1_ILIM_SEL */ PAD_CFG_GPO(GPP_D11, 0, DEEP),</span><br><span style="color: hsl(120, 100%, 40%);">+/* EN_PP3300_DX_CAM */ PAD_CFG_NC(GPP_D12),</span><br><span style="color: hsl(120, 100%, 40%);">+/* EN_PP1800_DX_AUDIO */PAD_CFG_NC(GPP_D13),</span><br><span style="color: hsl(120, 100%, 40%);">+/* ISH_UART0_TXD */ PAD_CFG_NC(GPP_D14),</span><br><span style="color: hsl(120, 100%, 40%);">+/* ISH_UART0_RTS */ PAD_CFG_NC(GPP_D15),</span><br><span style="color: hsl(120, 100%, 40%);">+/* ISH_UART0_CTS */ PAD_CFG_NC(GPP_D16),</span><br><span style="color: hsl(120, 100%, 40%);">+/* DMIC_CLK_1 */ PAD_CFG_NC(GPP_D17),</span><br><span style="color: hsl(120, 100%, 40%);">+/* DMIC_DATA_1 */ PAD_CFG_NC(GPP_D18),</span><br><span style="color: hsl(120, 100%, 40%);">+/* DMIC_CLK_0 */ PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* DMIC_DATA_0 */ PAD_CFG_NF(GPP_D20, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* ITCH_SPI_D2 */ PAD_CFG_NC(GPP_D21),</span><br><span style="color: hsl(120, 100%, 40%);">+/* ITCH_SPI_D3 */ PAD_CFG_NC(GPP_D22),</span><br><span style="color: hsl(120, 100%, 40%);">+/* I2S_MCLK */ PAD_CFG_NF(GPP_D23, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* SPI_TPM_IRQ */ PAD_CFG_GPI_APIC(GPP_E0, NONE, PLTRST),</span><br><span style="color: hsl(120, 100%, 40%);">+/* SATAXPCIE1 */ PAD_CFG_NC(GPP_E1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* SSD_PEDET */ PAD_CFG_NC(GPP_E2),</span><br><span style="color: hsl(120, 100%, 40%);">+/* AUDIO_DB_ID */ PAD_CFG_GPI_GPIO_DRIVER(GPP_E3, NONE, DEEP),</span><br><span style="color: hsl(120, 100%, 40%);">+/* SSD_SATA_DEVSLP */ PAD_CFG_NC(GPP_E4),</span><br><span style="color: hsl(120, 100%, 40%);">+/* SATA_DEVSLP1 */ PAD_CFG_NC(GPP_E5),</span><br><span style="color: hsl(120, 100%, 40%);">+/* SATA_DEVSLP2 */ PAD_CFG_NC(GPP_E6),</span><br><span style="color: hsl(120, 100%, 40%);">+/* TCH_PNL_INTR* */ PAD_CFG_GPI_APIC(GPP_E7, NONE, PLTRST),</span><br><span style="color: hsl(120, 100%, 40%);">+/* SATALED# */ PAD_CFG_NC(GPP_E8),</span><br><span style="color: hsl(120, 100%, 40%);">+/* USB2_OC_0 */ PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* USB2_OC_1 */ PAD_CFG_NF(GPP_E10, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* USB2_OC_2 */ PAD_CFG_NF(GPP_E11, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* USB2_OC_3 */ PAD_CFG_NF(GPP_E12, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* DDI1_HPD */ PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* DDI2_HPD */ PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* EC_SMI */ PAD_CFG_GPI_ACPI_SMI(GPP_E15, NONE, DEEP, YES),</span><br><span style="color: hsl(120, 100%, 40%);">+/* EC_SCI */ PAD_CFG_GPI_ACPI_SCI(GPP_E16, NONE, DEEP, YES),</span><br><span style="color: hsl(120, 100%, 40%);">+/* EDP_HPD */ PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* DDPB_CTRLCLK */ PAD_CFG_NF(GPP_E18, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* DDPB_CTRLDATA */ PAD_CFG_NF(GPP_E19, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* DDPC_CTRLCLK */ PAD_CFG_NC(GPP_E20),</span><br><span style="color: hsl(120, 100%, 40%);">+/* DDPC_CTRLDATA */ PAD_CFG_NF(GPP_E21, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* DDPD_CTRLCLK */ PAD_CFG_NC(GPP_E22),</span><br><span style="color: hsl(120, 100%, 40%);">+/* TCH_PNL_RST */ PAD_CFG_GPO(GPP_E23, 1, DEEP),</span><br><span style="color: hsl(120, 100%, 40%);">+/* I2S2_SCLK */ PAD_CFG_NC(GPP_F0),</span><br><span style="color: hsl(120, 100%, 40%);">+/* I2S2_SFRM */ PAD_CFG_NC(GPP_F1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* I2S2_TXD */ PAD_CFG_NC(GPP_F2),</span><br><span style="color: hsl(120, 100%, 40%);">+/* I2S2_RXD */ PAD_CFG_NC(GPP_F3),</span><br><span style="color: hsl(120, 100%, 40%);">+/* I2C2_SDA */ PAD_CFG_NC(GPP_F4),</span><br><span style="color: hsl(120, 100%, 40%);">+/* I2C2_SCL */ PAD_CFG_NC(GPP_F5),</span><br><span style="color: hsl(120, 100%, 40%);">+/* I2C3_SDA */ PAD_CFG_NC(GPP_F6),</span><br><span style="color: hsl(120, 100%, 40%);">+/* I2C3_SCL */ PAD_CFG_NC(GPP_F7),</span><br><span style="color: hsl(120, 100%, 40%);">+/* I2C4_SDA */ PAD_CFG_NF(GPP_F8, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* I2C4_SDA */ PAD_CFG_NF(GPP_F9, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* AUDIO_IRQ */ PAD_CFG_GPI_APIC(GPP_F10, NONE, PLTRST),</span><br><span style="color: hsl(120, 100%, 40%);">+/* AUDIO_IRQ */ PAD_CFG_GPI_ACPI_SCI(GPP_F11, NONE, DEEP, YES),</span><br><span style="color: hsl(120, 100%, 40%);">+/* EMMC_CMD */ PAD_CFG_NF(GPP_F12, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* EMMC_DATA0 */ PAD_CFG_NF(GPP_F13, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* EMMC_DATA1 */ PAD_CFG_NF(GPP_F14, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* EMMC_DATA2 */ PAD_CFG_NF(GPP_F15, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* EMMC_DATA3 */ PAD_CFG_NF(GPP_F16, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* EMMC_DATA4 */ PAD_CFG_NF(GPP_F17, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* EMMC_DATA5 */ PAD_CFG_NF(GPP_F18, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* EMMC_DATA6 */ PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* EMMC_DATA7 */ PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* EMMC_RCLK */ PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* EMMC_CLK */ PAD_CFG_NF(GPP_F22, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* BOOT_BEEP */ PAD_CFG_GPO(GPP_F23, 0, DEEP),</span><br><span style="color: hsl(120, 100%, 40%);">+/* SD_CMD */ PAD_CFG_NC(GPP_G0),</span><br><span style="color: hsl(120, 100%, 40%);">+/* SD_DATA0 */ PAD_CFG_NC(GPP_G1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* SD_DATA1 */ PAD_CFG_NC(GPP_G2),</span><br><span style="color: hsl(120, 100%, 40%);">+/* SD_DATA2 */ PAD_CFG_NC(GPP_G3),</span><br><span style="color: hsl(120, 100%, 40%);">+/* SD_DATA3 */ PAD_CFG_NC(GPP_G4),</span><br><span style="color: hsl(120, 100%, 40%);">+/* SD_CD# */ PAD_CFG_NC(GPP_G5),</span><br><span style="color: hsl(120, 100%, 40%);">+/* SD_CLK */ PAD_CFG_NC(GPP_G6),</span><br><span style="color: hsl(120, 100%, 40%);">+/* SD_WP */ PAD_CFG_NC(GPP_G7),</span><br><span style="color: hsl(120, 100%, 40%);">+/* PCH_BATLOW */ PAD_CFG_NF(GPD0, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* EC_PCH_ACPRESENT */ PAD_CFG_NF(GPD1, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* EC_PCH_WAKE */ PAD_CFG_NF(GPD2, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* EC_PCH_PWRBTN */ PAD_CFG_NF(GPD3, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* PM_SLP_S3# */ PAD_CFG_NF(GPD4, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* PM_SLP_S4# */ PAD_CFG_NF(GPD5, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* PM_SLP_SA# */ PAD_CFG_NF(GPD6, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* GPD7 */ PAD_CFG_NC(GPD7),</span><br><span style="color: hsl(120, 100%, 40%);">+/* PM_SUSCLK */ PAD_CFG_NF(GPD8, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* PCH_SLP_WLAN# */ PAD_CFG_NC(GPD9),</span><br><span style="color: hsl(120, 100%, 40%);">+/* PM_SLP_S5# */ PAD_CFG_NC(GPD10),</span><br><span style="color: hsl(120, 100%, 40%);">+/* LANPHYC */ PAD_CFG_NC(GPD11),</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* Early pad configuration in romstage. */</span><br><span style="color: hsl(120, 100%, 40%);">+static const struct pad_config early_gpio_table[] = {</span><br><span style="color: hsl(120, 100%, 40%);">+/* SPI_WP_STATUS */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, 20K_PU, DEEP),</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span>diff --git a/src/mainboard/google/glados/variants/asuka/variant.c b/src/mainboard/google/glados/variants/asuka/variant.c</span><br><span>new file mode 100644</span><br><span>index 0000000..326ee8a</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/google/glados/variants/asuka/variant.c</span><br><span>@@ -0,0 +1,54 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2015 Google Inc.</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2015 Intel Corporation</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <stdint.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <string.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <baseboard/variant.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/pei_data.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/pei_wrapper.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+void mainboard_fill_pei_data(struct pei_data *pei_data)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ /* DQ byte map */</span><br><span style="color: hsl(120, 100%, 40%);">+ const u8 dq_map[2][12] = {</span><br><span style="color: hsl(120, 100%, 40%);">+ { 0x0F, 0xF0, 0x00, 0xF0, 0x0F, 0xF0 ,</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x0F, 0x00, 0xFF, 0x00, 0xFF, 0x00 },</span><br><span style="color: hsl(120, 100%, 40%);">+ { 0x0F, 0xF0, 0x00, 0xF0, 0x0F, 0xF0 ,</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x0F, 0x00, 0xFF, 0x00, 0xFF, 0x00 } };</span><br><span style="color: hsl(120, 100%, 40%);">+ /* DQS CPU<>DRAM map */</span><br><span style="color: hsl(120, 100%, 40%);">+ const u8 dqs_map[2][8] = {</span><br><span style="color: hsl(120, 100%, 40%);">+ { 0, 1, 3, 2, 6, 5, 4, 7 },</span><br><span style="color: hsl(120, 100%, 40%);">+ { 2, 3, 0, 1, 6, 7, 4, 5 } };</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Rcomp resistor */</span><br><span style="color: hsl(120, 100%, 40%);">+ const u16 RcompResistor[3] = { 200, 81, 162 };</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Rcomp target */</span><br><span style="color: hsl(120, 100%, 40%);">+ const u16 RcompTarget[5] = { 100, 40, 40, 23, 40 };</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ memcpy(pei_data->dq_map, dq_map, sizeof(dq_map));</span><br><span style="color: hsl(120, 100%, 40%);">+ memcpy(pei_data->dqs_map, dqs_map, sizeof(dqs_map));</span><br><span style="color: hsl(120, 100%, 40%);">+ memcpy(pei_data->RcompResistor, RcompResistor,</span><br><span style="color: hsl(120, 100%, 40%);">+ sizeof(RcompResistor));</span><br><span style="color: hsl(120, 100%, 40%);">+ memcpy(pei_data->RcompTarget, RcompTarget,</span><br><span style="color: hsl(120, 100%, 40%);">+ sizeof(RcompTarget));</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+int is_dual_channel(const int spd_index)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Per Makefile.inc, dual channel indices 1,3,5 */</span><br><span style="color: hsl(120, 100%, 40%);">+ return (spd_index & 0x1);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/27421">change 27421</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/27421"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I591578fea2514a28c75177835807c3f250904577 </div>
<div style="display:none"> Gerrit-Change-Number: 27421 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Matt DeVillier <matt.devillier@gmail.com> </div>