<p>Elyes HAOUAS has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/27408">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">src/soc: Use "foo *bar" instead of "foo* bar"<br><br>Change-Id: I21680354f33916b7b4d913f51a842b5d6c2ecef3<br>Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr><br>---<br>M src/soc/amd/common/block/include/amdblocks/amd_pci_util.h<br>M src/soc/intel/baytrail/include/soc/romstage.h<br>M src/soc/intel/baytrail/romstage/romstage.c<br>M src/soc/intel/braswell/pmutil.c<br>M src/soc/intel/braswell/ramstage.c<br>M src/soc/intel/cannonlake/bootblock/report_platform.c<br>M src/soc/intel/common/block/include/intelblocks/pmclib.h<br>M src/soc/intel/denverton_ns/pmutil.c<br>M src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c<br>M src/soc/intel/fsp_broadwell_de/pmutil.c<br>M src/soc/intel/skylake/bootblock/report_platform.c<br>M src/soc/intel/skylake/me.c<br>M src/soc/nvidia/tegra/dc.h<br>M src/soc/nvidia/tegra124/clock.c<br>M src/soc/nvidia/tegra124/display.c<br>M src/soc/nvidia/tegra124/dp.c<br>M src/soc/nvidia/tegra124/include/soc/clock.h<br>M src/soc/nvidia/tegra210/clock.c<br>M src/soc/nvidia/tegra210/dc.c<br>M src/soc/nvidia/tegra210/dsi.c<br>M src/soc/nvidia/tegra210/flow_ctrl.c<br>M src/soc/nvidia/tegra210/include/soc/id.h<br>M src/soc/nvidia/tegra210/mtc.c<br>M src/soc/nvidia/tegra210/power.c<br>M src/soc/qualcomm/ipq806x/usb.c<br>M src/soc/samsung/exynos5250/include/soc/alternate_cbfs.h<br>M src/soc/samsung/exynos5250/include/soc/power.h<br>M src/soc/samsung/exynos5420/dp_lowlevel.c<br>M src/soc/samsung/exynos5420/include/soc/alternate_cbfs.h<br>M src/soc/samsung/exynos5420/include/soc/power.h<br>M src/soc/samsung/exynos5420/smp.c<br>31 files changed, 79 insertions(+), 79 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/08/27408/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/soc/amd/common/block/include/amdblocks/amd_pci_util.h b/src/soc/amd/common/block/include/amdblocks/amd_pci_util.h</span><br><span>index 92d27dc..3a55244 100644</span><br><span>--- a/src/soc/amd/common/block/include/amdblocks/amd_pci_util.h</span><br><span>+++ b/src/soc/amd/common/block/include/amdblocks/amd_pci_util.h</span><br><span>@@ -31,7 +31,7 @@</span><br><span> </span><br><span> struct irq_idx_name {</span><br><span> uint8_t index;</span><br><span style="color: hsl(0, 100%, 40%);">- const char * const name;</span><br><span style="color: hsl(120, 100%, 40%);">+ const char *const name;</span><br><span> };</span><br><span> </span><br><span> extern const struct pirq_struct *pirq_data_ptr;</span><br><span>diff --git a/src/soc/intel/baytrail/include/soc/romstage.h b/src/soc/intel/baytrail/include/soc/romstage.h</span><br><span>index a3f1fc7..ba12c8f 100644</span><br><span>--- a/src/soc/intel/baytrail/include/soc/romstage.h</span><br><span>+++ b/src/soc/intel/baytrail/include/soc/romstage.h</span><br><span>@@ -31,7 +31,7 @@</span><br><span> </span><br><span> void mainboard_romstage_entry(struct romstage_params *params);</span><br><span> void romstage_common(struct romstage_params *params);</span><br><span style="color: hsl(0, 100%, 40%);">-void * asmlinkage romstage_main(unsigned long bist, uint32_t tsc_lo,</span><br><span style="color: hsl(120, 100%, 40%);">+void *asmlinkage romstage_main(unsigned long bist, uint32_t tsc_lo,</span><br><span> uint32_t tsc_high);</span><br><span> void asmlinkage romstage_after_car(void);</span><br><span> void raminit(struct mrc_params *mp, int prev_sleep_state);</span><br><span>diff --git a/src/soc/intel/baytrail/romstage/romstage.c b/src/soc/intel/baytrail/romstage/romstage.c</span><br><span>index e38957e..c971b35 100644</span><br><span>--- a/src/soc/intel/baytrail/romstage/romstage.c</span><br><span>+++ b/src/soc/intel/baytrail/romstage/romstage.c</span><br><span>@@ -98,7 +98,7 @@</span><br><span> }</span><br><span> </span><br><span> /* Entry from cache-as-ram.inc. */</span><br><span style="color: hsl(0, 100%, 40%);">-void * asmlinkage romstage_main(unsigned long bist,</span><br><span style="color: hsl(120, 100%, 40%);">+void *asmlinkage romstage_main(unsigned long bist,</span><br><span> uint32_t tsc_low, uint32_t tsc_hi)</span><br><span> {</span><br><span> struct romstage_params rp = {</span><br><span>diff --git a/src/soc/intel/braswell/pmutil.c b/src/soc/intel/braswell/pmutil.c</span><br><span>index 5f078df..00284d1 100644</span><br><span>--- a/src/soc/intel/braswell/pmutil.c</span><br><span>+++ b/src/soc/intel/braswell/pmutil.c</span><br><span>@@ -53,7 +53,7 @@</span><br><span> }</span><br><span> </span><br><span> static void print_num_status_bits(int num_bits, uint32_t status,</span><br><span style="color: hsl(0, 100%, 40%);">- const char * const bit_names[])</span><br><span style="color: hsl(120, 100%, 40%);">+ const char *const bit_names[])</span><br><span> {</span><br><span> int i;</span><br><span> </span><br><span>@@ -72,7 +72,7 @@</span><br><span> </span><br><span> static uint32_t print_smi_status(uint32_t smi_sts)</span><br><span> {</span><br><span style="color: hsl(0, 100%, 40%);">- static const char * const smi_sts_bits[] = {</span><br><span style="color: hsl(120, 100%, 40%);">+ static const char *const smi_sts_bits[] = {</span><br><span> [2] = "BIOS",</span><br><span> [4] = "SLP_SMI",</span><br><span> [5] = "APM",</span><br><span>@@ -157,7 +157,7 @@</span><br><span> </span><br><span> static uint16_t print_pm1_status(uint16_t pm1_sts)</span><br><span> {</span><br><span style="color: hsl(0, 100%, 40%);">- static const char * const pm1_sts_bits[] = {</span><br><span style="color: hsl(120, 100%, 40%);">+ static const char *const pm1_sts_bits[] = {</span><br><span> [0] = "TMROF",</span><br><span> [5] = "GBL",</span><br><span> [8] = "PWRBTN",</span><br><span>@@ -190,7 +190,7 @@</span><br><span> </span><br><span> static uint32_t print_tco_status(uint32_t tco_sts)</span><br><span> {</span><br><span style="color: hsl(0, 100%, 40%);">- static const char * const tco_sts_bits[] = {</span><br><span style="color: hsl(120, 100%, 40%);">+ static const char *const tco_sts_bits[] = {</span><br><span> [3] = "TIMEOUT",</span><br><span> [17] = "SECOND_TO",</span><br><span> };</span><br><span>@@ -252,7 +252,7 @@</span><br><span> </span><br><span> static uint32_t print_gpe_sts(uint32_t gpe_sts)</span><br><span> {</span><br><span style="color: hsl(0, 100%, 40%);">- static const char * const gpe_sts_bits[] = {</span><br><span style="color: hsl(120, 100%, 40%);">+ static const char *const gpe_sts_bits[] = {</span><br><span> [1] = "HOTPLUG",</span><br><span> [2] = "SWGPE",</span><br><span> [3] = "PCIE_WAKE0",</span><br><span>@@ -308,7 +308,7 @@</span><br><span> static uint32_t print_alt_sts(uint32_t alt_gpio_smi)</span><br><span> {</span><br><span> uint32_t alt_gpio_sts;</span><br><span style="color: hsl(0, 100%, 40%);">- static const char * const alt_gpio_smi_sts_bits[] = {</span><br><span style="color: hsl(120, 100%, 40%);">+ static const char *const alt_gpio_smi_sts_bits[] = {</span><br><span> [0] = "SUS_GPIO_0",</span><br><span> [1] = "SUS_GPIO_1",</span><br><span> [2] = "SUS_GPIO_2",</span><br><span>diff --git a/src/soc/intel/braswell/ramstage.c b/src/soc/intel/braswell/ramstage.c</span><br><span>index 3ab1af3..4559739 100644</span><br><span>--- a/src/soc/intel/braswell/ramstage.c</span><br><span>+++ b/src/soc/intel/braswell/ramstage.c</span><br><span>@@ -72,7 +72,7 @@</span><br><span> }</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static const char * const stepping_str[] = {</span><br><span style="color: hsl(120, 100%, 40%);">+static const char *const stepping_str[] = {</span><br><span> "A0", "A1", "B0", "B1", "B2", "B3", "C0"</span><br><span> };</span><br><span> </span><br><span>diff --git a/src/soc/intel/cannonlake/bootblock/report_platform.c b/src/soc/intel/cannonlake/bootblock/report_platform.c</span><br><span>index a2cd864..9d967ce 100644</span><br><span>--- a/src/soc/intel/cannonlake/bootblock/report_platform.c</span><br><span>+++ b/src/soc/intel/cannonlake/bootblock/report_platform.c</span><br><span>@@ -86,7 +86,7 @@</span><br><span> char cpu_string[50], *cpu_name = cpu_string; /* 48 bytes are reported */</span><br><span> int vt, txt, aes;</span><br><span> msr_t microcode_ver;</span><br><span style="color: hsl(0, 100%, 40%);">- static const char * const mode[] = {"NOT ", ""};</span><br><span style="color: hsl(120, 100%, 40%);">+ static const char *const mode[] = {"NOT ", ""};</span><br><span> const char *cpu_type = "Unknown";</span><br><span> u32 p[13];</span><br><span> </span><br><span>diff --git a/src/soc/intel/common/block/include/intelblocks/pmclib.h b/src/soc/intel/common/block/include/intelblocks/pmclib.h</span><br><span>index ddf384b..9b21010 100644</span><br><span>--- a/src/soc/intel/common/block/include/intelblocks/pmclib.h</span><br><span>+++ b/src/soc/intel/common/block/include/intelblocks/pmclib.h</span><br><span>@@ -91,7 +91,7 @@</span><br><span> * names for the TCO status bits. Size of the array is</span><br><span> * returned as an output parameter.</span><br><span> */</span><br><span style="color: hsl(0, 100%, 40%);">-const char * const *soc_tco_sts_array(size_t *a);</span><br><span style="color: hsl(120, 100%, 40%);">+const char *const *soc_tco_sts_array(size_t *a);</span><br><span> </span><br><span> /*</span><br><span> * Resets the tco status registers. This function clears the tco_sts register</span><br><span>@@ -186,14 +186,14 @@</span><br><span> * names for the SMI status register bits. Size of the array is</span><br><span> * returned as an output parameter.</span><br><span> */</span><br><span style="color: hsl(0, 100%, 40%);">-const char * const *soc_smi_sts_array(size_t *a);</span><br><span style="color: hsl(120, 100%, 40%);">+const char *const *soc_smi_sts_array(size_t *a);</span><br><span> </span><br><span> /*</span><br><span> * This function returns array of string which represents</span><br><span> * names for the STD GPE status register bits.</span><br><span> * Size of the array is returned as an output parameter.</span><br><span> */</span><br><span style="color: hsl(0, 100%, 40%);">-const char * const *soc_std_gpe_sts_array(size_t *a);</span><br><span style="color: hsl(120, 100%, 40%);">+const char *const *soc_std_gpe_sts_array(size_t *a);</span><br><span> </span><br><span> /*</span><br><span> * This function gets the gpe0 dwX values from devicetree</span><br><span>diff --git a/src/soc/intel/denverton_ns/pmutil.c b/src/soc/intel/denverton_ns/pmutil.c</span><br><span>index 542997c..78903bb 100644</span><br><span>--- a/src/soc/intel/denverton_ns/pmutil.c</span><br><span>+++ b/src/soc/intel/denverton_ns/pmutil.c</span><br><span>@@ -24,7 +24,7 @@</span><br><span> #include <soc/pm.h></span><br><span> </span><br><span> static void print_num_status_bits(int num_bits, uint32_t status,</span><br><span style="color: hsl(0, 100%, 40%);">- const char * const bit_names[])</span><br><span style="color: hsl(120, 100%, 40%);">+ const char *const bit_names[])</span><br><span> {</span><br><span> int i;</span><br><span> </span><br><span>@@ -43,7 +43,7 @@</span><br><span> </span><br><span> static uint32_t print_smi_status(uint32_t smi_sts)</span><br><span> {</span><br><span style="color: hsl(0, 100%, 40%);">- static const char * const smi_sts_bits[] = {</span><br><span style="color: hsl(120, 100%, 40%);">+ static const char *const smi_sts_bits[] = {</span><br><span> [2] = "BIOS",</span><br><span> [4] = "SLP_SMI",</span><br><span> [5] = "APM",</span><br><span>@@ -129,7 +129,7 @@</span><br><span> </span><br><span> static uint16_t print_pm1_status(uint16_t pm1_sts)</span><br><span> {</span><br><span style="color: hsl(0, 100%, 40%);">- static const char * const pm1_sts_bits[] = {</span><br><span style="color: hsl(120, 100%, 40%);">+ static const char *const pm1_sts_bits[] = {</span><br><span> [0] = "TMROF", [4] = "BM", [5] = "GBL",</span><br><span> [8] = "PWRBTN", [10] = "RTC", [11] = "PRBTNOR",</span><br><span> [15] = "WAK",</span><br><span>@@ -155,7 +155,7 @@</span><br><span> </span><br><span> static uint32_t print_tco_status(uint32_t tco_sts)</span><br><span> {</span><br><span style="color: hsl(0, 100%, 40%);">- static const char * const tco_sts_bits[] = {</span><br><span style="color: hsl(120, 100%, 40%);">+ static const char *const tco_sts_bits[] = {</span><br><span> [0] = "NMI2SMI", [1] = "OS_TCO_SMI",</span><br><span> [2] = "TCO_INIT", [3] = "TIMEOUT",</span><br><span> [7] = "NEWCENTURY ", [8] = "BIOSWR ",</span><br><span>@@ -214,7 +214,7 @@</span><br><span> </span><br><span> static uint32_t print_gpe_sts(uint32_t gpe_sts)</span><br><span> {</span><br><span style="color: hsl(0, 100%, 40%);">- static const char * const gpe_sts_bits[] = {</span><br><span style="color: hsl(120, 100%, 40%);">+ static const char *const gpe_sts_bits[] = {</span><br><span> [0] = "GPIO_0", [1] = "GPIO_1",</span><br><span> [2] = "GPIO_2", [3] = "GPIO_3",</span><br><span> [4] = "GPIO_4", [5] = "GPIO_5",</span><br><span>diff --git a/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c b/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c</span><br><span>index c7c984c..a7268aa 100644</span><br><span>--- a/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c</span><br><span>+++ b/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c</span><br><span>@@ -44,7 +44,7 @@</span><br><span> UPD_DATA_REGION *UpdDataRgnPtr;</span><br><span> VpdDataRgnPtr = (VPD_DATA_REGION *)(UINT32)(FspInfo->CfgRegionOffset + FspInfo->ImageBase);</span><br><span> UpdDataRgnPtr = (UPD_DATA_REGION *)(UINT32)(VpdDataRgnPtr->PcdUpdRegionOffset + FspInfo->ImageBase);</span><br><span style="color: hsl(0, 100%, 40%);">- memcpy((void*)UpdData, (void*)UpdDataRgnPtr, sizeof(UPD_DATA_REGION));</span><br><span style="color: hsl(120, 100%, 40%);">+ memcpy((void *)UpdData, (void *)UpdDataRgnPtr, sizeof(UPD_DATA_REGION));</span><br><span> }</span><br><span> </span><br><span> /* default to just enabling HDMI audio */</span><br><span>diff --git a/src/soc/intel/fsp_broadwell_de/pmutil.c b/src/soc/intel/fsp_broadwell_de/pmutil.c</span><br><span>index bd19104..ccab1ce 100644</span><br><span>--- a/src/soc/intel/fsp_broadwell_de/pmutil.c</span><br><span>+++ b/src/soc/intel/fsp_broadwell_de/pmutil.c</span><br><span>@@ -29,7 +29,7 @@</span><br><span> #include <soc/pci_devs.h></span><br><span> </span><br><span> /* Print status bits with descriptive names */</span><br><span style="color: hsl(0, 100%, 40%);">-static void print_status_bits(u32 status, const char * const bit_names[])</span><br><span style="color: hsl(120, 100%, 40%);">+static void print_status_bits(u32 status, const char *const bit_names[])</span><br><span> {</span><br><span> int i;</span><br><span> </span><br><span>@@ -73,7 +73,7 @@</span><br><span> /* Print PM1 status bits */</span><br><span> static u16 print_pm1_status(u16 pm1_sts)</span><br><span> {</span><br><span style="color: hsl(0, 100%, 40%);">- static const char * const pm1_sts_bits[] = {</span><br><span style="color: hsl(120, 100%, 40%);">+ static const char *const pm1_sts_bits[] = {</span><br><span> [0] = "TMROF",</span><br><span> [4] = "BM",</span><br><span> [5] = "GBL",</span><br><span>@@ -117,7 +117,7 @@</span><br><span> /* Print SMI status bits */</span><br><span> static u32 print_smi_status(u32 smi_sts)</span><br><span> {</span><br><span style="color: hsl(0, 100%, 40%);">- static const char * const smi_sts_bits[] = {</span><br><span style="color: hsl(120, 100%, 40%);">+ static const char *const smi_sts_bits[] = {</span><br><span> [2] = "BIOS",</span><br><span> [3] = "LEGACY_USB",</span><br><span> [4] = "SLP_SMI",</span><br><span>diff --git a/src/soc/intel/skylake/bootblock/report_platform.c b/src/soc/intel/skylake/bootblock/report_platform.c</span><br><span>index 8fd6599..7d5bc3f 100644</span><br><span>--- a/src/soc/intel/skylake/bootblock/report_platform.c</span><br><span>+++ b/src/soc/intel/skylake/bootblock/report_platform.c</span><br><span>@@ -121,7 +121,7 @@</span><br><span> char cpu_string[50], *cpu_name = cpu_string; /* 48 bytes are reported */</span><br><span> int vt, txt, aes;</span><br><span> msr_t microcode_ver;</span><br><span style="color: hsl(0, 100%, 40%);">- static const char * const mode[] = {"NOT ", ""};</span><br><span style="color: hsl(120, 100%, 40%);">+ static const char *const mode[] = {"NOT ", ""};</span><br><span> const char *cpu_type = "Unknown";</span><br><span> </span><br><span> index = 0x80000000;</span><br><span>diff --git a/src/soc/intel/skylake/me.c b/src/soc/intel/skylake/me.c</span><br><span>index a23172e..632749d 100644</span><br><span>--- a/src/soc/intel/skylake/me.c</span><br><span>+++ b/src/soc/intel/skylake/me.c</span><br><span>@@ -34,7 +34,7 @@</span><br><span> }</span><br><span> </span><br><span> /* HFSTS1[3:0] Current Working State Values */</span><br><span style="color: hsl(0, 100%, 40%);">-static const char * const me_cws_values[] = {</span><br><span style="color: hsl(120, 100%, 40%);">+static const char *const me_cws_values[] = {</span><br><span> [ME_HFS_CWS_RESET] = "Reset",</span><br><span> [ME_HFS_CWS_INIT] = "Initializing",</span><br><span> [ME_HFS_CWS_REC] = "Recovery",</span><br><span>@@ -54,7 +54,7 @@</span><br><span> };</span><br><span> </span><br><span> /* HFSTS1[8:6] Current Operation State Values */</span><br><span style="color: hsl(0, 100%, 40%);">-static const char * const me_opstate_values[] = {</span><br><span style="color: hsl(120, 100%, 40%);">+static const char *const me_opstate_values[] = {</span><br><span> [ME_HFS_STATE_PREBOOT] = "Preboot",</span><br><span> [ME_HFS_STATE_M0_UMA] = "M0 with UMA",</span><br><span> [ME_HFS_STATE_M3] = "M3 without UMA",</span><br><span>@@ -64,7 +64,7 @@</span><br><span> };</span><br><span> </span><br><span> /* HFSTS1[19:16] Current Operation Mode Values */</span><br><span style="color: hsl(0, 100%, 40%);">-static const char * const me_opmode_values[] = {</span><br><span style="color: hsl(120, 100%, 40%);">+static const char *const me_opmode_values[] = {</span><br><span> [ME_HFS_MODE_NORMAL] = "Normal",</span><br><span> [ME_HFS_MODE_DEBUG] = "Debug",</span><br><span> [ME_HFS_MODE_DIS] = "Soft Temporary Disable",</span><br><span>@@ -73,7 +73,7 @@</span><br><span> };</span><br><span> </span><br><span> /* HFSTS1[15:12] Error Code Values */</span><br><span style="color: hsl(0, 100%, 40%);">-static const char * const me_error_values[] = {</span><br><span style="color: hsl(120, 100%, 40%);">+static const char *const me_error_values[] = {</span><br><span> [ME_HFS_ERROR_NONE] = "No Error",</span><br><span> [ME_HFS_ERROR_UNCAT] = "Uncategorized Failure",</span><br><span> [ME_HFS_ERROR_IMAGE] = "Image Failure",</span><br><span>@@ -81,7 +81,7 @@</span><br><span> };</span><br><span> </span><br><span> /* HFSTS2[31:28] ME Progress Code */</span><br><span style="color: hsl(0, 100%, 40%);">-static const char * const me_progress_values[] = {</span><br><span style="color: hsl(120, 100%, 40%);">+static const char *const me_progress_values[] = {</span><br><span> [ME_HFS2_PHASE_ROM] = "ROM Phase",</span><br><span> [1] = "Unknown (1)",</span><br><span> [ME_HFS2_PHASE_UKERNEL] = "uKernel Phase",</span><br><span>@@ -94,7 +94,7 @@</span><br><span> };</span><br><span> </span><br><span> /* HFSTS2[27:24] Power Management Event */</span><br><span style="color: hsl(0, 100%, 40%);">-static const char * const me_pmevent_values[] = {</span><br><span style="color: hsl(120, 100%, 40%);">+static const char *const me_pmevent_values[] = {</span><br><span> [ME_HFS2_PMEVENT_CLEAN_MOFF_MX_WAKE] =</span><br><span> "Clean Moff->Mx wake",</span><br><span> [ME_HFS2_PMEVENT_MOFF_MX_WAKE_ERROR] =</span><br><span>@@ -131,13 +131,13 @@</span><br><span> };</span><br><span> </span><br><span> /* Progress Code 0 states */</span><br><span style="color: hsl(0, 100%, 40%);">-static const char * const me_progress_rom_values[] = {</span><br><span style="color: hsl(120, 100%, 40%);">+static const char *const me_progress_rom_values[] = {</span><br><span> [ME_HFS2_STATE_ROM_BEGIN] = "BEGIN",</span><br><span> [ME_HFS2_STATE_ROM_DISABLE] = "DISABLE"</span><br><span> };</span><br><span> </span><br><span> /* Progress Code 1 states */</span><br><span style="color: hsl(0, 100%, 40%);">-static const char * const me_progress_bup_values[] = {</span><br><span style="color: hsl(120, 100%, 40%);">+static const char *const me_progress_bup_values[] = {</span><br><span> [ME_HFS2_STATE_BUP_INIT] =</span><br><span> "Initialization starts",</span><br><span> [ME_HFS2_STATE_BUP_DIS_HOST_WAKE] =</span><br><span>diff --git a/src/soc/nvidia/tegra/dc.h b/src/soc/nvidia/tegra/dc.h</span><br><span>index aed8b99..a9061f8 100644</span><br><span>--- a/src/soc/nvidia/tegra/dc.h</span><br><span>+++ b/src/soc/nvidia/tegra/dc.h</span><br><span>@@ -512,14 +512,14 @@</span><br><span> u32 vmode;</span><br><span> };</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-unsigned long READL(void * p);</span><br><span style="color: hsl(0, 100%, 40%);">-void WRITEL(unsigned long value, void * p);</span><br><span style="color: hsl(120, 100%, 40%);">+unsigned long READL(void *p);</span><br><span style="color: hsl(120, 100%, 40%);">+void WRITEL(unsigned long value, void *p);</span><br><span> </span><br><span> #ifndef __PRE_RAM__</span><br><span> void display_startup(struct device *dev);</span><br><span> #endif</span><br><span style="color: hsl(0, 100%, 40%);">-void dp_init(void * _config);</span><br><span style="color: hsl(0, 100%, 40%);">-void dp_enable(void * _dp);</span><br><span style="color: hsl(120, 100%, 40%);">+void dp_init(void *_config);</span><br><span style="color: hsl(120, 100%, 40%);">+void dp_enable(void *_dp);</span><br><span> unsigned int fb_base_mb(void);</span><br><span> </span><br><span> #endif /* __SOC_NVIDIA_TEGRA_DC_H */</span><br><span>diff --git a/src/soc/nvidia/tegra124/clock.c b/src/soc/nvidia/tegra124/clock.c</span><br><span>index e96a80c..9173e62 100644</span><br><span>--- a/src/soc/nvidia/tegra124/clock.c</span><br><span>+++ b/src/soc/nvidia/tegra124/clock.c</span><br><span>@@ -483,7 +483,7 @@</span><br><span> </span><br><span> void clock_cpu0_config(void *entry)</span><br><span> {</span><br><span style="color: hsl(0, 100%, 40%);">- void * const evp_cpu_reset = (uint8_t *)TEGRA_EVP_BASE + 0x100;</span><br><span style="color: hsl(120, 100%, 40%);">+ void *const evp_cpu_reset = (uint8_t *)TEGRA_EVP_BASE + 0x100;</span><br><span> </span><br><span> write32(&maincpu_stack_pointer, (uintptr_t)_estack);</span><br><span> write32(&maincpu_entry_point, (uintptr_t)entry);</span><br><span>diff --git a/src/soc/nvidia/tegra124/display.c b/src/soc/nvidia/tegra124/display.c</span><br><span>index e66cbbd..febb420 100644</span><br><span>--- a/src/soc/nvidia/tegra124/display.c</span><br><span>+++ b/src/soc/nvidia/tegra124/display.c</span><br><span>@@ -38,7 +38,7 @@</span><br><span> struct tegra_dc dc_data;</span><br><span> </span><br><span> int dump = 0;</span><br><span style="color: hsl(0, 100%, 40%);">-unsigned long READL(void * p)</span><br><span style="color: hsl(120, 100%, 40%);">+unsigned long READL(void *p)</span><br><span> {</span><br><span> unsigned long value;</span><br><span> </span><br><span>@@ -55,7 +55,7 @@</span><br><span> return value;</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-void WRITEL(unsigned long value, void * p)</span><br><span style="color: hsl(120, 100%, 40%);">+void WRITEL(unsigned long value, void *p)</span><br><span> {</span><br><span> if (dump)</span><br><span> printk(BIOS_SPEW, "writel %p %08lx\n", p, value);</span><br><span>diff --git a/src/soc/nvidia/tegra124/dp.c b/src/soc/nvidia/tegra124/dp.c</span><br><span>index 8a316f2..a9b8d7d 100644</span><br><span>--- a/src/soc/nvidia/tegra124/dp.c</span><br><span>+++ b/src/soc/nvidia/tegra124/dp.c</span><br><span>@@ -328,7 +328,7 @@</span><br><span> }</span><br><span> </span><br><span> static int tegra_dc_dp_dpcd_read(struct tegra_dc_dp_data *dp, u32 cmd,</span><br><span style="color: hsl(0, 100%, 40%);">- u8 * data_ptr)</span><br><span style="color: hsl(120, 100%, 40%);">+ u8 *data_ptr)</span><br><span> {</span><br><span> u32 size = 1;</span><br><span> u32 status = 0;</span><br><span>@@ -1356,7 +1356,7 @@</span><br><span> printk(BIOS_SPEW, "%s: configuration updated by EDID.\n", __func__);</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-void dp_init(void * _config)</span><br><span style="color: hsl(120, 100%, 40%);">+void dp_init(void *_config)</span><br><span> {</span><br><span> struct soc_nvidia_tegra124_config *config = (void *)_config;</span><br><span> struct tegra_dc *dc = config->dc_data;</span><br><span>@@ -1406,7 +1406,7 @@</span><br><span> return -1;</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-void dp_enable(void * _dp)</span><br><span style="color: hsl(120, 100%, 40%);">+void dp_enable(void *_dp)</span><br><span> {</span><br><span> struct tegra_dc_dp_data *dp = _dp;</span><br><span> struct tegra_dc *dc = dp->dc;</span><br><span>diff --git a/src/soc/nvidia/tegra124/include/soc/clock.h b/src/soc/nvidia/tegra124/include/soc/clock.h</span><br><span>index 28d1603..d08e26f 100644</span><br><span>--- a/src/soc/nvidia/tegra124/include/soc/clock.h</span><br><span>+++ b/src/soc/nvidia/tegra124/include/soc/clock.h</span><br><span>@@ -290,7 +290,7 @@</span><br><span> void clock_sdram(u32 m, u32 n, u32 p, u32 setup, u32 ph45, u32 ph90,</span><br><span> u32 ph135, u32 kvco, u32 kcp, u32 stable_time, u32 emc_source,</span><br><span> u32 same_freq);</span><br><span style="color: hsl(0, 100%, 40%);">-void clock_cpu0_config(void * entry);</span><br><span style="color: hsl(120, 100%, 40%);">+void clock_cpu0_config(void *entry);</span><br><span> void clock_cpu0_remove_reset(void);</span><br><span> void clock_halt_avp(void);</span><br><span> void clock_enable_clear_reset(u32 l, u32 h, u32 u, u32 v, u32 w, u32 x);</span><br><span>diff --git a/src/soc/nvidia/tegra210/clock.c b/src/soc/nvidia/tegra210/clock.c</span><br><span>index 51cfc8b..6ce2ba1 100644</span><br><span>--- a/src/soc/nvidia/tegra210/clock.c</span><br><span>+++ b/src/soc/nvidia/tegra210/clock.c</span><br><span>@@ -654,7 +654,7 @@</span><br><span> write32(rst_dev_clr_reg, val);</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static u32 * const clk_enb_set_arr[DEV_CONFIG_BLOCKS] = {</span><br><span style="color: hsl(120, 100%, 40%);">+static u32 *const clk_enb_set_arr[DEV_CONFIG_BLOCKS] = {</span><br><span> CLK_RST_REG(clk_enb_l_set),</span><br><span> CLK_RST_REG(clk_enb_h_set),</span><br><span> CLK_RST_REG(clk_enb_u_set),</span><br><span>@@ -664,7 +664,7 @@</span><br><span> CLK_RST_REG(clk_enb_y_set),</span><br><span> };</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static u32 * const clk_enb_clr_arr[DEV_CONFIG_BLOCKS] = {</span><br><span style="color: hsl(120, 100%, 40%);">+static u32 *const clk_enb_clr_arr[DEV_CONFIG_BLOCKS] = {</span><br><span> CLK_RST_REG(clk_enb_l_clr),</span><br><span> CLK_RST_REG(clk_enb_h_clr),</span><br><span> CLK_RST_REG(clk_enb_u_clr),</span><br><span>@@ -674,7 +674,7 @@</span><br><span> CLK_RST_REG(clk_enb_y_clr),</span><br><span> };</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static u32 * const rst_dev_set_arr[DEV_CONFIG_BLOCKS] = {</span><br><span style="color: hsl(120, 100%, 40%);">+static u32 *const rst_dev_set_arr[DEV_CONFIG_BLOCKS] = {</span><br><span> CLK_RST_REG(rst_dev_l_set),</span><br><span> CLK_RST_REG(rst_dev_h_set),</span><br><span> CLK_RST_REG(rst_dev_u_set),</span><br><span>@@ -684,7 +684,7 @@</span><br><span> CLK_RST_REG(rst_dev_y_set),</span><br><span> };</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static u32 * const rst_dev_clr_arr[DEV_CONFIG_BLOCKS] = {</span><br><span style="color: hsl(120, 100%, 40%);">+static u32 *const rst_dev_clr_arr[DEV_CONFIG_BLOCKS] = {</span><br><span> CLK_RST_REG(rst_dev_l_clr),</span><br><span> CLK_RST_REG(rst_dev_h_clr),</span><br><span> CLK_RST_REG(rst_dev_u_clr),</span><br><span>@@ -694,7 +694,7 @@</span><br><span> CLK_RST_REG(rst_dev_y_clr),</span><br><span> };</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void clock_write_regs(u32 * const regs[DEV_CONFIG_BLOCKS],</span><br><span style="color: hsl(120, 100%, 40%);">+static void clock_write_regs(u32 *const regs[DEV_CONFIG_BLOCKS],</span><br><span> u32 bits[DEV_CONFIG_BLOCKS])</span><br><span> {</span><br><span> int i = 0;</span><br><span>diff --git a/src/soc/nvidia/tegra210/dc.c b/src/soc/nvidia/tegra210/dc.c</span><br><span>index b54614f..b892c60 100644</span><br><span>--- a/src/soc/nvidia/tegra210/dc.c</span><br><span>+++ b/src/soc/nvidia/tegra210/dc.c</span><br><span>@@ -23,7 +23,7 @@</span><br><span> #include <soc/display.h></span><br><span> </span><br><span> int dump = 0;</span><br><span style="color: hsl(0, 100%, 40%);">-unsigned long READL(void * p)</span><br><span style="color: hsl(120, 100%, 40%);">+unsigned long READL(void *p)</span><br><span> {</span><br><span> unsigned long value;</span><br><span> </span><br><span>@@ -40,7 +40,7 @@</span><br><span> return value;</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-void WRITEL(unsigned long value, void * p)</span><br><span style="color: hsl(120, 100%, 40%);">+void WRITEL(unsigned long value, void *p)</span><br><span> {</span><br><span> if (dump)</span><br><span> printk(BIOS_SPEW, "writel %p %08lx\n", p, value);</span><br><span>diff --git a/src/soc/nvidia/tegra210/dsi.c b/src/soc/nvidia/tegra210/dsi.c</span><br><span>index 5a9d5a5..532ffc3 100644</span><br><span>--- a/src/soc/nvidia/tegra210/dsi.c</span><br><span>+++ b/src/soc/nvidia/tegra210/dsi.c</span><br><span>@@ -569,7 +569,7 @@</span><br><span> return tegra_mipi_calibrate(dsi->mipi);</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static const char * const error_report[16] = {</span><br><span style="color: hsl(120, 100%, 40%);">+static const char *const error_report[16] = {</span><br><span> "SoT Error",</span><br><span> "SoT Sync Error",</span><br><span> "EoT Sync Error",</span><br><span>diff --git a/src/soc/nvidia/tegra210/flow_ctrl.c b/src/soc/nvidia/tegra210/flow_ctrl.c</span><br><span>index ea5b279..0eb8357 100644</span><br><span>--- a/src/soc/nvidia/tegra210/flow_ctrl.c</span><br><span>+++ b/src/soc/nvidia/tegra210/flow_ctrl.c</span><br><span>@@ -36,7 +36,7 @@</span><br><span> #define FLOW_CTRL_CPU1_CSR 0x18</span><br><span> #define FLOW_CTRL_CC4_CORE0_CTRL 0x6c</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void *tegra_flowctrl_base = (void*)TEGRA_FLOW_BASE;</span><br><span style="color: hsl(120, 100%, 40%);">+static void *tegra_flowctrl_base = (void *)TEGRA_FLOW_BASE;</span><br><span> </span><br><span> static const uint8_t flowctrl_offset_halt_cpu[] = {</span><br><span> FLOW_CTRL_HALT_CPU0_EVENTS,</span><br><span>diff --git a/src/soc/nvidia/tegra210/include/soc/id.h b/src/soc/nvidia/tegra210/include/soc/id.h</span><br><span>index 0903ba9..42b2be6 100644</span><br><span>--- a/src/soc/nvidia/tegra210/include/soc/id.h</span><br><span>+++ b/src/soc/nvidia/tegra210/include/soc/id.h</span><br><span>@@ -23,7 +23,7 @@</span><br><span> static inline int context_avp(void)</span><br><span> {</span><br><span> const uint32_t avp_id = 0xaaaaaaaa;</span><br><span style="color: hsl(0, 100%, 40%);">- void * const uptag = (void *)(uintptr_t)TEGRA_PG_UP_BASE;</span><br><span style="color: hsl(120, 100%, 40%);">+ void *const uptag = (void *)(uintptr_t)TEGRA_PG_UP_BASE;</span><br><span> </span><br><span> return read32(uptag) == avp_id;</span><br><span> }</span><br><span>diff --git a/src/soc/nvidia/tegra210/mtc.c b/src/soc/nvidia/tegra210/mtc.c</span><br><span>index f71e5e8..97eb3de 100644</span><br><span>--- a/src/soc/nvidia/tegra210/mtc.c</span><br><span>+++ b/src/soc/nvidia/tegra210/mtc.c</span><br><span>@@ -31,7 +31,7 @@</span><br><span> struct region_device fh;</span><br><span> struct cbfsf mtc_file;</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- void * const mtc = (void *)(uintptr_t)CONFIG_MTC_ADDRESS;</span><br><span style="color: hsl(120, 100%, 40%);">+ void *const mtc = (void *)(uintptr_t)CONFIG_MTC_ADDRESS;</span><br><span> void *dvfs_table;</span><br><span> size_t (*mtc_fw)(void **dvfs_table) = (void *)mtc;</span><br><span> </span><br><span>diff --git a/src/soc/nvidia/tegra210/power.c b/src/soc/nvidia/tegra210/power.c</span><br><span>index 6b22f5a..cef5b99 100644</span><br><span>--- a/src/soc/nvidia/tegra210/power.c</span><br><span>+++ b/src/soc/nvidia/tegra210/power.c</span><br><span>@@ -36,7 +36,7 @@</span><br><span> return POWER_GATE;</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static const char * const power_gate_string[] = {</span><br><span style="color: hsl(120, 100%, 40%);">+static const char *const power_gate_string[] = {</span><br><span> [POWER_GATE] = "Gat",</span><br><span> [POWER_UNGATE] = "Ungat",</span><br><span> };</span><br><span>diff --git a/src/soc/qualcomm/ipq806x/usb.c b/src/soc/qualcomm/ipq806x/usb.c</span><br><span>index f8f4e4d..3a5b80b 100644</span><br><span>--- a/src/soc/qualcomm/ipq806x/usb.c</span><br><span>+++ b/src/soc/qualcomm/ipq806x/usb.c</span><br><span>@@ -24,7 +24,7 @@</span><br><span> #define CRPORT_RX_OVRD_IN_HI 0x1006</span><br><span> #define CRPORT_TX_ALT_BLOCK 0x102d</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static u32 * const tcsr_usb_sel = (void *)0x1a4000b0;</span><br><span style="color: hsl(120, 100%, 40%);">+static u32 *const tcsr_usb_sel = (void *)0x1a4000b0;</span><br><span> </span><br><span> struct usb_qc_phy {</span><br><span> u32 ipcat;</span><br><span>diff --git a/src/soc/samsung/exynos5250/include/soc/alternate_cbfs.h b/src/soc/samsung/exynos5250/include/soc/alternate_cbfs.h</span><br><span>index 184540c..0833934 100644</span><br><span>--- a/src/soc/samsung/exynos5250/include/soc/alternate_cbfs.h</span><br><span>+++ b/src/soc/samsung/exynos5250/include/soc/alternate_cbfs.h</span><br><span>@@ -17,14 +17,14 @@</span><br><span> #define CPU_SAMSUNG_EXYNOS5250_ALTERNATE_CBFS_H</span><br><span> </span><br><span> /* These are pointers to function pointers. Double indirection! */</span><br><span style="color: hsl(0, 100%, 40%);">-static void * * const irom_sdmmc_read_blocks_ptr = (void * *)0x02020030;</span><br><span style="color: hsl(0, 100%, 40%);">-static void * * const irom_msh_read_from_fifo_emmc_ptr = (void * *)0x02020044;</span><br><span style="color: hsl(0, 100%, 40%);">-static void * * const irom_msh_end_boot_op_emmc_ptr = (void * *)0x02020048;</span><br><span style="color: hsl(0, 100%, 40%);">-static void * * const irom_spi_sf_read_ptr = (void * *)0x02020058;</span><br><span style="color: hsl(0, 100%, 40%);">-static void * * const irom_load_image_from_usb_ptr = (void * *)0x02020070;</span><br><span style="color: hsl(120, 100%, 40%);">+static void **const irom_sdmmc_read_blocks_ptr = (void **)0x02020030;</span><br><span style="color: hsl(120, 100%, 40%);">+static void **const irom_msh_read_from_fifo_emmc_ptr = (void **)0x02020044;</span><br><span style="color: hsl(120, 100%, 40%);">+static void **const irom_msh_end_boot_op_emmc_ptr = (void **)0x02020048;</span><br><span style="color: hsl(120, 100%, 40%);">+static void **const irom_spi_sf_read_ptr = (void **)0x02020058;</span><br><span style="color: hsl(120, 100%, 40%);">+static void **const irom_load_image_from_usb_ptr = (void **)0x02020070;</span><br><span> </span><br><span> #define SECONDARY_BASE_BOOT_USB 0xfeed0002</span><br><span style="color: hsl(0, 100%, 40%);">-static u32 * const iram_secondary_base = (u32 *)0x02020018;</span><br><span style="color: hsl(120, 100%, 40%);">+static u32 *const iram_secondary_base = (u32 *)0x02020018;</span><br><span> </span><br><span> /* Values pulled from U-Boot, I think the manual is wrong here (for SPI) */</span><br><span> #define OM_STAT_SDMMC 0x4</span><br><span>diff --git a/src/soc/samsung/exynos5250/include/soc/power.h b/src/soc/samsung/exynos5250/include/soc/power.h</span><br><span>index dbcc4fe..b5a4c33 100644</span><br><span>--- a/src/soc/samsung/exynos5250/include/soc/power.h</span><br><span>+++ b/src/soc/samsung/exynos5250/include/soc/power.h</span><br><span>@@ -63,7 +63,7 @@</span><br><span> } __packed;</span><br><span> check_member(exynos5_power, ps_hold_ctrl, 0x330c);</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static struct exynos5_power * const exynos_power = (void*)EXYNOS5_POWER_BASE;</span><br><span style="color: hsl(120, 100%, 40%);">+static struct exynos5_power *const exynos_power = (void *)EXYNOS5_POWER_BASE;</span><br><span> </span><br><span> /**</span><br><span> * Perform a software reset.</span><br><span>diff --git a/src/soc/samsung/exynos5420/dp_lowlevel.c b/src/soc/samsung/exynos5420/dp_lowlevel.c</span><br><span>index e955dcd..1fae4d7 100644</span><br><span>--- a/src/soc/samsung/exynos5420/dp_lowlevel.c</span><br><span>+++ b/src/soc/samsung/exynos5420/dp_lowlevel.c</span><br><span>@@ -916,7 +916,7 @@</span><br><span> void exynos_dp_set_lanex_pre_emphasis(unsigned char request_val,</span><br><span> unsigned char lanecnt)</span><br><span> {</span><br><span style="color: hsl(0, 100%, 40%);">- void * reg_list[DP_LANE_CNT_4] = {</span><br><span style="color: hsl(120, 100%, 40%);">+ void *reg_list[DP_LANE_CNT_4] = {</span><br><span> &dp_regs->ln0_link_training_ctl,</span><br><span> &dp_regs->ln1_link_training_ctl,</span><br><span> &dp_regs->ln2_link_training_ctl,</span><br><span>diff --git a/src/soc/samsung/exynos5420/include/soc/alternate_cbfs.h b/src/soc/samsung/exynos5420/include/soc/alternate_cbfs.h</span><br><span>index 4bda93c..40af40b 100644</span><br><span>--- a/src/soc/samsung/exynos5420/include/soc/alternate_cbfs.h</span><br><span>+++ b/src/soc/samsung/exynos5420/include/soc/alternate_cbfs.h</span><br><span>@@ -17,14 +17,14 @@</span><br><span> #define CPU_SAMSUNG_EXYNOS5420_ALTERNATE_CBFS_H</span><br><span> </span><br><span> /* These are pointers to function pointers. Double indirection! */</span><br><span style="color: hsl(0, 100%, 40%);">-static void * * const irom_sdmmc_read_blocks_ptr = (void * *)0x02020030;</span><br><span style="color: hsl(0, 100%, 40%);">-static void * * const irom_msh_read_from_fifo_emmc_ptr = (void * *)0x02020044;</span><br><span style="color: hsl(0, 100%, 40%);">-static void * * const irom_msh_end_boot_op_emmc_ptr = (void * *)0x02020048;</span><br><span style="color: hsl(0, 100%, 40%);">-static void * * const irom_spi_sf_read_ptr = (void * *)0x02020058;</span><br><span style="color: hsl(0, 100%, 40%);">-static void * * const irom_load_image_from_usb_ptr = (void * *)0x02020070;</span><br><span style="color: hsl(120, 100%, 40%);">+static void **const irom_sdmmc_read_blocks_ptr = (void **)0x02020030;</span><br><span style="color: hsl(120, 100%, 40%);">+static void **const irom_msh_read_from_fifo_emmc_ptr = (void **)0x02020044;</span><br><span style="color: hsl(120, 100%, 40%);">+static void **const irom_msh_end_boot_op_emmc_ptr = (void **)0x02020048;</span><br><span style="color: hsl(120, 100%, 40%);">+static void **const irom_spi_sf_read_ptr = (void **)0x02020058;</span><br><span style="color: hsl(120, 100%, 40%);">+static void **const irom_load_image_from_usb_ptr = (void **)0x02020070;</span><br><span> </span><br><span> #define SECONDARY_BASE_BOOT_USB 0xfeed0002</span><br><span style="color: hsl(0, 100%, 40%);">-static u32 * const iram_secondary_base = (u32 *)0x02020018;</span><br><span style="color: hsl(120, 100%, 40%);">+static u32 *const iram_secondary_base = (u32 *)0x02020018;</span><br><span> </span><br><span> /* Values pulled from U-Boot, I think the manual is wrong here (for SPI) */</span><br><span> #define OM_STAT_SDMMC 0x4</span><br><span>diff --git a/src/soc/samsung/exynos5420/include/soc/power.h b/src/soc/samsung/exynos5420/include/soc/power.h</span><br><span>index 4fb96fd..c5709a5 100644</span><br><span>--- a/src/soc/samsung/exynos5420/include/soc/power.h</span><br><span>+++ b/src/soc/samsung/exynos5420/include/soc/power.h</span><br><span>@@ -76,7 +76,7 @@</span><br><span> } __packed;</span><br><span> check_member(exynos5_power, ps_hold_ctrl, 0x330c);</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static struct exynos5_power * const exynos_power = (void*)EXYNOS5_POWER_BASE;</span><br><span style="color: hsl(120, 100%, 40%);">+static struct exynos5_power *const exynos_power = (void *)EXYNOS5_POWER_BASE;</span><br><span> </span><br><span> /**</span><br><span> * Perform a software reset.</span><br><span>diff --git a/src/soc/samsung/exynos5420/smp.c b/src/soc/samsung/exynos5420/smp.c</span><br><span>index 7086da8..4a5c105 100644</span><br><span>--- a/src/soc/samsung/exynos5420/smp.c</span><br><span>+++ b/src/soc/samsung/exynos5420/smp.c</span><br><span>@@ -45,12 +45,12 @@</span><br><span> #define CORE_STATE_SWITCH_CLUSTER (1 << 4)</span><br><span> </span><br><span> /* The default address to re-power on a code. */</span><br><span style="color: hsl(0, 100%, 40%);">-#define CORE_RESET_INIT_ADDRESS ((void*)0x00000000)</span><br><span style="color: hsl(120, 100%, 40%);">+#define CORE_RESET_INIT_ADDRESS ((void *)0x00000000)</span><br><span> </span><br><span> /* Vectors in BL1 (0x02020000 = base of iRAM). */</span><br><span style="color: hsl(0, 100%, 40%);">-#define VECTOR_CORE_SEV_HANDLER ((void*)(intptr_t)0x02020004)</span><br><span style="color: hsl(0, 100%, 40%);">-#define VECTOR_LOW_POWER_FLAG ((void*)(intptr_t)0x02020028)</span><br><span style="color: hsl(0, 100%, 40%);">-#define VECTOR_LOW_POWER_ADDRESS ((void*)(intptr_t)0x0202002C)</span><br><span style="color: hsl(120, 100%, 40%);">+#define VECTOR_CORE_SEV_HANDLER ((void *)(intptr_t)0x02020004)</span><br><span style="color: hsl(120, 100%, 40%);">+#define VECTOR_LOW_POWER_FLAG ((void *)(intptr_t)0x02020028)</span><br><span style="color: hsl(120, 100%, 40%);">+#define VECTOR_LOW_POWER_ADDRESS ((void *)(intptr_t)0x0202002C)</span><br><span> </span><br><span> /* The data structure for the "CPU state" memory page (shared with kernel)</span><br><span> * controlling cores in active cluster. Kernel will put starting address for one</span><br><span>@@ -93,12 +93,12 @@</span><br><span> }</span><br><span> </span><br><span> /* Waits the referenced address to be ready (non-zero) and then jump into it. */</span><br><span style="color: hsl(0, 100%, 40%);">-static void wait_and_jump(volatile uint32_t* reference)</span><br><span style="color: hsl(120, 100%, 40%);">+static void wait_and_jump(volatile uint32_t *reference)</span><br><span> {</span><br><span> while (!*reference) {</span><br><span> wfe();</span><br><span> }</span><br><span style="color: hsl(0, 100%, 40%);">- jump_bx((void*)*reference);</span><br><span style="color: hsl(120, 100%, 40%);">+ jump_bx((void *)*reference);</span><br><span> }</span><br><span> </span><br><span> /* Configures L2 Control Register to use 3 cycles for DATA/TAG RAM latency. */</span><br><span>@@ -127,7 +127,7 @@</span><br><span> </span><br><span> /* Initializes the CPU states to reset state. */</span><br><span> static void init_exynos_cpu_states(void) {</span><br><span style="color: hsl(0, 100%, 40%);">- memset((void*)exynos_cpu_states, 0, sizeof(*exynos_cpu_states));</span><br><span style="color: hsl(120, 100%, 40%);">+ memset((void *)exynos_cpu_states, 0, sizeof(*exynos_cpu_states));</span><br><span> exynos_cpu_states->cpu_states[0] = CORE_STATE_RESET;</span><br><span> exynos_cpu_states->cpu_states[1] = CORE_STATE_SECONDARY_RESET;</span><br><span> exynos_cpu_states->cpu_states[2] = CORE_STATE_SECONDARY_RESET;</span><br><span>@@ -176,7 +176,7 @@</span><br><span> /* Standard Exynos suspend/resume. */</span><br><span> if (exynos_power->inform1) {</span><br><span> exynos_power->inform1 = 0;</span><br><span style="color: hsl(0, 100%, 40%);">- jump_bx((void*)exynos_power->inform0);</span><br><span style="color: hsl(120, 100%, 40%);">+ jump_bx((void *)exynos_power->inform0);</span><br><span> /* never returns. */</span><br><span> }</span><br><span> </span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/27408">change 27408</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/27408"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I21680354f33916b7b4d913f51a842b5d6c2ecef3 </div>
<div style="display:none"> Gerrit-Change-Number: 27408 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Elyes HAOUAS <ehaouas@noos.fr> </div>