<p><a href="https://review.coreboot.org/27407">View Change</a></p><p>33 comments:</p><ul style="list-style: none; padding: 0;"><li style="margin: 0; padding: 0;"><p><a href="https://review.coreboot.org/#/c/27407/1/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h">File src/northbridge/amd/amdmct/mct_ddr3/mct_d.h:</a></p><ul style="list-style: none; padding: 0;"><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/27407/1/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h@1058">Patch Set #1, Line 1058:</a> <code style="font-family:monospace,monospace">void read_dqs_receiver_enable_control_registers(uint16_t *current_total_delay, uint32_t dev, uint8_t dct, uint8_t dimm, uint32_t index_reg);</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/27407/1/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h@1059">Patch Set #1, Line 1059:</a> <code style="font-family:monospace,monospace">void read_dqs_write_timing_control_registers(uint16_t *current_total_delay, uint32_t dev, uint8_t dct, uint8_t dimm, uint32_t index_reg);</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/27407/1/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h@1136">Patch Set #1, Line 1136:</a> <code style="font-family:monospace,monospace">void write_dqs_receiver_enable_control_registers(uint16_t *current_total_delay, uint32_t dev, uint8_t dct, uint8_t dimm, uint32_t index_reg);</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li></ul></li><li style="margin: 0; padding: 0;"><p><a href="https://review.coreboot.org/#/c/27407/1/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c">File src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c:</a></p><ul style="list-style: none; padding: 0;"><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/27407/1/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c@320">Patch Set #1, Line 320:</a> <code style="font-family:monospace,monospace">static void read_dqs_write_data_timing_registers(uint16_t *delay, uint32_t dev, uint8_t dct, uint8_t dimm, uint32_t index_reg)</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/27407/1/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c@349">Patch Set #1, Line 349:</a> <code style="font-family:monospace,monospace">static void write_dqs_write_data_timing_registers(uint16_t *delay, uint32_t dev, uint8_t dct, uint8_t dimm, uint32_t index_reg)</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li></ul></li><li style="margin: 0; padding: 0;"><p><a href="https://review.coreboot.org/#/c/27407/1/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c">File src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c:</a></p><ul style="list-style: none; padding: 0;"><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/27407/1/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c@258">Patch Set #1, Line 258:</a> <code style="font-family:monospace,monospace">void read_dqs_write_timing_control_registers(uint16_t *current_total_delay, uint32_t dev, uint8_t dct, uint8_t dimm, uint32_t index_reg)</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/27407/1/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c@285">Patch Set #1, Line 285:</a> <code style="font-family:monospace,monospace">static void write_dqs_write_timing_control_registers(uint16_t *current_total_delay, uint32_t dev, uint8_t dct, uint8_t dimm, uint32_t index_reg)</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/27407/1/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c@317">Patch Set #1, Line 317:</a> <code style="font-family:monospace,monospace">static void write_write_data_timing_control_registers(uint16_t *current_total_delay, uint32_t dev, uint8_t dct, uint8_t dimm, uint32_t index_reg)</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/27407/1/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c@356">Patch Set #1, Line 356:</a> <code style="font-family:monospace,monospace">void read_dqs_receiver_enable_control_registers(uint16_t *current_total_delay, uint32_t dev, uint8_t dct, uint8_t dimm, uint32_t index_reg)</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/27407/1/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c@390">Patch Set #1, Line 390:</a> <code style="font-family:monospace,monospace">void write_dqs_receiver_enable_control_registers(uint16_t *current_total_delay, uint32_t dev, uint8_t dct, uint8_t dimm, uint32_t index_reg)</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/27407/1/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c@427">Patch Set #1, Line 427:</a> <code style="font-family:monospace,monospace">static void read_dram_phase_recovery_control_registers(uint16_t *current_total_delay, uint32_t dev, uint8_t dct, uint8_t dimm, uint32_t index_reg)</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/27407/1/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c@459">Patch Set #1, Line 459:</a> <code style="font-family:monospace,monospace">static void write_dram_phase_recovery_control_registers(uint16_t *current_total_delay, uint32_t dev, uint8_t dct, uint8_t dimm, uint32_t index_reg)</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/27407/1/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c@497">Patch Set #1, Line 497:</a> <code style="font-family:monospace,monospace">void read_dqs_read_data_timing_registers(uint16_t *delay, uint32_t dev, uint8_t dct, uint8_t dimm, uint32_t index_reg)</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/27407/1/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c@531">Patch Set #1, Line 531:</a> <code style="font-family:monospace,monospace">void write_dqs_read_data_timing_registers(uint16_t *delay, uint32_t dev, uint8_t dct, uint8_t dimm, uint32_t index_reg)</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li></ul></li><li style="margin: 0; padding: 0;"><p><a href="https://review.coreboot.org/#/c/27407/1/src/northbridge/amd/amdmct/mct_ddr3/s3utils.c">File src/northbridge/amd/amdmct/mct_ddr3/s3utils.c:</a></p><ul style="list-style: none; padding: 0;"><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/27407/1/src/northbridge/amd/amdmct/mct_ddr3/s3utils.c@272">Patch Set #1, Line 272:</a> <code style="font-family:monospace,monospace">static void copy_cbmem_spd_data_to_save_variable(struct amd_s3_persistent_data *persistent_data, uint8_t *restored)</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/27407/1/src/northbridge/amd/amdmct/mct_ddr3/s3utils.c@306">Patch Set #1, Line 306:</a> <code style="font-family:monospace,monospace">void copy_mct_data_to_save_variable(struct amd_s3_persistent_data *persistent_data)</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/27407/1/src/northbridge/amd/amdmct/mct_ddr3/s3utils.c@329">Patch Set #1, Line 329:</a> <code style="font-family:monospace,monospace"> struct amd_s3_persistent_mct_channel_data *data = &persistent_data->node[node].channel[channel];</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/27407/1/src/northbridge/amd/amdmct/mct_ddr3/s3utils.c@597">Patch Set #1, Line 597:</a> <code style="font-family:monospace,monospace">void restore_mct_data_from_save_variable(struct amd_s3_persistent_data *persistent_data, uint8_t training_only)</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/27407/1/src/northbridge/amd/amdmct/mct_ddr3/s3utils.c@611">Patch Set #1, Line 611:</a> <code style="font-family:monospace,monospace"> struct amd_s3_persistent_mct_channel_data *data = &persistent_data->node[node].channel[channel];</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/27407/1/src/northbridge/amd/amdmct/mct_ddr3/s3utils.c@655">Patch Set #1, Line 655:</a> <code style="font-family:monospace,monospace"> struct amd_s3_persistent_mct_channel_data *data = &persistent_data->node[node].channel[channel];</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/27407/1/src/northbridge/amd/amdmct/mct_ddr3/s3utils.c@666">Patch Set #1, Line 666:</a> <code style="font-family:monospace,monospace"> struct amd_s3_persistent_mct_channel_data *data = &persistent_data->node[node].channel[channel];</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/27407/1/src/northbridge/amd/amdmct/mct_ddr3/s3utils.c@722">Patch Set #1, Line 722:</a> <code style="font-family:monospace,monospace"> struct amd_s3_persistent_mct_channel_data *data = &persistent_data->node[node].channel[channel];</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/27407/1/src/northbridge/amd/amdmct/mct_ddr3/s3utils.c@761">Patch Set #1, Line 761:</a> <code style="font-family:monospace,monospace"> struct amd_s3_persistent_mct_channel_data *data = &persistent_data->node[node].channel[channel];</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/27407/1/src/northbridge/amd/amdmct/mct_ddr3/s3utils.c@826">Patch Set #1, Line 826:</a> <code style="font-family:monospace,monospace"> struct amd_s3_persistent_mct_channel_data *data = &persistent_data->node[node].channel[channel];</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/27407/1/src/northbridge/amd/amdmct/mct_ddr3/s3utils.c@871">Patch Set #1, Line 871:</a> <code style="font-family:monospace,monospace"> struct amd_s3_persistent_mct_channel_data *data = &persistent_data->node[node].channel[channel];</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/27407/1/src/northbridge/amd/amdmct/mct_ddr3/s3utils.c@912">Patch Set #1, Line 912:</a> <code style="font-family:monospace,monospace"> struct amd_s3_persistent_mct_channel_data *data = &persistent_data->node[node].channel[channel];</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/27407/1/src/northbridge/amd/amdmct/mct_ddr3/s3utils.c@929">Patch Set #1, Line 929:</a> <code style="font-family:monospace,monospace"> struct amd_s3_persistent_mct_channel_data *data = &persistent_data->node[node].channel[channel];</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/27407/1/src/northbridge/amd/amdmct/mct_ddr3/s3utils.c@967">Patch Set #1, Line 967:</a> <code style="font-family:monospace,monospace"> struct amd_s3_persistent_mct_channel_data *data = &persistent_data->node[node].channel[channel];</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/27407/1/src/northbridge/amd/amdmct/mct_ddr3/s3utils.c@986">Patch Set #1, Line 986:</a> <code style="font-family:monospace,monospace"> struct amd_s3_persistent_mct_channel_data *data = &persistent_data->node[node].channel[channel];</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/27407/1/src/northbridge/amd/amdmct/mct_ddr3/s3utils.c@1013">Patch Set #1, Line 1013:</a> <code style="font-family:monospace,monospace"> struct amd_s3_persistent_mct_channel_data *data = &persistent_data->node[node].channel[channel];</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/27407/1/src/northbridge/amd/amdmct/mct_ddr3/s3utils.c@1037">Patch Set #1, Line 1037:</a> <code style="font-family:monospace,monospace"> struct amd_s3_persistent_mct_channel_data *data = &persistent_data->node[node].channel[channel];</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/27407/1/src/northbridge/amd/amdmct/mct_ddr3/s3utils.c@1069">Patch Set #1, Line 1069:</a> <code style="font-family:monospace,monospace"> struct amd_s3_persistent_mct_channel_data *data = &persistent_data->node[node].channel[channel];</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/27407/1/src/northbridge/amd/amdmct/mct_ddr3/s3utils.c@1084">Patch Set #1, Line 1084:</a> <code style="font-family:monospace,monospace"> struct amd_s3_persistent_mct_channel_data *data = &persistent_data->node[node].channel[channel];</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li></ul></li></ul><p>To view, visit <a href="https://review.coreboot.org/27407">change 27407</a>. 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<div style="display:none"> Gerrit-Project: coreboot </div>
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<div style="display:none"> Gerrit-Change-Id: Iaf86a0c91da089b486bd39518e5c8216163bf8ec </div>
<div style="display:none"> Gerrit-Change-Number: 27407 </div>
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<div style="display:none"> Gerrit-Owner: Elyes HAOUAS <ehaouas@noos.fr> </div>
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