<p>Elyes HAOUAS has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/27407">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">src/northbridge: Use "foo *bar" instead of "foo* bar"<br><br>Change-Id: Iaf86a0c91da089b486bd39518e5c8216163bf8ec<br>Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr><br>---<br>M src/northbridge/amd/amdht/h3gtopo.h<br>M src/northbridge/amd/amdht/ht_wrapper.c<br>M src/northbridge/amd/amdmct/mct_ddr3/mct_d.h<br>M src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c<br>M src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c<br>M src/northbridge/amd/amdmct/mct_ddr3/s3utils.c<br>M src/northbridge/amd/pi/agesawrapper.c<br>M src/northbridge/amd/pi/agesawrapper_call.h<br>M src/northbridge/intel/fsp_rangeley/fsp/chipset_fsp_util.c<br>M src/northbridge/intel/fsp_sandybridge/fsp/chipset_fsp_util.c<br>M src/northbridge/intel/gm45/iommu.c<br>M src/northbridge/intel/nehalem/raminit.c<br>M src/northbridge/intel/pineview/raminit.c<br>M src/northbridge/via/vx900/lpc.c<br>14 files changed, 57 insertions(+), 56 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/07/27407/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/northbridge/amd/amdht/h3gtopo.h b/src/northbridge/amd/amdht/h3gtopo.h</span><br><span>index 7baba30..e211d4c 100644</span><br><span>--- a/src/northbridge/amd/amdht/h3gtopo.h</span><br><span>+++ b/src/northbridge/amd/amdht/h3gtopo.h</span><br><span>@@ -324,7 +324,7 @@</span><br><span>  0x00, 0x55, 0x00, 0x55, 0x00, 0x55, 0x00, 0x55, 0x00, 0x65, 0x40, 0x55, 0x00, 0x66, 0x60, 0xFF  // Node7</span><br><span> };</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static const u8 * const amd_topo_list[] = {</span><br><span style="color: hsl(120, 100%, 40%);">+static const u8 *const amd_topo_list[] = {</span><br><span>    amdHtTopologySingleNode,</span><br><span>     amdHtTopologyDualNode,</span><br><span>       amdHtTopologyThreeLine,</span><br><span>diff --git a/src/northbridge/amd/amdht/ht_wrapper.c b/src/northbridge/amd/amdht/ht_wrapper.c</span><br><span>index f4e8337..08ecb4d 100644</span><br><span>--- a/src/northbridge/amd/amdht/ht_wrapper.c</span><br><span>+++ b/src/northbridge/amd/amdht/ht_wrapper.c</span><br><span>@@ -65,7 +65,7 @@</span><br><span> </span><br><span> typedef struct {</span><br><span>     uint32_t code;</span><br><span style="color: hsl(0, 100%, 40%);">-  const char * string;</span><br><span style="color: hsl(120, 100%, 40%);">+  const char *string;</span><br><span> } event_string_decode_t;</span><br><span> </span><br><span> static const event_string_decode_t event_string_decodes[] = {</span><br><span>@@ -90,7 +90,8 @@</span><br><span>     { HT_EVENT_HW_HTCRC, "HT_EVENT_HW_HTCRC" }</span><br><span> };</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static const char * event_string_decode(uint32_t event) {</span><br><span style="color: hsl(120, 100%, 40%);">+static const char *event_string_decode(uint32_t event)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span>   uint32_t i;</span><br><span>  for (i = 0; i < ARRAY_SIZE(event_string_decodes); i++)</span><br><span>            if (event_string_decodes[i].code == event)</span><br><span>diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h</span><br><span>index a02f49b..3cda13f 100644</span><br><span>--- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h</span><br><span>+++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h</span><br><span>@@ -1055,13 +1055,13 @@</span><br><span> void SetDllSpeedUp_D(struct MCTStatStruc *pMCTstat,</span><br><span>                                 struct DCTStatStruc *pDCTstat, u8 dct);</span><br><span> uint8_t get_available_lane_count(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat);</span><br><span style="color: hsl(0, 100%, 40%);">-void read_dqs_receiver_enable_control_registers(uint16_t* current_total_delay, uint32_t dev, uint8_t dct, uint8_t dimm, uint32_t index_reg);</span><br><span style="color: hsl(0, 100%, 40%);">-void read_dqs_write_timing_control_registers(uint16_t* current_total_delay, uint32_t dev, uint8_t dct, uint8_t dimm, uint32_t index_reg);</span><br><span style="color: hsl(120, 100%, 40%);">+void read_dqs_receiver_enable_control_registers(uint16_t *current_total_delay, uint32_t dev, uint8_t dct, uint8_t dimm, uint32_t index_reg);</span><br><span style="color: hsl(120, 100%, 40%);">+void read_dqs_write_timing_control_registers(uint16_t *current_total_delay, uint32_t dev, uint8_t dct, uint8_t dimm, uint32_t index_reg);</span><br><span> void fam15EnableTrainingMode(struct MCTStatStruc *pMCTstat,</span><br><span>              struct DCTStatStruc *pDCTstat, uint8_t dct, uint8_t enable);</span><br><span style="color: hsl(0, 100%, 40%);">-void read_dqs_read_data_timing_registers(uint16_t* delay, uint32_t dev,</span><br><span style="color: hsl(120, 100%, 40%);">+void read_dqs_read_data_timing_registers(uint16_t *delay, uint32_t dev,</span><br><span>                         uint8_t dct, uint8_t dimm, uint32_t index_reg);</span><br><span style="color: hsl(0, 100%, 40%);">-void write_dqs_read_data_timing_registers(uint16_t* delay, uint32_t dev,</span><br><span style="color: hsl(120, 100%, 40%);">+void write_dqs_read_data_timing_registers(uint16_t *delay, uint32_t dev,</span><br><span>                    uint8_t dct, uint8_t dimm, uint32_t index_reg);</span><br><span> void dqsTrainMaxRdLatency_SW_Fam15(struct MCTStatStruc *pMCTstat,</span><br><span>                                 struct DCTStatStruc *pDCTstat);</span><br><span>@@ -1133,7 +1133,7 @@</span><br><span> void read_dram_dqs_training_pattern_fam15(struct MCTStatStruc *pMCTstat,</span><br><span>  struct DCTStatStruc *pDCTstat, uint8_t dct,</span><br><span>  uint8_t Receiver, uint8_t lane, uint8_t stop_on_error);</span><br><span style="color: hsl(0, 100%, 40%);">-void write_dqs_receiver_enable_control_registers(uint16_t* current_total_delay, uint32_t dev, uint8_t dct, uint8_t dimm, uint32_t index_reg);</span><br><span style="color: hsl(120, 100%, 40%);">+void write_dqs_receiver_enable_control_registers(uint16_t *current_total_delay, uint32_t dev, uint8_t dct, uint8_t dimm, uint32_t index_reg);</span><br><span> </span><br><span> uint32_t fenceDynTraining_D(struct MCTStatStruc *pMCTstat,</span><br><span>                        struct DCTStatStruc *pDCTstat, uint8_t dct);</span><br><span>diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c</span><br><span>index 9b74817..0429993 100644</span><br><span>--- a/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c</span><br><span>+++ b/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c</span><br><span>@@ -317,7 +317,7 @@</span><br><span>      pDCTstat->DQSDelay = (u8)DQSDelay;</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void read_dqs_write_data_timing_registers(uint16_t* delay, uint32_t dev, uint8_t dct, uint8_t dimm, uint32_t index_reg)</span><br><span style="color: hsl(120, 100%, 40%);">+static void read_dqs_write_data_timing_registers(uint16_t *delay, uint32_t dev, uint8_t dct, uint8_t dimm, uint32_t index_reg)</span><br><span> {</span><br><span>    uint32_t dword;</span><br><span>      uint32_t mask;</span><br><span>@@ -346,7 +346,7 @@</span><br><span>         delay[8] = dword & mask;</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void write_dqs_write_data_timing_registers(uint16_t* delay, uint32_t dev, uint8_t dct, uint8_t dimm, uint32_t index_reg)</span><br><span style="color: hsl(120, 100%, 40%);">+static void write_dqs_write_data_timing_registers(uint16_t *delay, uint32_t dev, uint8_t dct, uint8_t dimm, uint32_t index_reg)</span><br><span> {</span><br><span>   uint32_t dword;</span><br><span>      uint32_t mask;</span><br><span>diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c b/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c</span><br><span>index 7c3781f..bae2e89 100644</span><br><span>--- a/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c</span><br><span>+++ b/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c</span><br><span>@@ -255,7 +255,7 @@</span><br><span>    return seed;</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-void read_dqs_write_timing_control_registers(uint16_t* current_total_delay, uint32_t dev, uint8_t dct, uint8_t dimm, uint32_t index_reg)</span><br><span style="color: hsl(120, 100%, 40%);">+void read_dqs_write_timing_control_registers(uint16_t *current_total_delay, uint32_t dev, uint8_t dct, uint8_t dimm, uint32_t index_reg)</span><br><span> {</span><br><span>         uint8_t lane;</span><br><span>        uint32_t dword;</span><br><span>@@ -282,7 +282,7 @@</span><br><span> }</span><br><span> </span><br><span> #ifdef UNUSED_CODE</span><br><span style="color: hsl(0, 100%, 40%);">-static void write_dqs_write_timing_control_registers(uint16_t* current_total_delay, uint32_t dev, uint8_t dct, uint8_t dimm, uint32_t index_reg)</span><br><span style="color: hsl(120, 100%, 40%);">+static void write_dqs_write_timing_control_registers(uint16_t *current_total_delay, uint32_t dev, uint8_t dct, uint8_t dimm, uint32_t index_reg)</span><br><span> {</span><br><span>  uint8_t lane;</span><br><span>        uint32_t dword;</span><br><span>@@ -314,7 +314,7 @@</span><br><span> }</span><br><span> #endif</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void write_write_data_timing_control_registers(uint16_t* current_total_delay, uint32_t dev, uint8_t dct, uint8_t dimm, uint32_t index_reg)</span><br><span style="color: hsl(120, 100%, 40%);">+static void write_write_data_timing_control_registers(uint16_t *current_total_delay, uint32_t dev, uint8_t dct, uint8_t dimm, uint32_t index_reg)</span><br><span> {</span><br><span>    uint8_t lane;</span><br><span>        uint32_t dword;</span><br><span>@@ -353,7 +353,7 @@</span><br><span>        }</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-void read_dqs_receiver_enable_control_registers(uint16_t* current_total_delay, uint32_t dev, uint8_t dct, uint8_t dimm, uint32_t index_reg)</span><br><span style="color: hsl(120, 100%, 40%);">+void read_dqs_receiver_enable_control_registers(uint16_t *current_total_delay, uint32_t dev, uint8_t dct, uint8_t dimm, uint32_t index_reg)</span><br><span> {</span><br><span>      uint8_t lane;</span><br><span>        uint32_t mask;</span><br><span>@@ -387,7 +387,7 @@</span><br><span>         }</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-void write_dqs_receiver_enable_control_registers(uint16_t* current_total_delay, uint32_t dev, uint8_t dct, uint8_t dimm, uint32_t index_reg)</span><br><span style="color: hsl(120, 100%, 40%);">+void write_dqs_receiver_enable_control_registers(uint16_t *current_total_delay, uint32_t dev, uint8_t dct, uint8_t dimm, uint32_t index_reg)</span><br><span> {</span><br><span>    uint8_t lane;</span><br><span>        uint32_t mask;</span><br><span>@@ -424,7 +424,7 @@</span><br><span>         }</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void read_dram_phase_recovery_control_registers(uint16_t* current_total_delay, uint32_t dev, uint8_t dct, uint8_t dimm, uint32_t index_reg)</span><br><span style="color: hsl(120, 100%, 40%);">+static void read_dram_phase_recovery_control_registers(uint16_t *current_total_delay, uint32_t dev, uint8_t dct, uint8_t dimm, uint32_t index_reg)</span><br><span> {</span><br><span>        uint8_t lane;</span><br><span>        uint32_t dword;</span><br><span>@@ -456,7 +456,7 @@</span><br><span>        }</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void write_dram_phase_recovery_control_registers(uint16_t* current_total_delay, uint32_t dev, uint8_t dct, uint8_t dimm, uint32_t index_reg)</span><br><span style="color: hsl(120, 100%, 40%);">+static void write_dram_phase_recovery_control_registers(uint16_t *current_total_delay, uint32_t dev, uint8_t dct, uint8_t dimm, uint32_t index_reg)</span><br><span> {</span><br><span>      uint8_t lane;</span><br><span>        uint32_t dword;</span><br><span>@@ -494,7 +494,7 @@</span><br><span>        }</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-void read_dqs_read_data_timing_registers(uint16_t* delay, uint32_t dev, uint8_t dct, uint8_t dimm, uint32_t index_reg)</span><br><span style="color: hsl(120, 100%, 40%);">+void read_dqs_read_data_timing_registers(uint16_t *delay, uint32_t dev, uint8_t dct, uint8_t dimm, uint32_t index_reg)</span><br><span> {</span><br><span>        uint8_t shift;</span><br><span>       uint32_t dword;</span><br><span>@@ -528,7 +528,7 @@</span><br><span>        delay[8] = (dword & mask) >> shift;</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-void write_dqs_read_data_timing_registers(uint16_t* delay, uint32_t dev, uint8_t dct, uint8_t dimm, uint32_t index_reg)</span><br><span style="color: hsl(120, 100%, 40%);">+void write_dqs_read_data_timing_registers(uint16_t *delay, uint32_t dev, uint8_t dct, uint8_t dimm, uint32_t index_reg)</span><br><span> {</span><br><span>  uint8_t shift;</span><br><span>       uint32_t dword;</span><br><span>diff --git a/src/northbridge/amd/amdmct/mct_ddr3/s3utils.c b/src/northbridge/amd/amdmct/mct_ddr3/s3utils.c</span><br><span>index 84e26ea..4c33a2f 100644</span><br><span>--- a/src/northbridge/amd/amdmct/mct_ddr3/s3utils.c</span><br><span>+++ b/src/northbridge/amd/amdmct/mct_ddr3/s3utils.c</span><br><span>@@ -194,11 +194,11 @@</span><br><span>     return ret;</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static struct amd_s3_persistent_data * map_s3nv_in_nvram(void)</span><br><span style="color: hsl(120, 100%, 40%);">+static struct amd_s3_persistent_data *map_s3nv_in_nvram(void)</span><br><span> {</span><br><span>       ssize_t s3nv_offset;</span><br><span>         ssize_t s3nv_file_offset;</span><br><span style="color: hsl(0, 100%, 40%);">-       void * s3nv_cbfs_file_ptr;</span><br><span style="color: hsl(120, 100%, 40%);">+    void *s3nv_cbfs_file_ptr;</span><br><span>    struct amd_s3_persistent_data *persistent_data;</span><br><span> </span><br><span>  /* Obtain CBFS file offset */</span><br><span>@@ -269,7 +269,7 @@</span><br><span>  return pci_read_config32(dev, reg);</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void copy_cbmem_spd_data_to_save_variable(struct amd_s3_persistent_data* persistent_data, uint8_t * restored)</span><br><span style="color: hsl(120, 100%, 40%);">+static void copy_cbmem_spd_data_to_save_variable(struct amd_s3_persistent_data *persistent_data, uint8_t *restored)</span><br><span> {</span><br><span>   uint8_t node;</span><br><span>        uint8_t dimm;</span><br><span>@@ -303,7 +303,7 @@</span><br><span>  }</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-void copy_mct_data_to_save_variable(struct amd_s3_persistent_data* persistent_data)</span><br><span style="color: hsl(120, 100%, 40%);">+void copy_mct_data_to_save_variable(struct amd_s3_persistent_data *persistent_data)</span><br><span> {</span><br><span>      uint8_t i;</span><br><span>   uint8_t j;</span><br><span>@@ -326,7 +326,7 @@</span><br><span>             persistent_data->node[node].node_present = 1;</span><br><span> </span><br><span>                 for (channel = 0; channel < 2; channel++) {</span><br><span style="color: hsl(0, 100%, 40%);">-                  struct amd_s3_persistent_mct_channel_data* data = &persistent_data->node[node].channel[channel];</span><br><span style="color: hsl(120, 100%, 40%);">+                       struct amd_s3_persistent_mct_channel_data *data = &persistent_data->node[node].channel[channel];</span><br><span> </span><br><span>                  /* Stage 1 */</span><br><span>                        data->f2x110 = pci_read_config32(dev_fn2, 0x110);</span><br><span>@@ -594,7 +594,7 @@</span><br><span>   wrmsr(index, msr);</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-void restore_mct_data_from_save_variable(struct amd_s3_persistent_data* persistent_data, uint8_t training_only)</span><br><span style="color: hsl(120, 100%, 40%);">+void restore_mct_data_from_save_variable(struct amd_s3_persistent_data *persistent_data, uint8_t training_only)</span><br><span> {</span><br><span>     uint8_t i;</span><br><span>   uint8_t j;</span><br><span>@@ -608,7 +608,7 @@</span><br><span>             /* Only restore the Receiver Enable and DQS training registers */</span><br><span>            for (node = 0; node < MAX_NODES_SUPPORTED; node++) {</span><br><span>                      for (channel = 0; channel < 2; channel++) {</span><br><span style="color: hsl(0, 100%, 40%);">-                          struct amd_s3_persistent_mct_channel_data* data = &persistent_data->node[node].channel[channel];</span><br><span style="color: hsl(120, 100%, 40%);">+                               struct amd_s3_persistent_mct_channel_data *data = &persistent_data->node[node].channel[channel];</span><br><span>                              if (!persistent_data->node[node].node_present)</span><br><span>                                    continue;</span><br><span> </span><br><span>@@ -652,7 +652,7 @@</span><br><span>  /* Stage 1 */</span><br><span>        for (node = 0; node < MAX_NODES_SUPPORTED; node++) {</span><br><span>              for (channel = 0; channel < 2; channel++) {</span><br><span style="color: hsl(0, 100%, 40%);">-                  struct amd_s3_persistent_mct_channel_data* data = &persistent_data->node[node].channel[channel];</span><br><span style="color: hsl(120, 100%, 40%);">+                       struct amd_s3_persistent_mct_channel_data *data = &persistent_data->node[node].channel[channel];</span><br><span>                      if (!persistent_data->node[node].node_present)</span><br><span>                            continue;</span><br><span> </span><br><span>@@ -663,7 +663,7 @@</span><br><span>  /* Stage 2 */</span><br><span>        for (node = 0; node < MAX_NODES_SUPPORTED; node++) {</span><br><span>              for (channel = 0; channel < 2; channel++) {</span><br><span style="color: hsl(0, 100%, 40%);">-                  struct amd_s3_persistent_mct_channel_data* data = &persistent_data->node[node].channel[channel];</span><br><span style="color: hsl(120, 100%, 40%);">+                       struct amd_s3_persistent_mct_channel_data *data = &persistent_data->node[node].channel[channel];</span><br><span>                      if (!persistent_data->node[node].node_present)</span><br><span>                            continue;</span><br><span> </span><br><span>@@ -719,7 +719,7 @@</span><br><span>  /* Stage 3 */</span><br><span>        for (node = 0; node < MAX_NODES_SUPPORTED; node++) {</span><br><span>              for (channel = 0; channel < 2; channel++) {</span><br><span style="color: hsl(0, 100%, 40%);">-                  struct amd_s3_persistent_mct_channel_data* data = &persistent_data->node[node].channel[channel];</span><br><span style="color: hsl(120, 100%, 40%);">+                       struct amd_s3_persistent_mct_channel_data *data = &persistent_data->node[node].channel[channel];</span><br><span>                      if (!persistent_data->node[node].node_present)</span><br><span>                            continue;</span><br><span> </span><br><span>@@ -758,7 +758,7 @@</span><br><span>  if (is_fam15h()) {</span><br><span>           for (node = 0; node < MAX_NODES_SUPPORTED; node++) {</span><br><span>                      for (channel = 0; channel < 2; channel++) {</span><br><span style="color: hsl(0, 100%, 40%);">-                          struct amd_s3_persistent_mct_channel_data* data = &persistent_data->node[node].channel[channel];</span><br><span style="color: hsl(120, 100%, 40%);">+                               struct amd_s3_persistent_mct_channel_data *data = &persistent_data->node[node].channel[channel];</span><br><span>                              if (!persistent_data->node[node].node_present)</span><br><span>                                    continue;</span><br><span> </span><br><span>@@ -823,7 +823,7 @@</span><br><span>  /* Stage 4 */</span><br><span>        for (node = 0; node < MAX_NODES_SUPPORTED; node++) {</span><br><span>              for (channel = 0; channel < 2; channel++) {</span><br><span style="color: hsl(0, 100%, 40%);">-                  struct amd_s3_persistent_mct_channel_data* data = &persistent_data->node[node].channel[channel];</span><br><span style="color: hsl(120, 100%, 40%);">+                       struct amd_s3_persistent_mct_channel_data *data = &persistent_data->node[node].channel[channel];</span><br><span>                      if (!persistent_data->node[node].node_present)</span><br><span>                            continue;</span><br><span> </span><br><span>@@ -868,7 +868,7 @@</span><br><span>  /* Stage 5 */</span><br><span>        for (node = 0; node < MAX_NODES_SUPPORTED; node++) {</span><br><span>              for (channel = 0; channel < 2; channel++) {</span><br><span style="color: hsl(0, 100%, 40%);">-                  struct amd_s3_persistent_mct_channel_data* data = &persistent_data->node[node].channel[channel];</span><br><span style="color: hsl(120, 100%, 40%);">+                       struct amd_s3_persistent_mct_channel_data *data = &persistent_data->node[node].channel[channel];</span><br><span>                      if (!persistent_data->node[node].node_present)</span><br><span>                            continue;</span><br><span> </span><br><span>@@ -909,7 +909,7 @@</span><br><span>  /* Stage 6 */</span><br><span>        for (node = 0; node < MAX_NODES_SUPPORTED; node++) {</span><br><span>              for (channel = 0; channel < 2; channel++) {</span><br><span style="color: hsl(0, 100%, 40%);">-                  struct amd_s3_persistent_mct_channel_data* data = &persistent_data->node[node].channel[channel];</span><br><span style="color: hsl(120, 100%, 40%);">+                       struct amd_s3_persistent_mct_channel_data *data = &persistent_data->node[node].channel[channel];</span><br><span>                      if (!persistent_data->node[node].node_present)</span><br><span>                            continue;</span><br><span> </span><br><span>@@ -926,7 +926,7 @@</span><br><span>  if (is_fam15h()) {</span><br><span>           for (node = 0; node < MAX_NODES_SUPPORTED; node++) {</span><br><span>                      for (channel = 0; channel < 2; channel++) {</span><br><span style="color: hsl(0, 100%, 40%);">-                          struct amd_s3_persistent_mct_channel_data* data = &persistent_data->node[node].channel[channel];</span><br><span style="color: hsl(120, 100%, 40%);">+                               struct amd_s3_persistent_mct_channel_data *data = &persistent_data->node[node].channel[channel];</span><br><span>                              if (!persistent_data->node[node].node_present)</span><br><span>                                    continue;</span><br><span> </span><br><span>@@ -964,7 +964,7 @@</span><br><span>  /* Stage 7 */</span><br><span>        for (node = 0; node < MAX_NODES_SUPPORTED; node++) {</span><br><span>              for (channel = 0; channel < 2; channel++) {</span><br><span style="color: hsl(0, 100%, 40%);">-                  struct amd_s3_persistent_mct_channel_data* data = &persistent_data->node[node].channel[channel];</span><br><span style="color: hsl(120, 100%, 40%);">+                       struct amd_s3_persistent_mct_channel_data *data = &persistent_data->node[node].channel[channel];</span><br><span>                      if (!persistent_data->node[node].node_present)</span><br><span>                            continue;</span><br><span> </span><br><span>@@ -983,7 +983,7 @@</span><br><span>  /* Stage 8 */</span><br><span>        for (node = 0; node < MAX_NODES_SUPPORTED; node++) {</span><br><span>              for (channel = 0; channel < 2; channel++) {</span><br><span style="color: hsl(0, 100%, 40%);">-                  struct amd_s3_persistent_mct_channel_data* data = &persistent_data->node[node].channel[channel];</span><br><span style="color: hsl(120, 100%, 40%);">+                       struct amd_s3_persistent_mct_channel_data *data = &persistent_data->node[node].channel[channel];</span><br><span>                      if (!persistent_data->node[node].node_present)</span><br><span>                            continue;</span><br><span> </span><br><span>@@ -1010,7 +1010,7 @@</span><br><span>        /* Stage 9 */</span><br><span>        for (node = 0; node < MAX_NODES_SUPPORTED; node++) {</span><br><span>              for (channel = 0; channel < 2; channel++) {</span><br><span style="color: hsl(0, 100%, 40%);">-                  struct amd_s3_persistent_mct_channel_data* data = &persistent_data->node[node].channel[channel];</span><br><span style="color: hsl(120, 100%, 40%);">+                       struct amd_s3_persistent_mct_channel_data *data = &persistent_data->node[node].channel[channel];</span><br><span>                      if (!persistent_data->node[node].node_present)</span><br><span>                            continue;</span><br><span> </span><br><span>@@ -1034,7 +1034,7 @@</span><br><span>        /* Stage 10 */</span><br><span>       for (node = 0; node < MAX_NODES_SUPPORTED; node++) {</span><br><span>              for (channel = 0; channel < 2; channel++) {</span><br><span style="color: hsl(0, 100%, 40%);">-                  struct amd_s3_persistent_mct_channel_data* data = &persistent_data->node[node].channel[channel];</span><br><span style="color: hsl(120, 100%, 40%);">+                       struct amd_s3_persistent_mct_channel_data *data = &persistent_data->node[node].channel[channel];</span><br><span>                      if (!persistent_data->node[node].node_present)</span><br><span>                            continue;</span><br><span> </span><br><span>@@ -1066,7 +1066,7 @@</span><br><span>        if (IS_ENABLED(CONFIG_DIMM_DDR3)) {</span><br><span>          for (node = 0; node < MAX_NODES_SUPPORTED; node++) {</span><br><span>                      for (channel = 0; channel < 2; channel++) {</span><br><span style="color: hsl(0, 100%, 40%);">-                          struct amd_s3_persistent_mct_channel_data* data = &persistent_data->node[node].channel[channel];</span><br><span style="color: hsl(120, 100%, 40%);">+                               struct amd_s3_persistent_mct_channel_data *data = &persistent_data->node[node].channel[channel];</span><br><span>                              if (!persistent_data->node[node].node_present)</span><br><span>                                    continue;</span><br><span> </span><br><span>@@ -1081,7 +1081,7 @@</span><br><span>        /* Other */</span><br><span>  for (node = 0; node < MAX_NODES_SUPPORTED; node++) {</span><br><span>              for (channel = 0; channel < 2; channel++) {</span><br><span style="color: hsl(0, 100%, 40%);">-                  struct amd_s3_persistent_mct_channel_data* data = &persistent_data->node[node].channel[channel];</span><br><span style="color: hsl(120, 100%, 40%);">+                       struct amd_s3_persistent_mct_channel_data *data = &persistent_data->node[node].channel[channel];</span><br><span>                      if (!persistent_data->node[node].node_present)</span><br><span>                            continue;</span><br><span> </span><br><span>diff --git a/src/northbridge/amd/pi/agesawrapper.c b/src/northbridge/amd/pi/agesawrapper.c</span><br><span>index a66917b..67c8a59 100644</span><br><span>--- a/src/northbridge/amd/pi/agesawrapper.c</span><br><span>+++ b/src/northbridge/amd/pi/agesawrapper.c</span><br><span>@@ -289,7 +289,7 @@</span><br><span> </span><br><span> const void *agesawrapper_locate_module (const CHAR8 name[8])</span><br><span> {</span><br><span style="color: hsl(0, 100%, 40%);">-   const void* agesa;</span><br><span style="color: hsl(120, 100%, 40%);">+    const void *agesa;</span><br><span>   const AMD_IMAGE_HEADER* image;</span><br><span>       const AMD_MODULE_HEADER* module;</span><br><span>     size_t file_size;</span><br><span>diff --git a/src/northbridge/amd/pi/agesawrapper_call.h b/src/northbridge/amd/pi/agesawrapper_call.h</span><br><span>index 1ed4a4c..bfcd78d 100644</span><br><span>--- a/src/northbridge/amd/pi/agesawrapper_call.h</span><br><span>+++ b/src/northbridge/amd/pi/agesawrapper_call.h</span><br><span>@@ -30,7 +30,7 @@</span><br><span>  * 0x6 = AGESA_CRITICAL</span><br><span>  * 0x7 = AGESA_FATAL</span><br><span>  */</span><br><span style="color: hsl(0, 100%, 40%);">-static const char * decodeAGESA_STATUS(AGESA_STATUS sret)</span><br><span style="color: hsl(120, 100%, 40%);">+static const char *decodeAGESA_STATUS(AGESA_STATUS sret)</span><br><span> {</span><br><span>         const char *statusStrings[] = { "AGESA_SUCCESS", "AGESA_UNSUPPORTED",</span><br><span>                                    "AGESA_BOUNDS_CHK", "AGESA_ALERT",</span><br><span>diff --git a/src/northbridge/intel/fsp_rangeley/fsp/chipset_fsp_util.c b/src/northbridge/intel/fsp_rangeley/fsp/chipset_fsp_util.c</span><br><span>index ed79f45..999d5a8 100644</span><br><span>--- a/src/northbridge/intel/fsp_rangeley/fsp/chipset_fsp_util.c</span><br><span>+++ b/src/northbridge/intel/fsp_rangeley/fsp/chipset_fsp_util.c</span><br><span>@@ -43,7 +43,7 @@</span><br><span>                  + FspInfo->ImageBase);</span><br><span>    UpdDataRgnPtr = (UPD_DATA_REGION *)(UINT32)</span><br><span>                  (VpdDataRgnPtr->PcdUpdRegionOffset + FspInfo->ImageBase);</span><br><span style="color: hsl(0, 100%, 40%);">- memcpy((void*)UpdData, (void*)UpdDataRgnPtr, sizeof(UPD_DATA_REGION));</span><br><span style="color: hsl(120, 100%, 40%);">+        memcpy((void *)UpdData, (void *)UpdDataRgnPtr, sizeof(UPD_DATA_REGION));</span><br><span> }</span><br><span> </span><br><span> typedef struct northbridge_intel_fsp_rangeley_config config_t;</span><br><span>diff --git a/src/northbridge/intel/fsp_sandybridge/fsp/chipset_fsp_util.c b/src/northbridge/intel/fsp_sandybridge/fsp/chipset_fsp_util.c</span><br><span>index 888da8e..eb31655 100644</span><br><span>--- a/src/northbridge/intel/fsp_sandybridge/fsp/chipset_fsp_util.c</span><br><span>+++ b/src/northbridge/intel/fsp_sandybridge/fsp/chipset_fsp_util.c</span><br><span>@@ -33,7 +33,7 @@</span><br><span>         UPD_DATA_REGION *UpdDataRgnPtr;</span><br><span>      VpdDataRgnPtr = (VPD_DATA_REGION *)(UINT32)(FspInfo->CfgRegionOffset  + FspInfo->ImageBase);</span><br><span>   UpdDataRgnPtr = (UPD_DATA_REGION *)(UINT32)(VpdDataRgnPtr->PcdUpdRegionOffset + FspInfo->ImageBase);</span><br><span style="color: hsl(0, 100%, 40%);">-      memcpy((void*)UpdData, (void*)UpdDataRgnPtr, sizeof(UPD_DATA_REGION));</span><br><span style="color: hsl(120, 100%, 40%);">+        memcpy((void *)UpdData, (void *)UpdDataRgnPtr, sizeof(UPD_DATA_REGION));</span><br><span> }</span><br><span> </span><br><span> static void ConfigureDefaultUpdData(UPD_DATA_REGION   *UpdData)</span><br><span>@@ -70,7 +70,7 @@</span><br><span>     UPD_DATA_REGION *fsp_upd_data = pFspRtBuffer->Common.UpdDataRgnPtr;</span><br><span> #else</span><br><span>      MEM_CONFIG MemoryConfig;</span><br><span style="color: hsl(0, 100%, 40%);">-        memset((void*)&MemoryConfig, 0, sizeof(MEM_CONFIG));</span><br><span style="color: hsl(120, 100%, 40%);">+      memset((void *)&MemoryConfig, 0, sizeof(MEM_CONFIG));</span><br><span> #endif</span><br><span>  FspInitParams->NvsBufferPtr = NULL;</span><br><span> </span><br><span>diff --git a/src/northbridge/intel/gm45/iommu.c b/src/northbridge/intel/gm45/iommu.c</span><br><span>index 77aba94..0108116 100644</span><br><span>--- a/src/northbridge/intel/gm45/iommu.c</span><br><span>+++ b/src/northbridge/intel/gm45/iommu.c</span><br><span>@@ -54,7 +54,7 @@</span><br><span>          u8 cmd = pci_read_config8(igd, PCI_COMMAND);</span><br><span>                 cmd |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;</span><br><span>              pci_write_config8(igd, PCI_COMMAND, cmd);</span><br><span style="color: hsl(0, 100%, 40%);">-               void* bar = (void*)pci_read_config32(igd, PCI_BASE_ADDRESS_0);</span><br><span style="color: hsl(120, 100%, 40%);">+                void *bar = (void *)pci_read_config32(igd, PCI_BASE_ADDRESS_0);</span><br><span> </span><br><span>          /* clear GTT, 2MB is enough (and should be safe) */</span><br><span>          memset(bar, 0, 2<<20);</span><br><span>diff --git a/src/northbridge/intel/nehalem/raminit.c b/src/northbridge/intel/nehalem/raminit.c</span><br><span>index 94d9af8..dcf9b7b 100644</span><br><span>--- a/src/northbridge/intel/nehalem/raminit.c</span><br><span>+++ b/src/northbridge/intel/nehalem/raminit.c</span><br><span>@@ -1786,7 +1786,7 @@</span><br><span>                                       csr.csr.buffer_read_ptr));</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void send_heci_packet(struct mei_header *head, u32 * payload)</span><br><span style="color: hsl(120, 100%, 40%);">+static void send_heci_packet(struct mei_header *head, u32 *payload)</span><br><span> {</span><br><span>     int len = (head->length + 3) / 4;</span><br><span>         int i;</span><br><span>@@ -1803,7 +1803,7 @@</span><br><span> }</span><br><span> </span><br><span> static void</span><br><span style="color: hsl(0, 100%, 40%);">-send_heci_message(u8 * msg, int len, u8 hostaddress, u8 clientaddress)</span><br><span style="color: hsl(120, 100%, 40%);">+send_heci_message(u8 *msg, int len, u8 hostaddress, u8 clientaddress)</span><br><span> {</span><br><span>     struct mei_header head;</span><br><span>      int maxlen;</span><br><span>@@ -1830,8 +1830,8 @@</span><br><span> </span><br><span> /* FIXME: Add timeout.  */</span><br><span> static int</span><br><span style="color: hsl(0, 100%, 40%);">-recv_heci_packet(struct raminfo *info, struct mei_header *head, u32 * packet,</span><br><span style="color: hsl(0, 100%, 40%);">-                 u32 * packet_size)</span><br><span style="color: hsl(120, 100%, 40%);">+recv_heci_packet(struct raminfo *info, struct mei_header *head, u32 *packet,</span><br><span style="color: hsl(120, 100%, 40%);">+              u32 *packet_size)</span><br><span> {</span><br><span>      union {</span><br><span>              struct mei_csr csr;</span><br><span>@@ -1877,7 +1877,7 @@</span><br><span> </span><br><span> /* FIXME: Add timeout.  */</span><br><span> static int</span><br><span style="color: hsl(0, 100%, 40%);">-recv_heci_message(struct raminfo *info, u32 * message, u32 * message_size)</span><br><span style="color: hsl(120, 100%, 40%);">+recv_heci_message(struct raminfo *info, u32 *message, u32 *message_size)</span><br><span> {</span><br><span>         struct mei_header head;</span><br><span>      int current_position;</span><br><span>@@ -2291,9 +2291,9 @@</span><br><span> }</span><br><span> </span><br><span> static void</span><br><span style="color: hsl(0, 100%, 40%);">-do_fsm(enum state *state, u16 * counter,</span><br><span style="color: hsl(0, 100%, 40%);">-       u8 fail_mask, int margin, int uplimit,</span><br><span style="color: hsl(0, 100%, 40%);">-       u8 * res_low, u8 * res_high, u8 val)</span><br><span style="color: hsl(120, 100%, 40%);">+do_fsm(enum state *state, u16 *counter,</span><br><span style="color: hsl(120, 100%, 40%);">+        u8 fail_mask, int margin, int uplimit,</span><br><span style="color: hsl(120, 100%, 40%);">+        u8 *res_low, u8 *res_high, u8 val)</span><br><span> {</span><br><span>      int lane;</span><br><span> </span><br><span>diff --git a/src/northbridge/intel/pineview/raminit.c b/src/northbridge/intel/pineview/raminit.c</span><br><span>index f31f032..66f0a10 100644</span><br><span>--- a/src/northbridge/intel/pineview/raminit.c</span><br><span>+++ b/src/northbridge/intel/pineview/raminit.c</span><br><span>@@ -1845,7 +1845,7 @@</span><br><span>           MCHBAR8(0x5d8) = MCHBAR8(0x5d8) | 0x2;</span><br><span>               hpet_udelay(1);</span><br><span>              barrier();</span><br><span style="color: hsl(0, 100%, 40%);">-              strobedata = read32((void*)strobeaddr);</span><br><span style="color: hsl(120, 100%, 40%);">+               strobedata = read32((void *)strobeaddr);</span><br><span>             barrier();</span><br><span>           hpet_udelay(1);</span><br><span> </span><br><span>diff --git a/src/northbridge/via/vx900/lpc.c b/src/northbridge/via/vx900/lpc.c</span><br><span>index 075a872..b90e2d4 100644</span><br><span>--- a/src/northbridge/via/vx900/lpc.c</span><br><span>+++ b/src/northbridge/via/vx900/lpc.c</span><br><span>@@ -246,7 +246,7 @@</span><br><span> };</span><br><span> </span><br><span> #if IS_ENABLED(CONFIG_PIRQ_ROUTE)</span><br><span style="color: hsl(0, 100%, 40%);">-void pirq_assign_irqs(const u8 * pirq)</span><br><span style="color: hsl(120, 100%, 40%);">+void pirq_assign_irqs(const u8 *pirq)</span><br><span> {</span><br><span>  struct device *lpc;</span><br><span> </span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/27407">change 27407</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/27407"/><meta itemprop="name" content="View Change"/></div></div>

<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: Iaf86a0c91da089b486bd39518e5c8216163bf8ec </div>
<div style="display:none"> Gerrit-Change-Number: 27407 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Elyes HAOUAS <ehaouas@noos.fr> </div>