<p>Felix Held has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/27385">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">superio/winbond: remove LDN-specific ops overrides<br><br>The pnp ops struct is already passed to the pnp_enable_devices function and it<br>is used if no override is supplied in the elements of the pnp_info struct array<br><br>Change-Id: I4311834f3970bd3471f2f5a73ca7da3c03936d37<br>Signed-off-by: Felix Held <felix-coreboot@felixheld.de><br>---<br>M src/superio/winbond/w83627dhg/superio.c<br>M src/superio/winbond/w83627ehg/superio.c<br>M src/superio/winbond/w83627hf/superio.c<br>M src/superio/winbond/w83627thg/superio.c<br>M src/superio/winbond/w83627uhg/superio.c<br>M src/superio/winbond/w83667hg-a/superio.c<br>M src/superio/winbond/w83697hf/superio.c<br>M src/superio/winbond/w83977tf/superio.c<br>M src/superio/winbond/wpcd376i/superio.c<br>9 files changed, 127 insertions(+), 114 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/27385/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/superio/winbond/w83627dhg/superio.c b/src/superio/winbond/w83627dhg/superio.c</span><br><span>index 4907435..23b73a2 100644</span><br><span>--- a/src/superio/winbond/w83627dhg/superio.c</span><br><span>+++ b/src/superio/winbond/w83627dhg/superio.c</span><br><span>@@ -58,21 +58,22 @@</span><br><span> };</span><br><span> </span><br><span> static struct pnp_info pnp_dev_info[] = {</span><br><span style="color: hsl(0, 100%, 40%);">-        { &ops, W83627DHG_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8, },</span><br><span style="color: hsl(0, 100%, 40%);">-    { &ops, W83627DHG_PP,  PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8, },</span><br><span style="color: hsl(0, 100%, 40%);">-    { &ops, W83627DHG_SP1, PNP_IO0 | PNP_IRQ0, 0x07f8, },</span><br><span style="color: hsl(0, 100%, 40%);">-       { &ops, W83627DHG_SP2, PNP_IO0 | PNP_IRQ0, 0x07f8, },</span><br><span style="color: hsl(0, 100%, 40%);">-       { &ops, W83627DHG_KBC, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1, 0x07ff, 0x07ff, },</span><br><span style="color: hsl(0, 100%, 40%);">-  { &ops, W83627DHG_SPI, PNP_IO1, 0, 0x7f8, },</span><br><span style="color: hsl(0, 100%, 40%);">-        { &ops, W83627DHG_GPIO6, },</span><br><span style="color: hsl(0, 100%, 40%);">- { &ops, W83627DHG_WDTO_PLED, },</span><br><span style="color: hsl(0, 100%, 40%);">-     { &ops, W83627DHG_GPIO2, },</span><br><span style="color: hsl(0, 100%, 40%);">- { &ops, W83627DHG_GPIO3, },</span><br><span style="color: hsl(0, 100%, 40%);">- { &ops, W83627DHG_GPIO4, },</span><br><span style="color: hsl(0, 100%, 40%);">- { &ops, W83627DHG_GPIO5, },</span><br><span style="color: hsl(0, 100%, 40%);">- { &ops, W83627DHG_ACPI, PNP_IRQ0, },</span><br><span style="color: hsl(0, 100%, 40%);">-        { &ops, W83627DHG_HWM, PNP_IO0 | PNP_IRQ0, 0x07fe, },</span><br><span style="color: hsl(0, 100%, 40%);">-       { &ops, W83627DHG_PECI_SST, },</span><br><span style="color: hsl(120, 100%, 40%);">+    { NULL, W83627DHG_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8, },</span><br><span style="color: hsl(120, 100%, 40%);">+      { NULL, W83627DHG_PP,  PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8, },</span><br><span style="color: hsl(120, 100%, 40%);">+      { NULL, W83627DHG_SP1, PNP_IO0 | PNP_IRQ0, 0x07f8, },</span><br><span style="color: hsl(120, 100%, 40%);">+ { NULL, W83627DHG_SP2, PNP_IO0 | PNP_IRQ0, 0x07f8, },</span><br><span style="color: hsl(120, 100%, 40%);">+ { NULL, W83627DHG_KBC, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1,</span><br><span style="color: hsl(120, 100%, 40%);">+               0x07ff, 0x07ff, },</span><br><span style="color: hsl(120, 100%, 40%);">+    { NULL, W83627DHG_SPI, PNP_IO1, 0, 0x7f8, },</span><br><span style="color: hsl(120, 100%, 40%);">+  { NULL, W83627DHG_GPIO6, },</span><br><span style="color: hsl(120, 100%, 40%);">+   { NULL, W83627DHG_WDTO_PLED, },</span><br><span style="color: hsl(120, 100%, 40%);">+       { NULL, W83627DHG_GPIO2, },</span><br><span style="color: hsl(120, 100%, 40%);">+   { NULL, W83627DHG_GPIO3, },</span><br><span style="color: hsl(120, 100%, 40%);">+   { NULL, W83627DHG_GPIO4, },</span><br><span style="color: hsl(120, 100%, 40%);">+   { NULL, W83627DHG_GPIO5, },</span><br><span style="color: hsl(120, 100%, 40%);">+   { NULL, W83627DHG_ACPI, PNP_IRQ0, },</span><br><span style="color: hsl(120, 100%, 40%);">+  { NULL, W83627DHG_HWM, PNP_IO0 | PNP_IRQ0, 0x07fe, },</span><br><span style="color: hsl(120, 100%, 40%);">+ { NULL, W83627DHG_PECI_SST, },</span><br><span> };</span><br><span> </span><br><span> static void enable_dev(struct device *dev)</span><br><span>diff --git a/src/superio/winbond/w83627ehg/superio.c b/src/superio/winbond/w83627ehg/superio.c</span><br><span>index 9d1eb3d..db1f98e 100644</span><br><span>--- a/src/superio/winbond/w83627ehg/superio.c</span><br><span>+++ b/src/superio/winbond/w83627ehg/superio.c</span><br><span>@@ -122,24 +122,25 @@</span><br><span> };</span><br><span> </span><br><span> static struct pnp_info pnp_dev_info[] = {</span><br><span style="color: hsl(0, 100%, 40%);">-  { &ops, W83627EHG_FDC,  PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8, },</span><br><span style="color: hsl(0, 100%, 40%);">-   { &ops, W83627EHG_PP,   PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8, },</span><br><span style="color: hsl(0, 100%, 40%);">-   { &ops, W83627EHG_SP1,  PNP_IO0 | PNP_IRQ0, 0x07f8, },</span><br><span style="color: hsl(0, 100%, 40%);">-      { &ops, W83627EHG_SP2,  PNP_IO0 | PNP_IRQ0, 0x07f8, },</span><br><span style="color: hsl(0, 100%, 40%);">-      { &ops, W83627EHG_KBC,  PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1, 0x07ff, 0x07ff, },</span><br><span style="color: hsl(0, 100%, 40%);">- { &ops, W83627EHG_SFI,  PNP_IO0 | PNP_IRQ0, 0x07f8, },</span><br><span style="color: hsl(0, 100%, 40%);">-      { &ops, W83627EHG_WDTO_PLED, },</span><br><span style="color: hsl(0, 100%, 40%);">-     { &ops, W83627EHG_ACPI, PNP_IRQ0, },</span><br><span style="color: hsl(0, 100%, 40%);">-        { &ops, W83627EHG_HWM,  PNP_IO0 | PNP_IRQ0, 0x07fe, },</span><br><span style="color: hsl(120, 100%, 40%);">+    { NULL, W83627EHG_FDC,  PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8, },</span><br><span style="color: hsl(120, 100%, 40%);">+     { NULL, W83627EHG_PP,   PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8, },</span><br><span style="color: hsl(120, 100%, 40%);">+     { NULL, W83627EHG_SP1,  PNP_IO0 | PNP_IRQ0, 0x07f8, },</span><br><span style="color: hsl(120, 100%, 40%);">+        { NULL, W83627EHG_SP2,  PNP_IO0 | PNP_IRQ0, 0x07f8, },</span><br><span style="color: hsl(120, 100%, 40%);">+        { NULL, W83627EHG_KBC,  PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1,</span><br><span style="color: hsl(120, 100%, 40%);">+              0x07ff, 0x07ff, },</span><br><span style="color: hsl(120, 100%, 40%);">+    { NULL, W83627EHG_SFI,  PNP_IO0 | PNP_IRQ0, 0x07f8, },</span><br><span style="color: hsl(120, 100%, 40%);">+        { NULL, W83627EHG_WDTO_PLED, },</span><br><span style="color: hsl(120, 100%, 40%);">+       { NULL, W83627EHG_ACPI, PNP_IRQ0, },</span><br><span style="color: hsl(120, 100%, 40%);">+  { NULL, W83627EHG_HWM,  PNP_IO0 | PNP_IRQ0, 0x07fe, },</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-      { &ops, W83627EHG_GAME, PNP_IO0, 0x07ff, },</span><br><span style="color: hsl(0, 100%, 40%);">- { &ops, W83627EHG_MIDI, PNP_IO1 | PNP_IRQ0, 0, 0x07fe, },</span><br><span style="color: hsl(0, 100%, 40%);">-   { &ops, W83627EHG_GPIO1, },</span><br><span style="color: hsl(0, 100%, 40%);">- { &ops, W83627EHG_GPIO2, },</span><br><span style="color: hsl(0, 100%, 40%);">- { &ops, W83627EHG_GPIO3, },</span><br><span style="color: hsl(0, 100%, 40%);">- { &ops, W83627EHG_GPIO4, },</span><br><span style="color: hsl(0, 100%, 40%);">- { &ops, W83627EHG_GPIO5, },</span><br><span style="color: hsl(0, 100%, 40%);">- { &ops, W83627EHG_GPIO6, },</span><br><span style="color: hsl(120, 100%, 40%);">+       { NULL, W83627EHG_GAME, PNP_IO0, 0x07ff, },</span><br><span style="color: hsl(120, 100%, 40%);">+   { NULL, W83627EHG_MIDI, PNP_IO1 | PNP_IRQ0, 0, 0x07fe, },</span><br><span style="color: hsl(120, 100%, 40%);">+     { NULL, W83627EHG_GPIO1, },</span><br><span style="color: hsl(120, 100%, 40%);">+   { NULL, W83627EHG_GPIO2, },</span><br><span style="color: hsl(120, 100%, 40%);">+   { NULL, W83627EHG_GPIO3, },</span><br><span style="color: hsl(120, 100%, 40%);">+   { NULL, W83627EHG_GPIO4, },</span><br><span style="color: hsl(120, 100%, 40%);">+   { NULL, W83627EHG_GPIO5, },</span><br><span style="color: hsl(120, 100%, 40%);">+   { NULL, W83627EHG_GPIO6, },</span><br><span> };</span><br><span> </span><br><span> static void enable_dev(struct device *dev)</span><br><span>diff --git a/src/superio/winbond/w83627hf/superio.c b/src/superio/winbond/w83627hf/superio.c</span><br><span>index 2ef5a5d..733dc35 100644</span><br><span>--- a/src/superio/winbond/w83627hf/superio.c</span><br><span>+++ b/src/superio/winbond/w83627hf/superio.c</span><br><span>@@ -129,17 +129,19 @@</span><br><span> };</span><br><span> </span><br><span> static struct pnp_info pnp_dev_info[] = {</span><br><span style="color: hsl(0, 100%, 40%);">- { &ops, W83627HF_FDC,  PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8, },</span><br><span style="color: hsl(0, 100%, 40%);">-    { &ops, W83627HF_PP,   PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8, },</span><br><span style="color: hsl(0, 100%, 40%);">-    { &ops, W83627HF_SP1,  PNP_IO0 | PNP_IRQ0, 0x07f8, },</span><br><span style="color: hsl(0, 100%, 40%);">-       { &ops, W83627HF_SP2,  PNP_IO0 | PNP_IRQ0, 0x07f8, },</span><br><span style="color: hsl(0, 100%, 40%);">-       { &ops, W83627HF_KBC,  PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1, 0x07ff, 0x07ff, },</span><br><span style="color: hsl(0, 100%, 40%);">-  { &ops, W83627HF_CIR, PNP_IO0 | PNP_IRQ0, 0x07f8, },</span><br><span style="color: hsl(0, 100%, 40%);">-        { &ops, W83627HF_GAME_MIDI_GPIO1, PNP_IO0 | PNP_IO1 | PNP_IRQ0, 0x07ff, 0x07fe, },</span><br><span style="color: hsl(0, 100%, 40%);">-  { &ops, W83627HF_GPIO2, },</span><br><span style="color: hsl(0, 100%, 40%);">-  { &ops, W83627HF_GPIO3, },</span><br><span style="color: hsl(0, 100%, 40%);">-  { &ops, W83627HF_ACPI, },</span><br><span style="color: hsl(0, 100%, 40%);">-   { &ops, W83627HF_HWM,  PNP_IO0 | PNP_IRQ0, 0x0ff8, },</span><br><span style="color: hsl(120, 100%, 40%);">+     { NULL, W83627HF_FDC,  PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8, },</span><br><span style="color: hsl(120, 100%, 40%);">+      { NULL, W83627HF_PP,   PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8, },</span><br><span style="color: hsl(120, 100%, 40%);">+      { NULL, W83627HF_SP1,  PNP_IO0 | PNP_IRQ0, 0x07f8, },</span><br><span style="color: hsl(120, 100%, 40%);">+ { NULL, W83627HF_SP2,  PNP_IO0 | PNP_IRQ0, 0x07f8, },</span><br><span style="color: hsl(120, 100%, 40%);">+ { NULL, W83627HF_KBC,  PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1,</span><br><span style="color: hsl(120, 100%, 40%);">+               0x07ff, 0x07ff, },</span><br><span style="color: hsl(120, 100%, 40%);">+    { NULL, W83627HF_CIR, PNP_IO0 | PNP_IRQ0, 0x07f8, },</span><br><span style="color: hsl(120, 100%, 40%);">+  { NULL, W83627HF_GAME_MIDI_GPIO1, PNP_IO0 | PNP_IO1 | PNP_IRQ0,</span><br><span style="color: hsl(120, 100%, 40%);">+               0x07ff, 0x07fe, },</span><br><span style="color: hsl(120, 100%, 40%);">+    { NULL, W83627HF_GPIO2, },</span><br><span style="color: hsl(120, 100%, 40%);">+    { NULL, W83627HF_GPIO3, },</span><br><span style="color: hsl(120, 100%, 40%);">+    { NULL, W83627HF_ACPI, },</span><br><span style="color: hsl(120, 100%, 40%);">+     { NULL, W83627HF_HWM,  PNP_IO0 | PNP_IRQ0, 0x0ff8, },</span><br><span> };</span><br><span> </span><br><span> static void enable_dev(struct device *dev)</span><br><span>diff --git a/src/superio/winbond/w83627thg/superio.c b/src/superio/winbond/w83627thg/superio.c</span><br><span>index 3ee75d7..fb6e54d 100644</span><br><span>--- a/src/superio/winbond/w83627thg/superio.c</span><br><span>+++ b/src/superio/winbond/w83627thg/superio.c</span><br><span>@@ -48,16 +48,19 @@</span><br><span> };</span><br><span> </span><br><span> static struct pnp_info pnp_dev_info[] = {</span><br><span style="color: hsl(0, 100%, 40%);">-     { &ops, W83627THG_FDC,   PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8, },</span><br><span style="color: hsl(0, 100%, 40%);">-  { &ops, W83627THG_PP,    PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8, },</span><br><span style="color: hsl(0, 100%, 40%);">-  { &ops, W83627THG_SP1,   PNP_IO0 | PNP_IRQ0, 0x07f8, },</span><br><span style="color: hsl(0, 100%, 40%);">-     { &ops, W83627THG_SP2,   PNP_IO0 | PNP_IRQ0 | PNP_MSC1, 0x07f8, },</span><br><span style="color: hsl(0, 100%, 40%);">-  { &ops, W83627THG_KBC,   PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1 | PNP_MSC0, 0x07ff, 0x07ff, },</span><br><span style="color: hsl(0, 100%, 40%);">-     { &ops, W83627THG_GAME_MIDI_GPIO1, PNP_IO0 | PNP_IO1 | PNP_IRQ0, 0x07ff, 0x07fe, },</span><br><span style="color: hsl(0, 100%, 40%);">- { &ops, W83627THG_GPIO2, },</span><br><span style="color: hsl(0, 100%, 40%);">- { &ops, W83627THG_GPIO3, PNP_EN | PNP_MSC0 | PNP_MSC1, },</span><br><span style="color: hsl(0, 100%, 40%);">-   { &ops, W83627THG_ACPI,  PNP_IRQ0, },</span><br><span style="color: hsl(0, 100%, 40%);">-       { &ops, W83627THG_HWM,   PNP_IO0 | PNP_IRQ0, 0x0ff8, },</span><br><span style="color: hsl(120, 100%, 40%);">+   { NULL, W83627THG_FDC,   PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8, },</span><br><span style="color: hsl(120, 100%, 40%);">+    { NULL, W83627THG_PP,    PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8, },</span><br><span style="color: hsl(120, 100%, 40%);">+    { NULL, W83627THG_SP1,   PNP_IO0 | PNP_IRQ0, 0x07f8, },</span><br><span style="color: hsl(120, 100%, 40%);">+       { NULL, W83627THG_SP2,   PNP_IO0 | PNP_IRQ0 | PNP_MSC1, 0x07f8, },</span><br><span style="color: hsl(120, 100%, 40%);">+    { NULL, W83627THG_KBC,</span><br><span style="color: hsl(120, 100%, 40%);">+                PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1 | PNP_MSC0,</span><br><span style="color: hsl(120, 100%, 40%);">+           0x07ff, 0x07ff, },</span><br><span style="color: hsl(120, 100%, 40%);">+    { NULL, W83627THG_GAME_MIDI_GPIO1, PNP_IO0 | PNP_IO1 | PNP_IRQ0,</span><br><span style="color: hsl(120, 100%, 40%);">+              0x07ff, 0x07fe, },</span><br><span style="color: hsl(120, 100%, 40%);">+    { NULL, W83627THG_GPIO2, },</span><br><span style="color: hsl(120, 100%, 40%);">+   { NULL, W83627THG_GPIO3, PNP_EN | PNP_MSC0 | PNP_MSC1, },</span><br><span style="color: hsl(120, 100%, 40%);">+     { NULL, W83627THG_ACPI,  PNP_IRQ0, },</span><br><span style="color: hsl(120, 100%, 40%);">+ { NULL, W83627THG_HWM,   PNP_IO0 | PNP_IRQ0, 0x0ff8, },</span><br><span> };</span><br><span> </span><br><span> static void enable_dev(struct device *dev)</span><br><span>diff --git a/src/superio/winbond/w83627uhg/superio.c b/src/superio/winbond/w83627uhg/superio.c</span><br><span>index cb7e474..f68aec9 100644</span><br><span>--- a/src/superio/winbond/w83627uhg/superio.c</span><br><span>+++ b/src/superio/winbond/w83627uhg/superio.c</span><br><span>@@ -94,21 +94,22 @@</span><br><span> };</span><br><span> </span><br><span> static struct pnp_info pnp_dev_info[] = {</span><br><span style="color: hsl(0, 100%, 40%);">-   { &ops, W83627UHG_FDC,  PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8, },</span><br><span style="color: hsl(0, 100%, 40%);">-   { &ops, W83627UHG_PP,   PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8, },</span><br><span style="color: hsl(0, 100%, 40%);">-   { &ops, W83627UHG_SP1,  PNP_IO0 | PNP_IRQ0, 0x07f8, },</span><br><span style="color: hsl(0, 100%, 40%);">-      { &ops, W83627UHG_SP2,  PNP_IO0 | PNP_IRQ0, 0x07f8, },</span><br><span style="color: hsl(0, 100%, 40%);">-      { &ops, W83627UHG_KBC,  PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1, 0x07ff, 0x07ff, },</span><br><span style="color: hsl(0, 100%, 40%);">- { &ops, W83627UHG_SP3,  PNP_IO0 | PNP_IRQ0, 0x07f8, },</span><br><span style="color: hsl(0, 100%, 40%);">-      { &ops, W83627UHG_GPIO3_4, },</span><br><span style="color: hsl(0, 100%, 40%);">-       { &ops, W83627UHG_WDTO_PLED_GPIO5_6, },</span><br><span style="color: hsl(0, 100%, 40%);">-     { &ops, W83627UHG_GPIO1_2, },</span><br><span style="color: hsl(0, 100%, 40%);">-       { &ops, W83627UHG_ACPI, PNP_IRQ0, },</span><br><span style="color: hsl(0, 100%, 40%);">-        { &ops, W83627UHG_HWM,  PNP_IO0 | PNP_IRQ0, 0x0ff8, },</span><br><span style="color: hsl(0, 100%, 40%);">-      { &ops, W83627UHG_PECI_SST, },</span><br><span style="color: hsl(0, 100%, 40%);">-      { &ops, W83627UHG_SP4,  PNP_IO0 | PNP_IRQ0, 0x07f8, },</span><br><span style="color: hsl(0, 100%, 40%);">-      { &ops, W83627UHG_SP5,  PNP_IO0 | PNP_IRQ0, 0x07f8, },</span><br><span style="color: hsl(0, 100%, 40%);">-      { &ops, W83627UHG_SP6,  PNP_IO0 | PNP_IRQ0, 0x07f8, },</span><br><span style="color: hsl(120, 100%, 40%);">+    { NULL, W83627UHG_FDC,  PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8, },</span><br><span style="color: hsl(120, 100%, 40%);">+     { NULL, W83627UHG_PP,   PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8, },</span><br><span style="color: hsl(120, 100%, 40%);">+     { NULL, W83627UHG_SP1,  PNP_IO0 | PNP_IRQ0, 0x07f8, },</span><br><span style="color: hsl(120, 100%, 40%);">+        { NULL, W83627UHG_SP2,  PNP_IO0 | PNP_IRQ0, 0x07f8, },</span><br><span style="color: hsl(120, 100%, 40%);">+        { NULL, W83627UHG_KBC,  PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1,</span><br><span style="color: hsl(120, 100%, 40%);">+              0x07ff, 0x07ff, },</span><br><span style="color: hsl(120, 100%, 40%);">+    { NULL, W83627UHG_SP3,  PNP_IO0 | PNP_IRQ0, 0x07f8, },</span><br><span style="color: hsl(120, 100%, 40%);">+        { NULL, W83627UHG_GPIO3_4, },</span><br><span style="color: hsl(120, 100%, 40%);">+ { NULL, W83627UHG_WDTO_PLED_GPIO5_6, },</span><br><span style="color: hsl(120, 100%, 40%);">+       { NULL, W83627UHG_GPIO1_2, },</span><br><span style="color: hsl(120, 100%, 40%);">+ { NULL, W83627UHG_ACPI, PNP_IRQ0, },</span><br><span style="color: hsl(120, 100%, 40%);">+  { NULL, W83627UHG_HWM,  PNP_IO0 | PNP_IRQ0, 0x0ff8, },</span><br><span style="color: hsl(120, 100%, 40%);">+        { NULL, W83627UHG_PECI_SST, },</span><br><span style="color: hsl(120, 100%, 40%);">+        { NULL, W83627UHG_SP4,  PNP_IO0 | PNP_IRQ0, 0x07f8, },</span><br><span style="color: hsl(120, 100%, 40%);">+        { NULL, W83627UHG_SP5,  PNP_IO0 | PNP_IRQ0, 0x07f8, },</span><br><span style="color: hsl(120, 100%, 40%);">+        { NULL, W83627UHG_SP6,  PNP_IO0 | PNP_IRQ0, 0x07f8, },</span><br><span> };</span><br><span> </span><br><span> static void enable_dev(struct device *dev)</span><br><span>diff --git a/src/superio/winbond/w83667hg-a/superio.c b/src/superio/winbond/w83667hg-a/superio.c</span><br><span>index 1a3be44..ceb783d 100644</span><br><span>--- a/src/superio/winbond/w83667hg-a/superio.c</span><br><span>+++ b/src/superio/winbond/w83667hg-a/superio.c</span><br><span>@@ -95,27 +95,28 @@</span><br><span> };</span><br><span> </span><br><span> static struct pnp_info pnp_dev_info[] = {</span><br><span style="color: hsl(0, 100%, 40%);">-        { &ops, W83667HG_A_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x0ff8, },</span><br><span style="color: hsl(0, 100%, 40%);">-   { &ops, W83667HG_A_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x0ff8, },</span><br><span style="color: hsl(0, 100%, 40%);">-    { &ops, W83667HG_A_SP1, PNP_IO0 | PNP_IRQ0, 0x0ff8, },</span><br><span style="color: hsl(0, 100%, 40%);">-      { &ops, W83667HG_A_SP2, PNP_IO0 | PNP_IRQ0, 0x0ff8, },</span><br><span style="color: hsl(0, 100%, 40%);">-      { &ops, W83667HG_A_KBC, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1, 0x0fff, 0x0fff, },</span><br><span style="color: hsl(0, 100%, 40%);">- { &ops, W83667HG_A_SPI1, PNP_IO1, 0, 0x0ff8},</span><br><span style="color: hsl(0, 100%, 40%);">-       { &ops, W83667HG_A_WDT1},</span><br><span style="color: hsl(0, 100%, 40%);">-   { &ops, W83667HG_A_ACPI},</span><br><span style="color: hsl(0, 100%, 40%);">-   { &ops, W83667HG_A_HWM_TSI, PNP_IO0 | PNP_IRQ0, 0x0ffe, },</span><br><span style="color: hsl(0, 100%, 40%);">-  { &ops, W83667HG_A_PECI},</span><br><span style="color: hsl(0, 100%, 40%);">-   { &ops, W83667HG_A_VID_BUSSEL},</span><br><span style="color: hsl(0, 100%, 40%);">-     { &ops, W83667HG_A_GPIO_PP_OD},</span><br><span style="color: hsl(0, 100%, 40%);">-     { &ops, W83667HG_A_GPIO1},</span><br><span style="color: hsl(0, 100%, 40%);">-  { &ops, W83667HG_A_GPIO2},</span><br><span style="color: hsl(0, 100%, 40%);">-  { &ops, W83667HG_A_GPIO3},</span><br><span style="color: hsl(0, 100%, 40%);">-  { &ops, W83667HG_A_GPIO4},</span><br><span style="color: hsl(0, 100%, 40%);">-  { &ops, W83667HG_A_GPIO5},</span><br><span style="color: hsl(0, 100%, 40%);">-  { &ops, W83667HG_A_GPIO6},</span><br><span style="color: hsl(0, 100%, 40%);">-  { &ops, W83667HG_A_GPIO7},</span><br><span style="color: hsl(0, 100%, 40%);">-  { &ops, W83667HG_A_GPIO8},</span><br><span style="color: hsl(0, 100%, 40%);">-  { &ops, W83667HG_A_GPIO9},</span><br><span style="color: hsl(120, 100%, 40%);">+        { NULL, W83667HG_A_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x0ff8, },</span><br><span style="color: hsl(120, 100%, 40%);">+     { NULL, W83667HG_A_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x0ff8, },</span><br><span style="color: hsl(120, 100%, 40%);">+      { NULL, W83667HG_A_SP1, PNP_IO0 | PNP_IRQ0, 0x0ff8, },</span><br><span style="color: hsl(120, 100%, 40%);">+        { NULL, W83667HG_A_SP2, PNP_IO0 | PNP_IRQ0, 0x0ff8, },</span><br><span style="color: hsl(120, 100%, 40%);">+        { NULL, W83667HG_A_KBC, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1,</span><br><span style="color: hsl(120, 100%, 40%);">+              0x0fff, 0x0fff, },</span><br><span style="color: hsl(120, 100%, 40%);">+    { NULL, W83667HG_A_SPI1, PNP_IO1, 0, 0x0ff8},</span><br><span style="color: hsl(120, 100%, 40%);">+ { NULL, W83667HG_A_WDT1},</span><br><span style="color: hsl(120, 100%, 40%);">+     { NULL, W83667HG_A_ACPI},</span><br><span style="color: hsl(120, 100%, 40%);">+     { NULL, W83667HG_A_HWM_TSI, PNP_IO0 | PNP_IRQ0, 0x0ffe, },</span><br><span style="color: hsl(120, 100%, 40%);">+    { NULL, W83667HG_A_PECI},</span><br><span style="color: hsl(120, 100%, 40%);">+     { NULL, W83667HG_A_VID_BUSSEL},</span><br><span style="color: hsl(120, 100%, 40%);">+       { NULL, W83667HG_A_GPIO_PP_OD},</span><br><span style="color: hsl(120, 100%, 40%);">+       { NULL, W83667HG_A_GPIO1},</span><br><span style="color: hsl(120, 100%, 40%);">+    { NULL, W83667HG_A_GPIO2},</span><br><span style="color: hsl(120, 100%, 40%);">+    { NULL, W83667HG_A_GPIO3},</span><br><span style="color: hsl(120, 100%, 40%);">+    { NULL, W83667HG_A_GPIO4},</span><br><span style="color: hsl(120, 100%, 40%);">+    { NULL, W83667HG_A_GPIO5},</span><br><span style="color: hsl(120, 100%, 40%);">+    { NULL, W83667HG_A_GPIO6},</span><br><span style="color: hsl(120, 100%, 40%);">+    { NULL, W83667HG_A_GPIO7},</span><br><span style="color: hsl(120, 100%, 40%);">+    { NULL, W83667HG_A_GPIO8},</span><br><span style="color: hsl(120, 100%, 40%);">+    { NULL, W83667HG_A_GPIO9},</span><br><span> };</span><br><span> </span><br><span> static void enable_dev(struct device *dev)</span><br><span>diff --git a/src/superio/winbond/w83697hf/superio.c b/src/superio/winbond/w83697hf/superio.c</span><br><span>index e5e4e67..0b63cd2 100644</span><br><span>--- a/src/superio/winbond/w83697hf/superio.c</span><br><span>+++ b/src/superio/winbond/w83697hf/superio.c</span><br><span>@@ -77,16 +77,17 @@</span><br><span> };</span><br><span> </span><br><span> static struct pnp_info pnp_dev_info[] = {</span><br><span style="color: hsl(0, 100%, 40%);">-    { &ops, W83697HF_FDC,  PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8, },</span><br><span style="color: hsl(0, 100%, 40%);">-    { &ops, W83697HF_PP,   PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8, },</span><br><span style="color: hsl(0, 100%, 40%);">-    { &ops, W83697HF_SP1,  PNP_IO0 | PNP_IRQ0, 0x07f8, },</span><br><span style="color: hsl(0, 100%, 40%);">-       { &ops, W83697HF_SP2,  PNP_IO0 | PNP_IRQ0, 0x07f8, },</span><br><span style="color: hsl(0, 100%, 40%);">-       { &ops, W83697HF_CIR,  PNP_IO0 | PNP_IRQ0, 0x07f8, },</span><br><span style="color: hsl(0, 100%, 40%);">-       { &ops, W83697HF_GAME_GPIO1, PNP_IO0 | PNP_IO1 | PNP_IRQ0, 0x07ff, 0x07fe, },</span><br><span style="color: hsl(0, 100%, 40%);">-       { &ops, W83697HF_MIDI_GPIO5, },</span><br><span style="color: hsl(0, 100%, 40%);">-     { &ops, W83697HF_GPIO234, },</span><br><span style="color: hsl(0, 100%, 40%);">-        { &ops, W83697HF_ACPI, },</span><br><span style="color: hsl(0, 100%, 40%);">-   { &ops, W83697HF_HWM,  PNP_IO0 | PNP_IRQ0, 0x0ff8, },</span><br><span style="color: hsl(120, 100%, 40%);">+     { NULL, W83697HF_FDC,  PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8, },</span><br><span style="color: hsl(120, 100%, 40%);">+      { NULL, W83697HF_PP,   PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8, },</span><br><span style="color: hsl(120, 100%, 40%);">+      { NULL, W83697HF_SP1,  PNP_IO0 | PNP_IRQ0, 0x07f8, },</span><br><span style="color: hsl(120, 100%, 40%);">+ { NULL, W83697HF_SP2,  PNP_IO0 | PNP_IRQ0, 0x07f8, },</span><br><span style="color: hsl(120, 100%, 40%);">+ { NULL, W83697HF_CIR,  PNP_IO0 | PNP_IRQ0, 0x07f8, },</span><br><span style="color: hsl(120, 100%, 40%);">+ { NULL, W83697HF_GAME_GPIO1, PNP_IO0 | PNP_IO1 | PNP_IRQ0,</span><br><span style="color: hsl(120, 100%, 40%);">+            0x07ff, 0x07fe, },</span><br><span style="color: hsl(120, 100%, 40%);">+    { NULL, W83697HF_MIDI_GPIO5, },</span><br><span style="color: hsl(120, 100%, 40%);">+       { NULL, W83697HF_GPIO234, },</span><br><span style="color: hsl(120, 100%, 40%);">+  { NULL, W83697HF_ACPI, },</span><br><span style="color: hsl(120, 100%, 40%);">+     { NULL, W83697HF_HWM,  PNP_IO0 | PNP_IRQ0, 0x0ff8, },</span><br><span> };</span><br><span> </span><br><span> static void enable_dev(struct device *dev)</span><br><span>diff --git a/src/superio/winbond/w83977tf/superio.c b/src/superio/winbond/w83977tf/superio.c</span><br><span>index 8fb9075..b0c838e 100644</span><br><span>--- a/src/superio/winbond/w83977tf/superio.c</span><br><span>+++ b/src/superio/winbond/w83977tf/superio.c</span><br><span>@@ -49,14 +49,16 @@</span><br><span> };</span><br><span> </span><br><span> static struct pnp_info pnp_dev_info[] = {</span><br><span style="color: hsl(0, 100%, 40%);">- { &ops, W83977TF_FDC,  PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8, },</span><br><span style="color: hsl(0, 100%, 40%);">-    { &ops, W83977TF_PP,   PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8, },</span><br><span style="color: hsl(0, 100%, 40%);">-    { &ops, W83977TF_SP1,  PNP_IO0 | PNP_IRQ0, 0x07f8, },</span><br><span style="color: hsl(0, 100%, 40%);">-       { &ops, W83977TF_SP2,  PNP_IO0 | PNP_IRQ0, 0x07f8, },</span><br><span style="color: hsl(0, 100%, 40%);">-       { &ops, W83977TF_KBC,  PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1, 0x07ff, 0x07ff, },</span><br><span style="color: hsl(0, 100%, 40%);">-  { &ops, W83977TF_CIR,  PNP_IO0 | PNP_IRQ0, 0x07f8, },</span><br><span style="color: hsl(0, 100%, 40%);">-       { &ops, W83977TF_GAME_MIDI_GPIO1, PNP_IO0 | PNP_IO1 | PNP_IRQ0, 0x07ff, 0x07fe, },</span><br><span style="color: hsl(0, 100%, 40%);">-  { &ops, W83977TF_ACPI, PNP_IRQ0, },</span><br><span style="color: hsl(120, 100%, 40%);">+       { NULL, W83977TF_FDC,  PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8, },</span><br><span style="color: hsl(120, 100%, 40%);">+      { NULL, W83977TF_PP,   PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8, },</span><br><span style="color: hsl(120, 100%, 40%);">+      { NULL, W83977TF_SP1,  PNP_IO0 | PNP_IRQ0, 0x07f8, },</span><br><span style="color: hsl(120, 100%, 40%);">+ { NULL, W83977TF_SP2,  PNP_IO0 | PNP_IRQ0, 0x07f8, },</span><br><span style="color: hsl(120, 100%, 40%);">+ { NULL, W83977TF_KBC,  PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1,</span><br><span style="color: hsl(120, 100%, 40%);">+               0x07ff, 0x07ff, },</span><br><span style="color: hsl(120, 100%, 40%);">+    { NULL, W83977TF_CIR,  PNP_IO0 | PNP_IRQ0, 0x07f8, },</span><br><span style="color: hsl(120, 100%, 40%);">+ { NULL, W83977TF_GAME_MIDI_GPIO1, PNP_IO0 | PNP_IO1 | PNP_IRQ0,</span><br><span style="color: hsl(120, 100%, 40%);">+               0x07ff, 0x07fe, },</span><br><span style="color: hsl(120, 100%, 40%);">+    { NULL, W83977TF_ACPI, PNP_IRQ0, },</span><br><span> };</span><br><span> </span><br><span> static void enable_dev(struct device *dev)</span><br><span>diff --git a/src/superio/winbond/wpcd376i/superio.c b/src/superio/winbond/wpcd376i/superio.c</span><br><span>index c18b9e5..7af5bcf 100644</span><br><span>--- a/src/superio/winbond/wpcd376i/superio.c</span><br><span>+++ b/src/superio/winbond/wpcd376i/superio.c</span><br><span>@@ -55,13 +55,14 @@</span><br><span> };</span><br><span> </span><br><span> static struct pnp_info pnp_dev_info[] = {</span><br><span style="color: hsl(0, 100%, 40%);">-   { &ops, WPCD376I_FDC,  PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07fa, },</span><br><span style="color: hsl(0, 100%, 40%);">-    { &ops, WPCD376I_LPT,  PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x04f8, },</span><br><span style="color: hsl(0, 100%, 40%);">-    { &ops, WPCD376I_IR,   PNP_IO0 | PNP_IRQ0 | PNP_DRQ0 | PNP_DRQ1, 0x07f8, },</span><br><span style="color: hsl(0, 100%, 40%);">- { &ops, WPCD376I_SP1,  PNP_IO0 | PNP_IRQ0, 0x07f8, },</span><br><span style="color: hsl(0, 100%, 40%);">-       { &ops, WPCD376I_KBCM, PNP_IRQ0, },</span><br><span style="color: hsl(0, 100%, 40%);">- { &ops, WPCD376I_KBCK, PNP_IO0 | PNP_IO1 | PNP_IRQ0, 0x07f8, 0x07f8, },</span><br><span style="color: hsl(0, 100%, 40%);">-     { &ops, WPCD376I_GPIO, PNP_IO0 | PNP_IRQ0, 0xfff8, },</span><br><span style="color: hsl(120, 100%, 40%);">+     { NULL, WPCD376I_FDC,  PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07fa, },</span><br><span style="color: hsl(120, 100%, 40%);">+      { NULL, WPCD376I_LPT,  PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x04f8, },</span><br><span style="color: hsl(120, 100%, 40%);">+      { NULL, WPCD376I_IR,   PNP_IO0 | PNP_IRQ0 | PNP_DRQ0 | PNP_DRQ1,</span><br><span style="color: hsl(120, 100%, 40%);">+              0x07f8, },</span><br><span style="color: hsl(120, 100%, 40%);">+    { NULL, WPCD376I_SP1,  PNP_IO0 | PNP_IRQ0, 0x07f8, },</span><br><span style="color: hsl(120, 100%, 40%);">+ { NULL, WPCD376I_KBCM, PNP_IRQ0, },</span><br><span style="color: hsl(120, 100%, 40%);">+   { NULL, WPCD376I_KBCK, PNP_IO0 | PNP_IO1 | PNP_IRQ0, 0x07f8, 0x07f8, },</span><br><span style="color: hsl(120, 100%, 40%);">+       { NULL, WPCD376I_GPIO, PNP_IO0 | PNP_IRQ0, 0xfff8, },</span><br><span> };</span><br><span> </span><br><span> static void enable_dev(struct device *dev)</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/27385">change 27385</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/27385"/><meta itemprop="name" content="View Change"/></div></div>

<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I4311834f3970bd3471f2f5a73ca7da3c03936d37 </div>
<div style="display:none"> Gerrit-Change-Number: 27385 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Felix Held <felix-coreboot@felixheld.de> </div>