<p>Rizwan Qureshi has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/27370">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">soc/intel/skylake: [WIP] enable microcode update<br><br>Change-Id: Ic492a8600c7400055ce4b950408f33c6463e0f92<br>Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com><br>---<br>M src/soc/intel/skylake/Kconfig<br>M src/soc/intel/skylake/romstage/romstage_fsp20.c<br>2 files changed, 7 insertions(+), 1 deletion(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/27370/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig</span><br><span>index 3e0158b..fdf78f5 100644</span><br><span>--- a/src/soc/intel/skylake/Kconfig</span><br><span>+++ b/src/soc/intel/skylake/Kconfig</span><br><span>@@ -74,6 +74,8 @@</span><br><span>       select TSC_MONOTONIC_TIMER</span><br><span>   select TSC_SYNC_MFENCE</span><br><span>       select UDELAY_TSC</span><br><span style="color: hsl(120, 100%, 40%);">+     select INTEL_HAS_TOP_SWAP</span><br><span style="color: hsl(120, 100%, 40%);">+     select INTEL_ADD_TOP_SWAP_BOOTBLOCK</span><br><span> </span><br><span> config MAINBOARD_USES_FSP2_0</span><br><span>      bool</span><br><span>@@ -348,5 +350,7 @@</span><br><span> config IFD_CHIPSET</span><br><span>     string</span><br><span>       default "sklkbl"</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(120, 100%, 40%);">+config INTEL_TOP_SWAP_FIT_ENTRY</span><br><span style="color: hsl(120, 100%, 40%);">+   string</span><br><span style="color: hsl(120, 100%, 40%);">+        default "RW_UCODE_STAGED"</span><br><span> endif</span><br><span>diff --git a/src/soc/intel/skylake/romstage/romstage_fsp20.c b/src/soc/intel/skylake/romstage/romstage_fsp20.c</span><br><span>index 64f9d7d..d4d27b1 100644</span><br><span>--- a/src/soc/intel/skylake/romstage/romstage_fsp20.c</span><br><span>+++ b/src/soc/intel/skylake/romstage/romstage_fsp20.c</span><br><span>@@ -38,6 +38,7 @@</span><br><span> #include <string.h></span><br><span> #include <timestamp.h></span><br><span> #include <security/vboot/vboot_common.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/ucode_update.h></span><br><span> </span><br><span> #define FSP_SMBIOS_MEMORY_INFO_GUID        \</span><br><span> {  \</span><br><span>@@ -142,6 +143,7 @@</span><br><span>      struct chipset_power_state *ps;</span><br><span> </span><br><span>  console_init();</span><br><span style="color: hsl(120, 100%, 40%);">+       check_and_update_ucode();</span><br><span> </span><br><span>        /* Program MCHBAR, DMIBAR, GDXBAR and EDRAMBAR */</span><br><span>    systemagent_early_init();</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/27370">change 27370</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/27370"/><meta itemprop="name" content="View Change"/></div></div>

<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: Ic492a8600c7400055ce4b950408f33c6463e0f92 </div>
<div style="display:none"> Gerrit-Change-Number: 27370 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Rizwan Qureshi <rizwan.qureshi@intel.com> </div>